taglinefilesource code
dma_regs97include/asm-sparc/dma.hextern inline void sparc_dma_pause(struct sparc_dma_registers *dma_regs,
dma_regs103include/asm-sparc/dma.hwhile((dma_regs->cond_reg&bit) && (ctr>0)) {
dma_regs121include/asm-sparc/dma.hextern inline void sparc_dma_enable_interrupts(struct sparc_dma_registers *dma_regs)
dma_regs123include/asm-sparc/dma.hdma_regs->cond_reg |= DMA_INT_ENAB;
dma_regs127include/asm-sparc/dma.hextern inline void sparc_dma_disable_interrupts(struct sparc_dma_registers *dma_regs)
dma_regs129include/asm-sparc/dma.hdma_regs->cond_reg &= ~(DMA_INT_ENAB);
dma_regs133include/asm-sparc/dma.hextern inline void sparc_dma_reset(struct sparc_dma_registers *dma_regs)
dma_regs136include/asm-sparc/dma.hsparc_dma_pause(dma_regs, (DMA_FIFO_ISDRAIN));
dma_regs139include/asm-sparc/dma.hdma_regs->cond_reg |= (DMA_RST_SCSI);     /* assert */
dma_regs141include/asm-sparc/dma.hdma_regs->cond_reg &= ~(DMA_RST_SCSI);    /* de-assert */
dma_regs143include/asm-sparc/dma.hsparc_dma_enable_interrupts(dma_regs);    /* Re-enable interrupts */
dma_regs146include/asm-sparc/dma.hif(Sparc_DMA.dma_rev>1) { dma_regs->cond_reg |= DMA_3CLKS; }