![[bottom]](../icons/bottom.png){kind=icon}
![[previous]](../icons/n_left.png){kind=icon}
![[next]](../icons/n_right.png){kind=icon}
![[first]](../icons/n_first.png){kind=icon}
![[last]](../icons/n_last.png){kind=icon}
![[top]](../icons/n_top.png){kind=icon}
![[index]](../icons/index.png){kind=icon}
![[help]](../icons/help.png){kind=icon}
*/
1 /*
2 * NCR 53c{7,8}0x0 driver, header file
3 *
4 * Sponsored by
5 * iX Multiuser Multitasking Magazine
6 * Hannover, Germany
7 * hm@ix.de
8 *
9 * Copyright 1993, Drew Eckhardt
10 * Visionary Computing
11 * (Unix and Linux consulting and custom programming)
12 * drew@Colorado.EDU
13 * +1 (303) 786-7975
14 *
15 * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
16 *
17 * PRE-ALPHA
18 *
19 * For more information, please consult
20 *
21 * NCR 53C700/53C700-66
22 * SCSI I/O Processor
23 * Data Manual
24 *
25 * NCR 53C810
26 * PCI-SCSI I/O Processor
27 * Data Manual
28 *
29 * NCR Microelectronics
30 * 1635 Aeroplaza Drive
31 * Colorado Springs, CO 80916
32 * +1 (719) 578-3400
33 *
34 * Toll free literature number
35 * +1 (800) 334-5454
36 *
37 */
38
39 #ifndef NCR53c7x0_H
40 #define NCR53c7x0_H
41
42 #ifdef __alpha__
43
44 # define ncr_readb(a) ((unsigned int)readb((unsigned long)(a)))
45 # define ncr_readw(a) ((unsigned int)readw((unsigned long)(a)))
46 # define ncr_readl(a) ((unsigned int)readl((unsigned long)(a)))
47 # define ncr_writeb(v,a) (writeb((v), (unsigned long)(a)))
48 # define ncr_writew(v,a) (writew((v), (unsigned long)(a)))
49 # define ncr_writel(v,a) (writel((v), (unsigned long)(a)))
50
51 #else
52
53 # define ncr_readb(a) (*(unsigned char*)(a))
54 # define ncr_readw(a) (*(unsigned short*)(a))
55 # define ncr_readl(a) (*(unsigned int*)(a))
56 # define ncr_writeb(v,a) (*(unsigned char*)(a) = (v))
57 # define ncr_writew(v,a) (*(unsigned short*)(a) = (v))
58 # define ncr_writel(v,a) (*(unsigned int*)(a) = (v))
59
60 #endif
61
62
63 /*
64 * Prevent name space pollution in hosts.c, and only provide the
65 * define we need to get the NCR53c7x0 driver into the host template
66 * array.
67 */
68
69 #if defined(HOSTS_C) || defined(MODULE)
70 #include <linux/scsicam.h>
71 extern int NCR53c7xx_abort(Scsi_Cmnd *);
72 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
73 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
74 extern int NCR53c7xx_reset(Scsi_Cmnd *);
75 #ifdef MODULE
76 extern int NCR53c7xx_release(struct Scsi_Host *);
77 #else
78 #define NCR53c7xx_release NULL
79 #endif
80
81 #define NCR53c7xx {NULL, NULL, "NCR53c{7,8}xx (rel 4)", NCR53c7xx_detect, \
82 NULL, /* info */ NULL, /* command, deprecated */ NULL, \
83 NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset, \
84 NULL /* slave attach */, scsicam_bios_param, /* can queue */ 1, \
85 /* id */ 7, 127 /* old SG_ALL */, /* cmd per lun */ 1 , \
86 /* present */ 0, /* unchecked isa dma */ 0, DISABLE_CLUSTERING}
87 #endif /* defined(HOSTS_C) || defined(MODULE) */
88
89 #ifndef HOSTS_C
90 /* Register addresses, ordered numerically */
91
92
93 /* SCSI control 0 rw, default = 0xc0 */
94 #define SCNTL0_REG 0x00
95 #define SCNTL0_ARB1 0x80 /* 0 0 = simple arbitration */
96 #define SCNTL0_ARB2 0x40 /* 1 1 = full arbitration */
97 #define SCNTL0_STRT 0x20 /* Start Sequence */
98 #define SCNTL0_WATN 0x10 /* Select with ATN */
99 #define SCNTL0_EPC 0x08 /* Enable parity checking */
100 /* Bit 2 is reserved on 800 series chips */
101 #define SCNTL0_EPG_700 0x04 /* Enable parity generation */
102 #define SCNTL0_AAP 0x02 /* ATN/ on parity error */
103 #define SCNTL0_TRG 0x01 /* Target mode */
104
105 /* SCSI control 1 rw, default = 0x00 */
106
107 #define SCNTL1_REG 0x01
108 #define SCNTL1_EXC 0x80 /* Extra Clock Cycle of Data setup */
109 #define SCNTL1_ADB 0x40 /* contents of SODL on bus */
110 #define SCNTL1_ESR_700 0x20 /* Enable SIOP response to selection
111 and reselection */
112 #define SCNTL1_DHP_800 0x20 /* Disable halt on parity error or ATN
113 target mode only */
114 #define SCNTL1_CON 0x10 /* Connected */
115 #define SCNTL1_RST 0x08 /* SCSI RST/ */
116 #define SCNTL1_AESP 0x04 /* Force bad parity */
117 #define SCNTL1_SND_700 0x02 /* Start SCSI send */
118 #define SCNTL1_IARB_800 0x02 /* Immediate Arbitration, start
119 arbitration immediately after
120 busfree is detected */
121 #define SCNTL1_RCV_700 0x01 /* Start SCSI receive */
122 #define SCNTL1_SST_800 0x01 /* Start SCSI transfer */
123
124 /* SCSI control 2 rw, */
125
126 #define SCNTL2_REG_800 0x02
127 #define SCNTL2_800_SDU 0x80 /* SCSI disconnect unexpected */
128
129 /* SCSI control 3 rw */
130
131 #define SCNTL3_REG_800 0x03
132 #define SCNTL3_800_SCF_SHIFT 4
133 #define SCNTL3_800_SCF_MASK 0x70
134 #define SCNTL3_800_SCF2 0x40 /* Synchronous divisor */
135 #define SCNTL3_800_SCF1 0x20 /* 0x00 = SCLK/3 */
136 #define SCNTL3_800_SCF0 0x10 /* 0x10 = SCLK/1 */
137 /* 0x20 = SCLK/1.5
138 0x30 = SCLK/2
139 0x40 = SCLK/3 */
140
141 #define SCNTL3_800_CCF_SHIFT 0
142 #define SCNTL3_800_CCF_MASK 0x07
143 #define SCNTL3_800_CCF2 0x04 /* 0x00 50.01 to 66 */
144 #define SCNTL3_800_CCF1 0x02 /* 0x01 16.67 to 25 */
145 #define SCNTL3_800_CCF0 0x01 /* 0x02 25.01 - 37.5
146 0x03 37.51 - 50
147 0x04 50.01 - 66 */
148
149 /*
150 * SCSI destination ID rw - the appropriate bit is set for the selected
151 * target ID. This is written by the SCSI SCRIPTS processor.
152 * default = 0x00
153 */
154 #define SDID_REG_700 0x02
155 #define SDID_REG_800 0x06
156
157 #define GP_REG_800 0x07 /* General purpose IO */
158 #define GP_800_IO1 0x02
159 #define GP_800_IO2 0x01
160
161
162 /* SCSI interrupt enable rw, default = 0x00 */
163 #define SIEN_REG_700 0x03
164 #define SIEN0_REG_800 0x40
165 #define SIEN_MA 0x80 /* Phase mismatch (ini) or ATN (tgt) */
166 #define SIEN_FC 0x40 /* Function complete */
167 #define SIEN_700_STO 0x20 /* Selection or reselection timeout */
168 #define SIEN_800_SEL 0x20 /* Selected */
169 #define SIEN_700_SEL 0x10 /* Selected or reselected */
170 #define SIEN_800_RESEL 0x10 /* Reselected */
171 #define SIEN_SGE 0x08 /* SCSI gross error */
172 #define SIEN_UDC 0x04 /* Unexpected disconnect */
173 #define SIEN_RST 0x02 /* SCSI RST/ received */
174 #define SIEN_PAR 0x01 /* Parity error */
175
176 /*
177 * SCSI chip ID rw
178 * NCR53c700 :
179 * When arbitrating, the highest bit is used, when reselection or selection
180 * occurs, the chip responds to all IDs for which a bit is set.
181 * default = 0x00
182 * NCR53c810 :
183 * Uses bit mapping
184 */
185 #define SCID_REG 0x04
186 /* Bit 7 is reserved on 800 series chips */
187 #define SCID_800_RRE 0x40 /* Enable response to reselection */
188 #define SCID_800_SRE 0x20 /* Enable response to selection */
189 /* Bits four and three are reserved on 800 series chips */
190 #define SCID_800_ENC_MASK 0x07 /* Encoded SCSI ID */
191
192 /* SCSI transfer rw, default = 0x00 */
193 #define SXFER_REG 0x05
194 #define SXFER_DHP 0x80 /* Disable halt on parity */
195
196 #define SXFER_TP2 0x40 /* Transfer period msb */
197 #define SXFER_TP1 0x20
198 #define SXFER_TP0 0x10 /* lsb */
199 #define SXFER_TP_MASK 0x70
200 #define SXFER_TP_SHIFT 4
201 #define SXFER_TP_4 0x00 /* Divisors */
202 #define SXFER_TP_5 0x10
203 #define SXFER_TP_6 0x20
204 #define SXFER_TP_7 0x30
205 #define SXFER_TP_8 0x40
206 #define SXFER_TP_9 0x50
207 #define SXFER_TP_10 0x60
208 #define SXFER_TP_11 0x70
209
210 #define SXFER_MO3 0x08 /* Max offset msb */
211 #define SXFER_MO2 0x04
212 #define SXFER_MO1 0x02
213 #define SXFER_MO0 0x01 /* lsb */
214 #define SXFER_MO_MASK 0x0f
215 #define SXFER_MO_SHIFT 0
216
217 /*
218 * SCSI output data latch rw
219 * The contents of this register are driven onto the SCSI bus when
220 * the Assert Data Bus bit of the SCNTL1 register is set and
221 * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
222 */
223 #define SODL_REG_700 0x06
224 #define SODL_REG_800 0x54
225
226
227 /*
228 * SCSI output control latch rw, default = 0
229 * Note that when the chip is being manually programmed as an initiator,
230 * the MSG, CD, and IO bits must be set correctly for the phase the target
231 * is driving the bus in. Otherwise no data transfer will occur due to
232 * phase mismatch.
233 */
234
235 #define SBCL_REG 0x0b
236 #define SBCL_REQ 0x80 /* REQ */
237 #define SBCL_ACK 0x40 /* ACK */
238 #define SBCL_BSY 0x20 /* BSY */
239 #define SBCL_SEL 0x10 /* SEL */
240 #define SBCL_ATN 0x08 /* ATN */
241 #define SBCL_MSG 0x04 /* MSG */
242 #define SBCL_CD 0x02 /* C/D */
243 #define SBCL_IO 0x01 /* I/O */
244 #define SBCL_PHASE_CMDOUT SBCL_CD
245 #define SBCL_PHASE_DATAIN SBCL_IO
246 #define SBCL_PHASE_DATAOUT 0
247 #define SBCL_PHASE_MSGIN (SBCL_CD|SBCL_IO|SBCL_MSG)
248 #define SBCL_PHASE_MSGOUT (SBCL_CD|SBCL_MSG)
249 #define SBCL_PHASE_STATIN (SBCL_CD|SBCL_IO)
250 #define SBCL_PHASE_MASK (SBCL_CD|SBCL_IO|SBCL_MSG)
251
252 /*
253 * SCSI first byte received latch ro
254 * This register contains the first byte received during a block MOVE
255 * SCSI SCRIPTS instruction, including
256 *
257 * Initiator mode Target mode
258 * Message in Command
259 * Status Message out
260 * Data in Data out
261 *
262 * It also contains the selecting or reselecting device's ID and our
263 * ID.
264 *
265 * Note that this is the register the various IF conditionals can
266 * operate on.
267 */
268 #define SFBR_REG 0x08
269
270 /*
271 * SCSI input data latch ro
272 * In initiator mode, data is latched into this register on the rising
273 * edge of REQ/. In target mode, data is latched on the rising edge of
274 * ACK/
275 */
276 #define SIDL_REG_700 0x09
277 #define SIDL_REG_800 0x50
278
279 /*
280 * SCSI bus data lines ro
281 * This register reflects the instantaneous status of the SCSI data
282 * lines. Note that SCNTL0 must be set to disable parity checking,
283 * otherwise reading this register will latch new parity.
284 */
285 #define SBDL_REG_700 0x0a
286 #define SBDL_REG_800 0x58
287
288 #define SSID_REG_800 0x0a
289 #define SSID_800_VAL 0x80 /* Exactly two bits asserted at sel */
290 #define SSID_800_ENCID_MASK 0x07 /* Device which performed operation */
291
292
293 /*
294 * SCSI bus control lines rw,
295 * instantaneous readout of control lines
296 */
297 #define SOCL_REG 0x0b
298 #define SOCL_REQ 0x80 /* REQ ro */
299 #define SOCL_ACK 0x40 /* ACK ro */
300 #define SOCL_BSY 0x20 /* BSY ro */
301 #define SOCL_SEL 0x10 /* SEL ro */
302 #define SOCL_ATN 0x08 /* ATN ro */
303 #define SOCL_MSG 0x04 /* MSG ro */
304 #define SOCL_CD 0x02 /* C/D ro */
305 #define SOCL_IO 0x01 /* I/O ro */
306 /*
307 * Synchronous SCSI Clock Control bits
308 * 0 - set by DCNTL
309 * 1 - SCLK / 1.0
310 * 2 - SCLK / 1.5
311 * 3 - SCLK / 2.0
312 */
313 #define SBCL_SSCF1 0x02 /* wo, -66 only */
314 #define SBCL_SSCF0 0x01 /* wo, -66 only */
315 #define SBCL_SSCF_MASK 0x03
316
317 /*
318 * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
319 * insure that 10 clocks elapse between the two
320 */
321 /* DMA status ro */
322 #define DSTAT_REG 0x0c
323 #define DSTAT_DFE 0x80 /* DMA FIFO empty */
324 #define DSTAT_800_MDPE 0x40 /* Master Data Parity Error */
325 #define DSTAT_800_BF 0x20 /* Bus Fault */
326 #define DSTAT_ABRT 0x10 /* Aborted - set on error */
327 #define DSTAT_SSI 0x08 /* SCRIPTS single step interrupt */
328 #define DSTAT_SIR 0x04 /* SCRIPTS interrupt received -
329 set when INT instruction is
330 executed */
331 #define DSTAT_WTD 0x02 /* Watchdog timeout detected */
332 #define DSTAT_OPC 0x01 /* Illegal instruction */
333 #define DSTAT_800_IID 0x01 /* Same thing, different name */
334
335
336 #define SSTAT0_REG 0x0d /* SCSI status 0 ro */
337 #define SIST0_REG_800 0x42
338 #define SSTAT0_MA 0x80 /* ini : phase mismatch,
339 * tgt : ATN/ asserted
340 */
341 #define SSTAT0_CMP 0x40 /* function complete */
342 #define SSTAT0_700_STO 0x20 /* Selection or reselection timeout */
343 #define SIST0_800_SEL 0x20 /* Selected */
344 #define SSTAT0_700_SEL 0x10 /* Selected or reselected */
345 #define SIST0_800_RSL 0x10 /* Reselected */
346 #define SSTAT0_SGE 0x08 /* SCSI gross error */
347 #define SSTAT0_UDC 0x04 /* Unexpected disconnect */
348 #define SSTAT0_RST 0x02 /* SCSI RST/ received */
349 #define SSTAT0_PAR 0x01 /* Parity error */
350
351 #define SSTAT1_REG 0x0e /* SCSI status 1 ro */
352 #define SSTAT1_ILF 0x80 /* SIDL full */
353 #define SSTAT1_ORF 0x40 /* SODR full */
354 #define SSTAT1_OLF 0x20 /* SODL full */
355 #define SSTAT1_AIP 0x10 /* Arbitration in progress */
356 #define SSTAT1_LOA 0x08 /* Lost arbitration */
357 #define SSTAT1_WOA 0x04 /* Won arbitration */
358 #define SSTAT1_RST 0x02 /* Instant readout of RST/ */
359 #define SSTAT1_SDP 0x01 /* Instant readout of SDP/ */
360
361 #define SSTAT2_REG 0x0f /* SCSI status 2 ro */
362 #define SSTAT2_FF3 0x80 /* number of bytes in synchronous */
363 #define SSTAT2_FF2 0x40 /* data FIFO */
364 #define SSTAT2_FF1 0x20
365 #define SSTAT2_FF0 0x10
366 #define SSTAT2_FF_MASK 0xf0
367
368 /*
369 * Latched signals, latched on the leading edge of REQ/ for initiators,
370 * ACK/ for targets.
371 */
372 #define SSTAT2_SDP 0x08 /* SDP */
373 #define SSTAT2_MSG 0x04 /* MSG */
374 #define SSTAT2_CD 0x02 /* C/D */
375 #define SSTAT2_IO 0x01 /* I/O */
376
377
378 /* NCR53c700-66 only */
379 #define SCRATCHA_REG_00 0x10 /* through 0x13 Scratch A rw */
380 /* NCR53c710 and higher */
381 #define DSA_REG 0x10 /* DATA structure address */
382
383 #define CTEST0_REG_700 0x14 /* Chip test 0 ro */
384 #define CTEST0_REG_800 0x18 /* Chip test 0 rw, general purpose */
385 /* 0x80 - 0x04 are reserved */
386 #define CTEST0_700_RTRG 0x02 /* Real target mode */
387 #define CTEST0_700_DDIR 0x01 /* Data direction, 1 =
388 * SCSI bus to host, 0 =
389 * host to SCSI.
390 */
391
392 #define CTEST1_REG_700 0x15 /* Chip test 1 ro */
393 #define CTEST1_REG_800 0x19 /* Chip test 1 ro */
394 #define CTEST1_FMT3 0x80 /* Identify which byte lanes are empty */
395 #define CTEST1_FMT2 0x40 /* in the DMA FIFO */
396 #define CTEST1_FMT1 0x20
397 #define CTEST1_FMT0 0x10
398
399 #define CTEST1_FFL3 0x08 /* Identify which bytes lanes are full */
400 #define CTEST1_FFL2 0x04 /* in the DMA FIFO */
401 #define CTEST1_FFL1 0x02
402 #define CTEST1_FFL0 0x01
403
404 #define CTEST2_REG_700 0x16 /* Chip test 2 ro */
405 #define CTEST2_REG_800 0x1a /* Chip test 2 ro */
406
407 #define CTEST2_800_DDIR 0x80 /* 1 = SCSI->host */
408 #define CTEST2_800_SIGP 0x40 /* A copy of SIGP in ISTAT.
409 Reading this register clears */
410 #define CTEST2_800_CIO 0x20 /* Configured as IO */.
411 #define CTEST2_800_CM 0x10 /* Configured as memory */
412
413 /* 0x80 - 0x40 are reserved on 700 series chips */
414 #define CTEST2_700_SOFF 0x20 /* SCSI Offset Compare,
415 * As an initiator, this bit is
416 * one when the synchronous offset
417 * is zero, as a target this bit
418 * is one when the synchronous
419 * offset is at the maximum
420 * defined in SXFER
421 */
422 #define CTEST2_700_SFP 0x10 /* SCSI FIFO parity bit,
423 * reading CTEST3 unloads a byte
424 * from the FIFO and sets this
425 */
426 #define CTEST2_700_DFP 0x08 /* DMA FIFO parity bit,
427 * reading CTEST6 unloads a byte
428 * from the FIFO and sets this
429 */
430 #define CTEST2_TEOP 0x04 /* SCSI true end of process,
431 * indicates a totally finished
432 * transfer
433 */
434 #define CTEST2_DREQ 0x02 /* Data request signal */
435 /* 0x01 is reserved on 700 series chips */
436 #define CTEST2_800_DACK 0x01
437
438 /*
439 * Chip test 3 ro
440 * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
441 * check SSTAT2 FIFO full bits to determine size. Note that a GROSS
442 * error results if a read is attempted on this register. Also note
443 * that 16 and 32 bit reads of this register will cause corruption.
444 */
445 #define CTEST3_REG_700 0x17
446 /* Chip test 3 rw */
447 #define CTEST3_REG_800 0x1b
448 #define CTEST3_800_V3 0x80 /* Chip revision */
449 #define CTEST3_800_V2 0x40
450 #define CTEST3_800_V1 0x20
451 #define CTEST3_800_V0 0x10
452 #define CTEST3_800_FLF 0x08 /* Flush DMA FIFO */
453 #define CTEST3_800_CLF 0x04 /* Clear DMA FIFO */
454 #define CTEST3_800_FM 0x02 /* Fetch mode pin */
455 /* bit 0 is reserved on 800 series chips */
456
457 #define CTEST4_REG_700 0x18 /* Chip test 4 rw */
458 #define CTEST4_REG_800 0x21 /* Chip test 4 rw */
459 /* 0x80 is reserved on 700 series chips */
460 #define CTEST4_800_BDIS 0x80 /* Burst mode disable */
461 #define CTEST4_ZMOD 0x40 /* High impedance mode */
462 #define CTEST4_SZM 0x20 /* SCSI bus high impedance */
463 #define CTEST4_700_SLBE 0x10 /* SCSI loopback enabled */
464 #define CTEST4_800_SRTM 0x10 /* Shadow Register Test Mode */
465 #define CTEST4_700_SFWR 0x08 /* SCSI FIFO write enable,
466 * redirects writes from SODL
467 * to the SCSI FIFO.
468 */
469 #define CTEST4_800_MPEE 0x08 /* Enable parity checking
470 during master cycles on PCI
471 bus */
472
473 /*
474 * These bits send the contents of the CTEST6 register to the appropriate
475 * byte lane of the 32 bit DMA FIFO. Normal operation is zero, otherwise
476 * the high bit means the low two bits select the byte lane.
477 */
478 #define CTEST4_FBL2 0x04
479 #define CTEST4_FBL1 0x02
480 #define CTEST4_FBL0 0x01
481 #define CTEST4_FBL_MASK 0x07
482 #define CTEST4_FBL_0 0x04 /* Select DMA FIFO byte lane 0 */
483 #define CTEST4_FBL_1 0x05 /* Select DMA FIFO byte lane 1 */
484 #define CTEST4_FBL_2 0x06 /* Select DMA FIFO byte lane 2 */
485 #define CTEST4_FBL_3 0x07 /* Select DMA FIFO byte lane 3 */
486 #define CTEST4_800_SAVE (CTEST4_800_BDIS)
487
488
489 #define CTEST5_REG_700 0x19 /* Chip test 5 rw */
490 #define CTEST5_REG_800 0x22 /* Chip test 5 rw */
491 /*
492 * Clock Address Incrementor. When set, it increments the
493 * DNAD register to the next bus size boundary. It automatically
494 * resets itself when the operation is complete.
495 */
496 #define CTEST5_ADCK 0x80
497 /*
498 * Clock Byte Counter. When set, it decrements the DBC register to
499 * the next bus size boundary.
500 */
501 #define CTEST5_BBCK 0x40
502 /*
503 * Reset SCSI Offset. Setting this bit to 1 clears the current offset
504 * pointer in the SCSI synchronous offset counter (SSTAT). This bit
505 * is set to 1 if a SCSI Gross Error Condition occurs. The offset should
506 * be cleared when a synchronous transfer fails. When written, it is
507 * automatically cleared after the SCSI synchronous offset counter is
508 * reset.
509 */
510 /* Bit 5 is reserved on 800 series chips */
511 #define CTEST5_700_ROFF 0x20
512 /*
513 * Master Control for Set or Reset pulses. When 1, causes the low
514 * four bits of register to set when set, 0 causes the low bits to
515 * clear when set.
516 */
517 #define CTEST5_MASR 0x10
518 #define CTEST5_DDIR 0x08 /* DMA direction */
519 /*
520 * Bits 2-0 are reserved on 800 series chips
521 */
522 #define CTEST5_700_EOP 0x04 /* End of process */
523 #define CTEST5_700_DREQ 0x02 /* Data request */
524 #define CTEST5_700_DACK 0x01 /* Data acknowledge */
525
526 /*
527 * Chip test 6 rw - writing to this register writes to the byte
528 * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
529 * register.
530 */
531 #define CTEST6_REG_700 0x1a
532 #define CTEST6_REG_800 0x23
533
534 #define CTEST7_REG 0x1b /* Chip test 7 rw */
535 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
536 #define CTEST7_10_CDIS 0x80 /* Cache burst disable */
537 #define CTEST7_10_SC1 0x40 /* Snoop control bits */
538 #define CTEST7_10_SC0 0x20
539 #define CTEST7_10_SC_MASK 0x60
540 /* 0x20 is reserved on the NCR53c700 */
541 #define CTEST7_0060_FM 0x20 /* Fetch mode */
542 #define CTEST7_STD 0x10 /* Selection timeout disable */
543 #define CTEST7_DFP 0x08 /* DMA FIFO parity bit for CTEST6 */
544 #define CTEST7_EVP 0x04 /* 1 = host bus even parity, 0 = odd */
545 #define CTEST7_10_TT1 0x02 /* Transfer type */
546 #define CTEST7_00_DC 0x02 /* Set to drive DC low during instruction
547 fetch */
548 #define CTEST7_DIFF 0x01 /* Differential mode */
549
550 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
551
552
553 #define TEMP_REG 0x1c /* through 0x1f Temporary stack rw */
554
555 #define DFIFO_REG 0x20 /* DMA FIFO rw */
556 /*
557 * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
558 * moved into the CTEST8 register.
559 */
560 #define DFIFO_00_FLF 0x80 /* Flush DMA FIFO to memory */
561 #define DFIFO_00_CLF 0x40 /* Clear DMA and SCSI FIFOs */
562 #define DFIFO_BO6 0x40
563 #define DFIFO_BO5 0x20
564 #define DFIFO_BO4 0x10
565 #define DFIFO_BO3 0x08
566 #define DFIFO_BO2 0x04
567 #define DFIFO_BO1 0x02
568 #define DFIFO_BO0 0x01
569 #define DFIFO_10_BO_MASK 0x7f /* 7 bit counter */
570 #define DFIFO_00_BO_MASK 0x3f /* 6 bit counter */
571
572 /*
573 * Interrupt status rw
574 * Note that this is the only register which can be read while SCSI
575 * SCRIPTS are being executed.
576 */
577 #define ISTAT_REG_700 0x21
578 #define ISTAT_REG_800 0x14
579 #define ISTAT_ABRT 0x80 /* Software abort, write
580 *1 to abort, wait for interrupt. */
581 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
582 #define ISTAT_10_SRST 0x40 /* software reset */
583 #define ISTAT_10_SIGP 0x20 /* signal script */
584 /* 0x10 is reserved on NCR53c700 series chips */
585 #define ISTAT_800_SEM 0x10 /* semaphore */
586 #define ISTAT_CON 0x08 /* 1 when connected */
587 #define ISTAT_800_INTF 0x04 /* Interrupt on the fly */
588 #define ISTAT_700_PRE 0x04 /* Pointer register empty.
589 * Set to 1 when DSPS and DSP
590 * registers are empty in pipeline
591 * mode, always set otherwise.
592 */
593 #define ISTAT_SIP 0x02 /* SCSI interrupt pending from
594 * SCSI portion of SIOP see
595 * SSTAT0
596 */
597 #define ISTAT_DIP 0x01 /* DMA interrupt pending
598 * see DSTAT
599 */
600
601 /* NCR53c700-66 and NCR53c710 only */
602 #define CTEST8_REG 0x22 /* Chip test 8 rw */
603 #define CTEST8_0066_EAS 0x80 /* Enable alternate SCSI clock,
604 * ie read from SCLK/ rather than CLK/
605 */
606 #define CTEST8_0066_EFM 0x40 /* Enable fetch and master outputs */
607 #define CTEST8_0066_GRP 0x20 /* Generate Receive Parity for
608 * pass through. This insures that
609 * bad parity won't reach the host
610 * bus.
611 */
612 #define CTEST8_0066_TE 0x10 /* TolerANT enable. Enable
613 * active negation, should only
614 * be used for slow SCSI
615 * non-differential.
616 */
617 #define CTEST8_0066_HSC 0x08 /* Halt SCSI clock */
618 #define CTEST8_0066_SRA 0x04 /* Shorten REQ/ACK filtering,
619 * must be set for fast SCSI-II
620 * speeds.
621 */
622 #define CTEST8_0066_DAS 0x02 /* Disable automatic target/initiator
623 * switching.
624 */
625 #define CTEST8_0066_LDE 0x01 /* Last disconnect enable.
626 * The status of pending
627 * disconnect is maintained by
628 * the core, eliminating
629 * the possibility of missing a
630 * selection or reselection
631 * while waiting to fetch a
632 * WAIT DISCONNECT opcode.
633 */
634
635 #define CTEST8_10_V3 0x80 /* Chip revision */
636 #define CTEST8_10_V2 0x40
637 #define CTEST8_10_V1 0x20
638 #define CTEST8_10_V0 0x10
639 #define CTEST8_10_V_MASK 0xf0
640 #define CTEST8_10_FLF 0x08 /* Flush FIFOs */
641 #define CTEST8_10_CLF 0x04 /* Clear FIFOs */
642 #define CTEST8_10_FM 0x02 /* Fetch pin mode */
643 #define CTEST8_10_SM 0x01 /* Snoop pin mode */
644
645
646 /*
647 * The CTEST9 register may be used to differentiate between a
648 * NCR53c700 and a NCR53c710.
649 *
650 * Write 0xff to this register.
651 * Read it.
652 * If the contents are 0xff, it is a NCR53c700
653 * If the contents are 0x00, it is a NCR53c700-66 first revision
654 * If the contents are some other value, it is some other NCR53c700-66
655 */
656 #define CTEST9_REG_00 0x23 /* Chip test 9 ro */
657 #define LCRC_REG_10 0x23
658
659 /*
660 * 0x24 through 0x27 are the DMA byte counter register. Instructions
661 * write their high 8 bits into the DCMD register, the low 24 bits into
662 * the DBC register.
663 *
664 * Function is dependent on the command type being executed.
665 */
666
667
668 #define DBC_REG 0x24
669 /*
670 * For Block Move Instructions, DBC is a 24 bit quantity representing
671 * the number of bytes to transfer.
672 * For Transfer Control Instructions, DBC is bit fielded as follows :
673 */
674 /* Bits 20 - 23 should be clear */
675 #define DBC_TCI_TRUE (1 << 19) /* Jump when true */
676 #define DBC_TCI_COMPARE_DATA (1 << 18) /* Compare data */
677 #define DBC_TCI_COMPARE_PHASE (1 << 17) /* Compare phase with DCMD field */
678 #define DBC_TCI_WAIT_FOR_VALID (1 << 16) /* Wait for REQ */
679 /* Bits 8 - 15 are reserved on some implementations ? */
680 #define DBC_TCI_MASK_MASK 0xff00 /* Mask for data compare */
681 #define DBC_TCI_MASK_SHIFT 8
682 #define DBC_TCI_DATA_MASK 0xff /* Data to be compared */
683 #define DBC_TCI_DATA_SHIFT 0
684
685 #define DBC_RWRI_IMMEDIATE_MASK 0xff00 /* Immediate data */
686 #define DBC_RWRI_IMMEDIATE_SHIFT 8 /* Amount to shift */
687 #define DBC_RWRI_ADDRESS_MASK 0x3f0000 /* Register address */
688 #define DBC_RWRI_ADDRESS_SHIFT 16
689
690
691 /*
692 * DMA command r/w
693 */
694 #define DCMD_REG 0x27
695 #define DCMD_TYPE_MASK 0xc0 /* Masks off type */
696 #define DCMD_TYPE_BMI 0x00 /* Indicates a Block Move instruction */
697 #define DCMD_BMI_IO 0x01 /* I/O, CD, and MSG bits selecting */
698 #define DCMD_BMI_CD 0x02 /* the phase for the block MOVE */
699 #define DCMD_BMI_MSG 0x04 /* instruction */
700
701 #define DCMD_BMI_OP_MASK 0x18 /* mask for opcode */
702 #define DCMD_BMI_OP_MOVE_T 0x00 /* MOVE */
703 #define DCMD_BMI_OP_MOVE_I 0x08 /* MOVE Initiator */
704
705 #define DCMD_BMI_INDIRECT 0x20 /* Indirect addressing */
706
707 #define DCMD_TYPE_TCI 0x80 /* Indicates a Transfer Control
708 instruction */
709 #define DCMD_TCI_IO 0x01 /* I/O, CD, and MSG bits selecting */
710 #define DCMD_TCI_CD 0x02 /* the phase for the block MOVE */
711 #define DCMD_TCI_MSG 0x04 /* instruction */
712 #define DCMD_TCI_OP_MASK 0x38 /* mask for opcode */
713 #define DCMD_TCI_OP_JUMP 0x00 /* JUMP */
714 #define DCMD_TCI_OP_CALL 0x08 /* CALL */
715 #define DCMD_TCI_OP_RETURN 0x10 /* RETURN */
716 #define DCMD_TCI_OP_INT 0x18 /* INT */
717
718 #define DCMD_TYPE_RWRI 0x40 /* Indicates I/O or register Read/Write
719 instruction */
720 #define DCMD_RWRI_OPC_MASK 0x38 /* Opcode mask */
721 #define DCMD_RWRI_OPC_WRITE 0x28 /* Write SFBR to register */
722 #define DCMD_RWRI_OPC_READ 0x30 /* Read register to SFBR */
723 #define DCMD_RWRI_OPC_MODIFY 0x38 /* Modify in place */
724
725 #define DCMD_RWRI_OP_MASK 0x07
726 #define DCMD_RWRI_OP_MOVE 0x00
727 #define DCMD_RWRI_OP_SHL 0x01
728 #define DCMD_RWRI_OP_OR 0x02
729 #define DCMD_RWRI_OP_XOR 0x03
730 #define DCMD_RWRI_OP_AND 0x04
731 #define DCMD_RWRI_OP_SHR 0x05
732 #define DCMD_RWRI_OP_ADD 0x06
733 #define DCMD_RWRI_OP_ADDC 0x07
734
735 #define DCMD_TYPE_MMI 0xc0 /* Indicates a Memory Move instruction
736 (three words) */
737
738
739 #define DNAD_REG 0x28 /* through 0x2b DMA next address for
740 data */
741 #define DSP_REG 0x2c /* through 0x2f DMA SCRIPTS pointer rw */
742 #define DSPS_REG 0x30 /* through 0x33 DMA SCRIPTS pointer
743 save rw */
744 #define DMODE_REG_00 0x34 /* DMA mode rw */
745 #define DMODE_00_BL1 0x80 /* Burst length bits */
746 #define DMODE_00_BL0 0x40
747 #define DMODE_BL_MASK 0xc0
748 /* Burst lengths (800) */
749 #define DMODE_BL_2 0x00 /* 2 transfer */
750 #define DMODE_BL_4 0x40 /* 4 transfers */
751 #define DMODE_BL_8 0x80 /* 8 transfers */
752 #define DMODE_BL_16 0xc0 /* 16 transfers */
753
754 #define DMODE_700_BW16 0x20 /* Host buswidth = 16 */
755 #define DMODE_700_286 0x10 /* 286 mode */
756 #define DMODE_700_IOM 0x08 /* Transfer to IO port */
757 #define DMODE_700_FAM 0x04 /* Fixed address mode */
758 #define DMODE_700_PIPE 0x02 /* Pipeline mode disables
759 * automatic fetch / exec
760 */
761 #define DMODE_MAN 0x01 /* Manual start mode,
762 * requires a 1 to be written
763 * to the start DMA bit in the DCNTL
764 * register to run scripts
765 */
766
767 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
768
769 /* NCR53c800 series only */
770 #define SCRATCHA_REG_800 0x34 /* through 0x37 Scratch A rw */
771 /* NCR53c710 only */
772 #define SCRATCB_REG_10 0x34 /* through 0x37 scratch B rw */
773
774 #define DMODE_REG_10 0x38 /* DMA mode rw, NCR53c710 and newer */
775 #define DMODE_800_SIOM 0x20 /* Source IO = 1 */
776 #define DMODE_800_DIOM 0x10 /* Destination IO = 1 */
777 #define DMODE_800_ERL 0x08 /* Enable Read Line */
778
779 /* 35-38 are reserved on 700 and 700-66 series chips */
780 #define DIEN_REG 0x39 /* DMA interrupt enable rw */
781 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
782 #define DIEN_800_MDPE 0x40 /* Master data parity error */
783 #define DIEN_800_BF 0x20 /* BUS fault */
784 #define DIEN_ABRT 0x10 /* Enable aborted interrupt */
785 #define DIEN_SSI 0x08 /* Enable single step interrupt */
786 #define DIEN_SIR 0x04 /* Enable SCRIPTS INT command
787 * interrupt
788 */
789 /* 0x02 is reserved on 800 series chips */
790 #define DIEN_700_WTD 0x02 /* Enable watchdog timeout interrupt */
791 #define DIEN_700_OPC 0x01 /* Enable illegal instruction
792 * interrupt
793 */
794 #define DIEN_800_IID 0x01 /* Same meaning, different name */
795
796 /*
797 * DMA watchdog timer rw
798 * set in 16 CLK input periods.
799 */
800 #define DWT_REG 0x3a
801
802 /* DMA control rw */
803 #define DCNTL_REG 0x3b
804 #define DCNTL_700_CF1 0x80 /* Clock divisor bits */
805 #define DCNTL_700_CF0 0x40
806 #define DCNTL_700_CF_MASK 0xc0
807 /* Clock divisors Divisor SCLK range (MHZ) */
808 #define DCNTL_700_CF_2 0x00 /* 2.0 37.51-50.00 */
809 #define DCNTL_700_CF_1_5 0x40 /* 1.5 25.01-37.50 */
810 #define DCNTL_700_CF_1 0x80 /* 1.0 16.67-25.00 */
811 #define DCNTL_700_CF_3 0xc0 /* 3.0 50.01-66.67 (53c700-66) */
812
813 #define DCNTL_700_S16 0x20 /* Load scripts 16 bits at a time */
814 #define DCNTL_SSM 0x10 /* Single step mode */
815 #define DCNTL_700_LLM 0x08 /* Low level mode, can only be set
816 * after selection */
817 #define DCNTL_800_IRQM 0x08 /* Totem pole IRQ pin */
818 #define DCNTL_STD 0x04 /* Start DMA / SCRIPTS */
819 /* 0x02 is reserved */
820 #define DCNTL_00_RST 0x01 /* Software reset, resets everything
821 * but 286 mode bit in DMODE. On the
822 * NCR53c710, this bit moved to CTEST8
823 */
824 #define DCNTL_10_COM 0x01 /* 700 software compatibility mode */
825
826 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
827
828
829 /* NCR53c700-66 only */
830 #define SCRATCHB_REG_00 0x3c /* through 0x3f scratch b rw */
831 #define SCRATCHB_REG_800 0x5c /* through 0x5f scratch b rw */
832 /* NCR53c710 only */
833 #define ADDER_REG_10 0x3c /* Adder, NCR53c710 only */
834
835 #define SIEN1_REG_800 0x41
836 #define SIEN1_800_STO 0x04 /* selection/reselection timeout */
837 #define SIEN1_800_GEN 0x02 /* general purpose timer */
838 #define SIEN1_800_HTH 0x01 /* handshake to handshake */
839
840 #define SIST1_REG_800 0x43
841 #define SIST1_800_STO 0x04 /* selection/reselection timeout */
842 #define SIST1_800_GEN 0x02 /* general purpose timer */
843 #define SIST1_800_HTH 0x01 /* handshake to handshake */
844
845 #define SLPAR_REG_800 0x44 /* Parity */
846
847 #define MACNTL_REG_800 0x46 /* Memory access control */
848 #define MACNTL_800_TYP3 0x80
849 #define MACNTL_800_TYP2 0x40
850 #define MACNTL_800_TYP1 0x20
851 #define MACNTL_800_TYP0 0x10
852 #define MACNTL_800_DWR 0x08
853 #define MACNTL_800_DRD 0x04
854 #define MACNTL_800_PSCPT 0x02
855 #define MACNTL_800_SCPTS 0x01
856
857 #define GPCNTL_REG_800 0x47 /* General Purpose Pin Control */
858
859 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
860 #define STIME0_REG_800 0x48 /* SCSI Timer Register 0 */
861 #define STIME0_800_HTH_MASK 0xf0 /* Handshake to Handshake timeout */
862 #define STIME0_800_HTH_SHIFT 4
863 #define STIME0_800_SEL_MASK 0x0f /* Selection timeout */
864 #define STIME0_800_SEL_SHIFT 0
865
866 #define STIME1_REG_800 0x49
867 #define STIME1_800_GEN_MASK 0x0f /* General purpose timer */
868
869 #define RESPID_REG_800 0x4a /* Response ID, bit fielded */
870
871 #define STEST0_REG_800 0x4c
872 #define STEST0_800_SLT 0x08 /* Selection response logic test */
873 #define STEST0_800_ART 0x04 /* Arbitration priority encoder test */
874 #define STEST0_800_SOZ 0x02 /* Synchronous offset zero */
875 #define STEST0_800_SOM 0x01 /* Synchronous offset maximum */
876
877 #define STEST1_REG_800 0x4d
878 #define STEST1_800_SCLK 0x80 /* Disable SCSI clock */
879
880 #define STEST2_REG_800 0x4e
881 #define STEST2_800_SCE 0x80 /* Enable SOCL/SODL */
882 #define STEST2_800_ROF 0x40 /* Reset SCSI sync offset */
883 #define STEST2_800_SLB 0x10 /* Enable SCSI loopback mode */
884 #define STEST2_800_SZM 0x08 /* SCSI high impedance mode */
885 #define STEST2_800_EXT 0x02 /* Extend REQ/ACK filter 30 to 60ns */
886 #define STEST2_800_LOW 0x01 /* SCSI low level mode */
887
888 #define STEST3_REG_800 0x4f
889 #define STEST3_800_TE 0x80 /* Enable active negation */
890 #define STEST3_800_STR 0x40 /* SCSI FIFO test read */
891 #define STEST3_800_HSC 0x20 /* Halt SCSI clock */
892 #define STEST3_800_DSI 0x10 /* Disable single initiator response */
893 #define STEST3_800_TTM 0x04 /* Time test mode */
894 #define STEST3_800_CSF 0x02 /* Clear SCSI FIFO */
895 #define STEST3_800_STW 0x01 /* SCSI FIFO test write */
896
897
898
899
900
901 #define OPTION_PARITY 0x1 /* Enable parity checking */
902 #define OPTION_TAGGED_QUEUE 0x2 /* Enable SCSI-II tagged queuing */
903 #define OPTION_700 0x8 /* Always run NCR53c700 scripts */
904 #define OPTION_INTFLY 0x10 /* Use INTFLY interrupts */
905 #define OPTION_DEBUG_INTR 0x20 /* Debug interrupts */
906 #define OPTION_DEBUG_INIT_ONLY 0x40 /* Run initialization code and
907 simple test code, return
908 DID_NO_CONNECT if any SCSI
909 commands are attempted. */
910 #define OPTION_DEBUG_READ_ONLY 0x80 /* Return DID_ERROR if any
911 SCSI write is attempted */
912 #define OPTION_DEBUG_TRACE 0x100 /* Animated trace mode, print
913 each address and instruction
914 executed to debug buffer. */
915 #define OPTION_DEBUG_SINGLE 0x200 /* stop after executing one
916 instruction */
917 #define OPTION_SYNCHRONOUS 0x400 /* Enable sync SCSI. */
918 #define OPTION_MEMORY_MAPPED 0x800 /* NCR registers have valid
919 memory mapping */
920 #define OPTION_IO_MAPPED 0x1000 /* NCR registers have valid
921 I/O mapping */
922 #define OPTION_DEBUG_PROBE_ONLY 0x2000 /* Probe only, don't even init */
923 #define OPTION_DEBUG_TESTS_ONLY 0x4000 /* Probe, init, run selected tests */
924
925 #define OPTION_DEBUG_TEST0 0x08000 /* Run test 0 */
926 #define OPTION_DEBUG_TEST1 0x10000 /* Run test 1 */
927 #define OPTION_DEBUG_TEST2 0x20000 /* Run test 2 */
928
929 #define OPTION_DEBUG_DUMP 0x40000 /* Dump commands */
930 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
931 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
932 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
933 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
934 #define OPTION_DEBUG_DSA 0x800000
935 #define OPTION_DEBUG_CORRUPTION 0x1000000 /* Detect script corruption */
936
937 #if !defined(PERM_OPTIONS)
938 #define PERM_OPTIONS 0
939 #endif
940
941 struct NCR53c7x0_synchronous {
942 u32 select_indirect; /* Value used for indirect selection */
943 u32 script[6]; /* Size ?? Script used when target is
944 reselected */
945 unsigned renegotiate:1; /* Force renegotiation on next
946 select */
947 };
948
949 #define CMD_FLAG_SDTR 1 /* Initiating synchronous
950 transfer negotiation */
951 #define CMD_FLAG_WDTR 2 /* Initiating wide transfer
952 negotiation */
953 #define CMD_FLAG_DID_SDTR 4 /* did SDTR */
954
955 struct NCR53c7x0_table_indirect {
956 u32 count;
957 void *address;
958 };
959
960 struct NCR53c7x0_cmd {
961 void *real; /* Real, unaligned address */
962 void (* free)(void *); /* Command to deallocate; NULL
963 for structures allocated with
964 scsi_register, etc. */
965 Scsi_Cmnd *cmd; /* Associated Scsi_Cmnd
966 structure, Scsi_Cmnd points
967 at NCR53c7x0_cmd using
968 host_scribble structure */
969
970 int size; /* scsi_malloc'd size of this
971 structure */
972
973 int flags;
974
975 unsigned char select[11]; /* Select message, includes
976 IDENTIFY
977 (optional) QUEUE TAG
978 (optional) SDTR or WDTR
979 */
980
981
982 volatile struct NCR53c7x0_cmd *next, *prev;
983 /* Linux maintained lists. Note that
984 hostdata->free is a singly linked
985 list; the rest are doubly linked */
986
987
988
989 u32 *data_transfer_start; /* Start of data transfer routines */
990 u32 *data_transfer_end; /* Address after end of data transfer o
991 routines */
992
993 u32 residual[8]; /* Residual data transfer
994 shadow of data_transfer code.
995
996 Has instruction with modified
997 DBC field followed by jump to
998 CALL routine following command.
999 */
1000
1001 u32 dsa[0]; /* Variable length (depending
1002 on host type, number of scatter /
1003 gather buffers, etc). */
1004 };
1005
1006 struct NCR53c7x0_break {
1007 u32 *address, old_instruction[2];
1008 struct NCR53c7x0_break *next;
1009 unsigned char old_size; /* Size of old instruction */
1010 };
1011
1012 /* Indicates that the NCR is not executing code */
1013 #define STATE_HALTED 0
1014 /*
1015 * Indicates that the NCR is executing the wait for select / reselect
1016 * script. Only used when running NCR53c700 compatible scripts, only
1017 * state during which an ABORT is _not_ considered an error condition.
1018 */
1019 #define STATE_WAITING 1
1020 /* Indicates that the NCR is executing other code. */
1021 #define STATE_RUNNING 2
1022 /*
1023 * Indicates that the NCR was being aborted.
1024 */
1025 #define STATE_ABORTING 3
1026 /*
1027 * Indicates that the NCR was successfully aborted. */
1028 #define STATE_ABORTED 4
1029
1030
1031 /*
1032 * Where knowledge of SCSI SCRIPT(tm) specified values are needed
1033 * in an interrupt handler, an interrupt handler exists for each
1034 * different SCSI script so we don't have name space problems.
1035 *
1036 * Return values of these handlers are as follows :
1037 */
1038 #define SPECIFIC_INT_NOTHING 0 /* don't even restart */
1039 #define SPECIFIC_INT_RESTART 1 /* restart at the next instruction */
1040 #define SPECIFIC_INT_ABORT 2 /* recoverable error, abort cmd */
1041 #define SPECIFIC_INT_PANIC 3 /* unrecoverable error, panic */
1042 #define SPECIFIC_INT_DONE 4 /* normal command completion */
1043 #define SPECIFIC_INT_BREAK 5 /* break point encountered */
1044
1045 struct NCR53c7x0_hostdata {
1046 int size; /* Size of entire Scsi_Host
1047 structure */
1048 struct Scsi_Host *next; /* next of this type */
1049 int board; /* set to board type, useful if
1050 we have host specific things,
1051 ie, a general purpose I/O
1052 bit is being used to enable
1053 termination, etc. */
1054
1055 int chip; /* set to chip type */
1056 /*
1057 * NCR53c700 = 700
1058 * NCR53c700-66 = 70066
1059 * NCR53c710 = 710
1060 * NCR53c720 = 720
1061 * NCR53c810 = 810
1062 */
1063
1064 /*
1065 * PCI bus, device, function, only for NCR53c8x0 chips.
1066 * pci_valid indicates that the PCI configuration information
1067 * is valid, and we can twiddle MAX_LAT, etc. as recommended
1068 * for maximum performance in the NCR documentation.
1069 */
1070 unsigned char pci_bus, pci_device_fn;
1071 unsigned pci_valid:1;
1072
1073 u32 *dsp; /* dsp to restart with after
1074 all stacked interrupts are
1075 handled. */
1076
1077 unsigned dsp_changed:1; /* Has dsp changed within this
1078 set of stacked interrupts ? */
1079
1080 unsigned char dstat; /* Most recent value of dstat */
1081 unsigned dstat_valid:1;
1082
1083 unsigned expecting_iid:1; /* Expect IID interrupt */
1084 unsigned expecting_sto:1; /* Expect STO interrupt */
1085
1086 /*
1087 * The code stays cleaner if we use variables with function
1088 * pointers and offsets that are unique for the different
1089 * scripts rather than having a slew of switch(hostdata->chip)
1090 * statements.
1091 *
1092 * It also means that the #defines from the SCSI SCRIPTS(tm)
1093 * don't have to be visible outside of the script-specific
1094 * instructions, preventing name space pollution.
1095 */
1096
1097 void (* init_fixup)(struct Scsi_Host *host);
1098 void (* init_save_regs)(struct Scsi_Host *host);
1099 void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1100 void (* soft_reset)(struct Scsi_Host *host);
1101 int (* run_tests)(struct Scsi_Host *host);
1102
1103 /*
1104 * Called when DSTAT_SIR is set, indicating an interrupt generated
1105 * by the INT instruction, where values are unique for each SCSI
1106 * script. Should return one of the SPEC_* values.
1107 */
1108
1109 int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1110
1111 long dsa_size; /* Size of DSA structure */
1112
1113 /*
1114 * Location of DSA fields for the SCSI SCRIPT corresponding to this
1115 * chip.
1116 */
1117
1118 s32 dsa_start;
1119 s32 dsa_end;
1120 s32 dsa_next;
1121 s32 dsa_prev;
1122 s32 dsa_cmnd;
1123 s32 dsa_select;
1124 s32 dsa_msgout;
1125 s32 dsa_cmdout;
1126 s32 dsa_dataout;
1127 s32 dsa_datain;
1128 s32 dsa_msgin;
1129 s32 dsa_msgout_other;
1130 s32 dsa_write_sync;
1131 s32 dsa_write_resume;
1132 s32 dsa_jump_resume;
1133 s32 dsa_check_reselect;
1134 s32 dsa_status;
1135
1136 /*
1137 * Important entry points that generic fixup code needs
1138 * to know about, fixed up.
1139 */
1140
1141 s32 E_accept_message;
1142 s32 E_dsa_code_template;
1143 s32 E_dsa_code_template_end;
1144 s32 E_command_complete;
1145 s32 E_msg_in;
1146 s32 E_initiator_abort;
1147 s32 E_other_transfer;
1148 s32 E_target_abort;
1149 s32 E_schedule;
1150 s32 E_debug_break;
1151 s32 E_reject_message;
1152 s32 E_respond_message;
1153 s32 E_select;
1154 s32 E_select_msgout;
1155 s32 E_test_0;
1156 s32 E_test_1;
1157 s32 E_test_2;
1158 s32 E_test_3;
1159 s32 E_dsa_zero;
1160 s32 E_dsa_jump_resume;
1161
1162 int options; /* Bitfielded set of options enabled */
1163 volatile u32 test_completed; /* Test completed */
1164 int test_running; /* Test currently running */
1165 int test_source;
1166 volatile int test_dest;
1167
1168 volatile int state; /* state of driver, only used for
1169 OPTION_700 */
1170
1171 unsigned char dmode; /*
1172 * set to the address of the DMODE
1173 * register for this chip.
1174 */
1175 unsigned char istat; /*
1176 * set to the address of the ISTAT
1177 * register for this chip.
1178 */
1179
1180 int scsi_clock; /*
1181 * SCSI clock in HZ. 0 may be used
1182 * for unknown, although this will
1183 * disable synchronous negotiation.
1184 */
1185
1186 volatile int intrs; /* Number of interrupts */
1187 unsigned char saved_dmode;
1188 unsigned char saved_ctest4;
1189 unsigned char saved_ctest7;
1190 unsigned char saved_dcntl;
1191 unsigned char saved_scntl3;
1192
1193 unsigned char this_id_mask;
1194
1195 /* Debugger information */
1196 struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1197 *breakpoint_current; /* Current breakpoint being stepped
1198 through, NULL if we are running
1199 normally. */
1200 #ifdef NCR_DEBUG
1201 int debug_size; /* Size of debug buffer */
1202 volatile int debug_count; /* Current data count */
1203 volatile char *debug_buf; /* Output ring buffer */
1204 volatile char *debug_write; /* Current write pointer */
1205 volatile char *debug_read; /* Current read pointer */
1206 #endif /* def NCR_DEBUG */
1207
1208 /* XXX - primitive debugging junk, remove when working ? */
1209 int debug_print_limit; /* Number of commands to print
1210 out exhaustive debugging
1211 information for if
1212 OPTION_DEBUG_DUMP is set */
1213
1214 unsigned char debug_lun_limit[8]; /* If OPTION_DEBUG_TARGET_LIMIT
1215 set, puke if commands are sent
1216 to other target/lun combinations */
1217
1218 int debug_count_limit; /* Number of commands to execute
1219 before puking to limit debugging
1220 output */
1221
1222
1223 volatile unsigned idle:1; /* set to 1 if idle */
1224
1225 /*
1226 * Table of synchronous transfer parameters set on a per-target
1227 * basis.
1228 *
1229 * XXX - do we need to increase this to 16 for the WIDE-SCSI
1230 * flavors of the board?
1231 */
1232
1233 volatile struct NCR53c7x0_synchronous sync[8];
1234
1235 volatile struct NCR53c7x0_cmd *issue_queue;
1236 /* waiting to be issued by
1237 Linux driver */
1238 volatile struct NCR53c7x0_cmd *running_list;
1239 /* commands running, maintained
1240 by Linux driver */
1241 volatile struct NCR53c7x0_cmd *current; /* currently connected
1242 nexus, ONLY valid for
1243 NCR53c700/NCR53c700-66
1244 */
1245
1246 volatile struct NCR53c7x0_cmd *spare; /* pointer to spare,
1247 allocated at probe time,
1248 which we can use for
1249 initialization */
1250 volatile struct NCR53c7x0_cmd *free;
1251 int max_cmd_size; /* Maximum size of NCR53c7x0_cmd
1252 based on number of
1253 scatter/gather segments, etc.
1254 */
1255 volatile int num_cmds; /* Number of commands
1256 allocated */
1257 volatile unsigned char cmd_allocated[8]; /* Have we allocated commands
1258 for this target yet? If not,
1259 do so ASAP */
1260 volatile unsigned char busy[8][8]; /* number of commands
1261 executing on each target
1262 */
1263 /*
1264 * Eventually, I'll switch to a coroutine for calling
1265 * cmd->done(cmd), etc. so that we can overlap interrupt
1266 * processing with this code for maximum performance.
1267 */
1268
1269 volatile struct NCR53c7x0_cmd *finished_queue;
1270
1271
1272 /* Shared variables between SCRIPT and host driver */
1273 volatile u32 issue_dsa_head;
1274 /* commands waiting to be
1275 issued, insertions are
1276 done by Linux driver,
1277 deletions are done by
1278 NCR */
1279 u32 *issue_dsa_tail; /* issue queue tail pointer;
1280 used by Linux driver only */
1281 volatile unsigned char msg_buf[16]; /* buffer for messages
1282 other than the command
1283 complete message */
1284 volatile u32 reconnect_dsa_head;
1285 /* disconnected commands,
1286 maintained by NCR */
1287 /* Data identifying nexus we are trying to match during reselection */
1288 volatile unsigned char reselected_identify; /* IDENTIFY message */
1289 volatile unsigned char reselected_tag; /* second byte of queue tag
1290 message or 0 */
1291 /* These were static variables before we moved them */
1292
1293 s32 NCR53c7xx_zero;
1294 s32 NCR53c7xx_sink;
1295 char NCR53c7xx_msg_reject;
1296 char NCR53c7xx_msg_abort;
1297 char NCR53c7xx_msg_nop;
1298
1299 int script_count; /* Size of script in words */
1300 u32 script[0]; /* Relocated SCSI script */
1301
1302 };
1303
1304 #define IRQ_NONE 255
1305 #define DMA_NONE 255
1306 #define IRQ_AUTO 254
1307 #define DMA_AUTO 254
1308
1309 #define BOARD_GENERIC 0
1310
1311 #define NCR53c7x0_insn_size(insn) \
1312 (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1313
1314
1315 #define NCR53c7x0_local_declare() \
1316 volatile unsigned char *NCR53c7x0_address_memory; \
1317 unsigned int NCR53c7x0_address_io; \
1318 int NCR53c7x0_memory_mapped
1319
1320 #define NCR53c7x0_local_setup(host) \
1321 NCR53c7x0_address_memory = (void *) (host)->base; \
1322 NCR53c7x0_address_io = (unsigned int) (host)->io_port; \
1323 NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *) \
1324 host->hostdata)-> options & OPTION_MEMORY_MAPPED
1325
1326 #define NCR53c7x0_read8(address) \
1327 (NCR53c7x0_memory_mapped ? \
1328 ncr_readb(NCR53c7x0_address_memory + (address)) : \
1329 inb(NCR53c7x0_address_io + (address)))
1330
1331 #define NCR53c7x0_read16(address) \
1332 (NCR53c7x0_memory_mapped ? \
1333 ncr_readw(NCR53c7x0_address_memory + (address)) : \
1334 inw(NCR53c7x0_address_io + (address)))
1335
1336 #define NCR53c7x0_read32(address) \
1337 (NCR53c7x0_memory_mapped ? \
1338 ncr_readl(NCR53c7x0_address_memory + (address)) : \
1339 inl(NCR53c7x0_address_io + (address)))
1340
1341 #define NCR53c7x0_write8(address,value) \
1342 (NCR53c7x0_memory_mapped ? \
1343 ncr_writeb((value), NCR53c7x0_address_memory + (address)) : \
1344 outb((value), NCR53c7x0_address_io + (address)))
1345
1346 #define NCR53c7x0_write16(address,value) \
1347 (NCR53c7x0_memory_mapped ? \
1348 ncr_writew((value), NCR53c7x0_address_memory + (address)) : \
1349 outw((value), NCR53c7x0_address_io + (address)))
1350
1351 #define NCR53c7x0_write32(address,value) \
1352 (NCR53c7x0_memory_mapped ? \
1353 ncr_writel((value), NCR53c7x0_address_memory + (address)) : \
1354 outl((value), NCR53c7x0_address_io + (address)))
1355
1356 #define patch_abs_32(script, offset, symbol, value) \
1357 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1358 (u32)); ++i) { \
1359 (script)[A_##symbol##_used[i] - (offset)] += (value); \
1360 if (hostdata->options & OPTION_DEBUG_FIXUP) \
1361 printk("scsi%d : %s reference %d at 0x%x in %s is now 0x%x\n",\
1362 host->host_no, #symbol, i, A_##symbol##_used[i] - \
1363 (int)(offset), #script, (script)[A_##symbol##_used[i] - \
1364 (offset)]); \
1365 }
1366
1367 #define patch_abs_rwri_data(script, offset, symbol, value) \
1368 for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof \
1369 (u32)); ++i) \
1370 (script)[A_##symbol##_used[i] - (offset)] = \
1371 ((script)[A_##symbol##_used[i] - (offset)] & \
1372 ~DBC_RWRI_IMMEDIATE_MASK) | \
1373 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) & \
1374 DBC_RWRI_IMMEDIATE_MASK)
1375
1376 #define patch_dsa_32(dsa, symbol, word, value) \
1377 { \
1378 (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(u32) \
1379 + (word)] = (value); \
1380 if (hostdata->options & OPTION_DEBUG_DSA) \
1381 printk("scsi : dsa %s symbol %s(%d) word %d now 0x%x\n", \
1382 #dsa, #symbol, hostdata->##symbol, \
1383 (word), (u32)(value)); \
1384 }
1385
1386
1387
1388 #endif /* NCR53c7x0_C */
1389 #endif /* NCR53c7x0_H */
![[top]](../icons/top.png){kind=icon}
![[bottom]](../icons/n_bottom.png){kind=icon}
*/