1 /* 2 * include/linux/serial.h 3 * 4 * Copyright (C) 1992 by Theodore Ts'o. 5 * 6 * Redistribution of this file is permitted under the terms of the GNU 7 * Public License (GPL) 8 */ 9 10 /* 11 * This our internal structure for keeping track of interrupt service 12 * routines. 13 */ 14 typedef struct struct_ISR *async_ISR; 15 struct struct_ISR { 16 int irq; /* The IRQ assigned for this device */ 17 int port; /* The base port for this device */ 18 /* (use is ISR specific) */ 19 void (*ISR_proc)(async_ISR, int); 20 int line; /* The serial line (or base */ 21 /* serial line) */ 22 int refcnt; /* How many devices are depending on */ 23 /* this interrupt (multiport boards) */ 24 async_ISR next_ISR; /* For the linked list */ 25 async_ISR prev_ISR; 26 }; 27 28 /* 29 * This is our internal structure for each serial port's state. 30 * 31 * Many fields are paralleled by the structure used by the serial_struct 32 * structure. 33 * 34 * For definitions of the flags field, see tty.h 35 */ 36 37 struct async_struct { 38 int baud_base; 39 int port; 40 async_ISR ISR; 41 int flags; 42 int type; 43 struct tty_struct *tty; 44 unsigned long timer; 45 int timeout; 46 int xmit_fifo_size; 47 int custom_divisor; 48 int line; 49 }; 50 51 /* 52 * These are the UART port assignments, expressed as offsets from the base 53 * register. These assignments should hold for any serial port based on 54 * a 8250, 16450, or 16550(A). 55 */ 56 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */ 57 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 58 #define UART_DLL 0 /* Out: Devisor Latch Low (DLAB=1) */ 59 #define UART_DLM 1 /* Out: Devisor Latch High (DLAB=1) */ 60 #define UART_IER 1 /* Out: Interrupt Enable Register */ 61 #define UART_IIR 2 /* In: Interrupt ID Register */ 62 #define UART_FCR 2 /* Out: FIFO Control Register */ 63 #define UART_LCR 3 /* Out: Line Control Register */ 64 #define UART_MCR 4 /* Out: Modem Control Register */ 65 #define UART_LSR 5 /* In: Line Status Register */ 66 #define UART_MSR 6 /* In: Modem Status Register */ 67 #define UART_SCR 7 /* I/O: Scratch Register */ 68 69 /* 70 * These are the definitions for the FIFO Control Register 71 */ 72 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 73 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 74 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 75 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 76 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 77 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 78 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 79 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 80 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 81 82 #define UART_FCR_CLEAR_CMD (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT) 83 #define UART_FCR_SETUP_CMD (UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14) 84 85 /* 86 * These are the definitions for the Line Control Register 87 * 88 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 89 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 90 */ 91 #define UART_LCR_DLAB 0x80 /* Devisor latch access bit */ 92 #define UART_LCR_SBC 0x40 /* Set break control */ 93 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 94 #define UART_LCR_EPAR 0x10 /* Even paraity select */ 95 #define UART_LCR_PARITY 0x08 /* Parity Enable */ 96 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 97 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 98 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 99 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 100 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 101 102 /* 103 * These are the definitions for the Line Status Register 104 */ 105 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 106 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 107 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 108 #define UART_LSR_FE 0x08 /* Frame error indicator */ 109 #define UART_LSR_PE 0x04 /* Parity error indicator */ 110 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 111 #define UART_LSR_DR 0x01 /* Receiver data ready */ 112 113 /* 114 * These are the definitions for the Interrupt Indentification Register 115 */ 116 #define UART_IIR_PEND 0x01 /* Interrupt pending */ 117 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 118 119 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 120 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 121 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 122 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 123 124 /* 125 * These are the definitions for the Interrupt Enable Register 126 */ 127 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 128 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 129 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 130 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 131 132 /* 133 * These are the definitions for the Modem Control Register 134 */ 135 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 136 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 137 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 138 #define UART_MCR_RTS 0x02 /* RTS complement */ 139 #define UART_MCR_DTR 0x01 /* DTR complement */ 140 141 /* 142 * These are the definitions for the Modem Status Register 143 */ 144 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 145 #define UART_MSR_RI 0x40 /* Ring Indicator */ 146 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 147 #define UART_MSR_CTS 0x10 /* Clear to Send */ 148 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 149 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 150 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 151 #define UART_MSR_DCTS 0x01 /* Delta CTS */