net/inet/8390.h

/* */
   1 /* Generic NS8390 register definitions. */
   2 /* This file is part of Donald Becker's 8390 drivers, and is distributed
   3    under the same license.
   4    Some of these names and comments are from the Crynwr packet drivers. */
   5 
   6 #ifndef e8390_h
   7 #define e8390_h
   8 
   9 #define TX_2X_PAGES 12
  10 #define TX_1X_PAGES 6
  11 #define TX_PAGES (ei_status.pingpong ? TX_2X_PAGES : TX_1X_PAGES)
  12 
  13 #define ETHER_ADDR_LEN 6
  14 
  15 /* From 8390.c */
  16 void ei_interrupt(int reg_ptr);
  17 /* From auto_irq.c */
  18 extern void autoirq_setup(int waittime);
  19 extern int autoirq_report(int waittime);
  20 
  21 /* Most of these entries should be in 'struct device' (or most of the
  22    things in there should be here!) */
  23 /* You have one of these per-board */
  24 struct ei_device {
  25   char *name;
  26   void (*reset_8390)(struct device *);
  27   void (*block_output)(struct device *, int, const unsigned char *, int);
  28   int  (*block_input)(struct device *, int, char *, int);
  29   int open:1;
  30   int word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */
  31   int txing:1;                  /* Transmit Active */
  32   int dmaing:2;                 /* Remote DMA Active */
  33   int irqlock:1;                /* 8390's intrs disabled when '1'. */
  34   int pingpong:1;               /* Using the ping-pong driver */
  35   unsigned char tx_start_page, rx_start_page, stop_page;
  36   unsigned char current_page;   /* Read pointer in buffer  */
  37   unsigned char interface_num;  /* Net port (AUI, 10bT.) to use. */
  38   unsigned char txqueue;        /* Tx Packet buffer queue length. */
  39   unsigned char in_interrupt;
  40   short tx1, tx2;               /* Packet lengths for ping-pong tx. */
  41   short lasttx;                 /* Alpha version consistency check. */
  42   /* The statistics: these are returned from the ioctl() as a block.  */
  43   int tx_packets;
  44   int tx_errors;
  45   int rx_packets;
  46   int soft_rx_errors;
  47   int soft_rx_err_bits;
  48   int missed_packets;
  49   int rx_overruns;
  50   int rx_overrun_packets;
  51 };
  52 
  53 #define ei_status (*(struct ei_device *)(dev->private))
  54 
  55 /* Some generic ethernet register configurations. */
  56 #define E8390_TX_IRQ_MASK 0xa   /* For register EN0_ISR */
  57 #define E8390_RX_IRQ_MASK  0x5
  58 #define E8390_RXCONFIG 0x4      /* EN0_RXCR: broadcasts, no multicast,errors */
  59 #define E8390_RXOFF 0x20        /* EN0_RXCR: Accept no packets */
  60 #define E8390_TXCONFIG 0x00     /* EN0_TXCR: Normal transmit mode */
  61 #define E8390_TXOFF 0x02        /* EN0_TXCR: Transmitter off */
  62 
  63 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  64 #define E8390_STOP      0x01    /* Stop and reset the chip */
  65 #define E8390_START     0x02    /* Start the chip, clear reset */
  66 #define E8390_TRANS     0x04    /* Transmit a frame */
  67 #define E8390_RREAD     0x08    /* Remote read */
  68 #define E8390_RWRITE    0x10    /* Remote write  */
  69 #define E8390_NODMA     0x20    /* Remote DMA */
  70 #define E8390_PAGE0     0x00    /* Select page chip registers */
  71 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  72 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  73 
  74 #define E8390_CMD       0x00    /* The command register (for all pages) */
  75 /* Page 0 register offsets. */
  76 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  77 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  78 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  79 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  80 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  81 #define EN0_TSR         0x04    /* Transmit status reg RD */
  82 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  83 #define EN0_NCR         0x05    /* Number of collision reg RD */
  84 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  85 #define EN0_FIFO        0x06    /* FIFO RD */
  86 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  87 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  88 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  89 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  90 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  91 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  92 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  93 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  94 #define EN0_RSR         0x0c    /* rx status reg RD */
  95 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  96 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  97 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  98 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  99 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
 100 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
 101 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
 102 
 103 /* Bits in EN0_ISR - Interrupt status register */
 104 #define ENISR_RX        0x01    /* Receiver, no error */
 105 #define ENISR_TX        0x02    /* Transmitter, no error */
 106 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
 107 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
 108 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
 109 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
 110 #define ENISR_RDC       0x40    /* remote dma complete */
 111 #define ENISR_RESET     0x80    /* Reset completed */
 112 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 113 
 114 /* Bits in EN0_DCFG - Data config register */
 115 #define ENDCFG_WTS      0x01    /* word transfer mode selection */
 116 
 117 /* Page 1 register offsets. */
 118 #define EN1_PHYS   0x01 /* This board's physical enet addr RD WR */
 119 #define EN1_CURPAG 0x07 /* Current memory page RD WR */
 120 #define EN1_MULT   0x08 /* Multicast filter mask array (8 bytes) RD WR */
 121 
 122 /* Bits in received packet status byte and EN0_RSR*/
 123 #define ENRSR_RXOK      0x01    /* Received a good packet */
 124 #define ENRSR_CRC       0x02    /* CRC error */
 125 #define ENRSR_FAE       0x04    /* frame alignment error */
 126 #define ENRSR_FO        0x08    /* FIFO overrun */
 127 #define ENRSR_MPA       0x10    /* missed pkt */
 128 #define ENRSR_PHY       0x20    /* physical/multicase address */
 129 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 130 #define ENRSR_DEF       0x80    /* deferring */
 131 
 132 /* Transmitted packet status, EN0_TSR. */
 133 #define ENTSR_PTX       0x01    /* Packet transmitted without error */
 134 /* The other bits in the TX status register mean:
 135    0x02 The transmit wasn't deferred.
 136    0x04 The transmit collided at least once.
 137    0x08 The transmit collided 16 times, and was deferred.
 138    0x10 The carrier sense was lost (from the ethernet transceiver)
 139    0x20 A "FIFO underrun" (internal error) occured during transmit.
 140    0x40 The collision detect "heartbeat" signal was lost.
 141    0x80 There was an out-of-window collision.
 142    */
 143 
 144 /* The per-packet-header format. */
 145 struct e8390_pkt_hdr {
 146   unsigned char status; /* status */
 147   unsigned char next;   /* pointer to next packet. */
 148   unsigned short count; /* header + packet lenght in bytes */
 149 };
 150 #endif /* e8390_h */
/* */
root/net/inet/8390.h

INCLUDED FROM
