1 /* Generic NS8390 register definitions. */ 2 /* This file is part of Donald Becker's 8390 drivers, and is distributed 3 under the same license. 4 Some of these names and comments originated from the Crynwr 5 packet drivers, which are distributed under the GPL. */ 6 7 #ifndef _8390_h 8 #define _8390_h 9 10 #include <linux/if_ether.h> 11 12 #define TX_2X_PAGES 12 13 #define TX_1X_PAGES 6 14 #define TX_PAGES (ei_status.pingpong ? TX_2X_PAGES : TX_1X_PAGES) 15 16 #define ETHER_ADDR_LEN 6 17 18 /* From 8390.c */ 19 extern int ei_debug; 20 extern struct sigaction ei_sigaction; 21 22 extern int ethif_init(struct device *dev); 23 extern int ethdev_init(struct device *dev); 24 extern void NS8390_init(struct device *dev, int startp); 25 extern int ei_open(struct device *dev); 26 extern void ei_interrupt(int reg_ptr); 27 28 /* From auto_irq.c */ 29 extern struct device *irq2dev_map[16]; 30 extern void autoirq_setup(int waittime); 31 extern int autoirq_report(int waittime); 32 33 /* Most of these entries should be in 'struct device' (or most of the 34 things in there should be here!) */ 35 /* You have one of these per-board */ 36 struct ei_device { 37 char *name; 38 void (*reset_8390)(struct device *); 39 void (*block_output)(struct device *, int, const unsigned char *, int); 40 int (*block_input)(struct device *, int, char *, int); 41 int open:1; 42 int word16:1; /* We have the 16-bit (vs 8-bit) version of the card. */ 43 int txing:1; /* Transmit Active */ 44 int dmaing:2; /* Remote DMA Active */ 45 int irqlock:1; /* 8390's intrs disabled when '1'. */ 46 int pingpong:1; /* Using the ping-pong driver */ 47 unsigned char tx_start_page, rx_start_page, stop_page; 48 unsigned char current_page; /* Read pointer in buffer */ 49 unsigned char interface_num; /* Net port (AUI, 10bT.) to use. */ 50 unsigned char txqueue; /* Tx Packet buffer queue length. */ 51 unsigned char in_interrupt; 52 short tx1, tx2; /* Packet lengths for ping-pong tx. */ 53 short lasttx; /* Alpha version consistency check. */ 54 unsigned char reg0; /* Register '0' in a WD8013 */ 55 unsigned char reg5; /* Register '5' in a WD8013 */ 56 unsigned char saved_irq; /* Original dev->irq value. */ 57 /* The new statistics table. */ 58 struct enet_statistics stat; 59 }; 60 61 #define ei_status (*(struct ei_device *)(dev->priv)) 62 63 /* Some generic ethernet register configurations. */ 64 #define E8390_TX_IRQ_MASK 0xa /* For register EN0_ISR */ 65 #define E8390_RX_IRQ_MASK 0x5 66 #define E8390_RXCONFIG 0x4 /* EN0_RXCR: broadcasts, no multicast,errors */ 67 #define E8390_RXOFF 0x20 /* EN0_RXCR: Accept no packets */ 68 #define E8390_TXCONFIG 0x00 /* EN0_TXCR: Normal transmit mode */ 69 #define E8390_TXOFF 0x02 /* EN0_TXCR: Transmitter off */ 70 71 /* Register accessed at EN_CMD, the 8390 base addr. */ 72 #define E8390_STOP 0x01 /* Stop and reset the chip */ 73 #define E8390_START 0x02 /* Start the chip, clear reset */ 74 #define E8390_TRANS 0x04 /* Transmit a frame */ 75 #define E8390_RREAD 0x08 /* Remote read */ 76 #define E8390_RWRITE 0x10 /* Remote write */ 77 #define E8390_NODMA 0x20 /* Remote DMA */ 78 #define E8390_PAGE0 0x00 /* Select page chip registers */ 79 #define E8390_PAGE1 0x40 /* using the two high-order bits */ 80 #define E8390_PAGE2 0x80 /* Page 3 is invalid. */ 81 82 #define E8390_CMD 0x00 /* The command register (for all pages) */ 83 /* Page 0 register offsets. */ 84 #define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ 85 #define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ 86 #define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ 87 #define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ 88 #define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ 89 #define EN0_TSR 0x04 /* Transmit status reg RD */ 90 #define EN0_TPSR 0x04 /* Transmit starting page WR */ 91 #define EN0_NCR 0x05 /* Number of collision reg RD */ 92 #define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ 93 #define EN0_FIFO 0x06 /* FIFO RD */ 94 #define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ 95 #define EN0_ISR 0x07 /* Interrupt status reg RD WR */ 96 #define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ 97 #define EN0_RSARLO 0x08 /* Remote start address reg 0 */ 98 #define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ 99 #define EN0_RSARHI 0x09 /* Remote start address reg 1 */ 100 #define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ 101 #define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ 102 #define EN0_RSR 0x0c /* rx status reg RD */ 103 #define EN0_RXCR 0x0c /* RX configuration reg WR */ 104 #define EN0_TXCR 0x0d /* TX configuration reg WR */ 105 #define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ 106 #define EN0_DCFG 0x0e /* Data configuration reg WR */ 107 #define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ 108 #define EN0_IMR 0x0f /* Interrupt mask reg WR */ 109 #define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ 110 111 /* Bits in EN0_ISR - Interrupt status register */ 112 #define ENISR_RX 0x01 /* Receiver, no error */ 113 #define ENISR_TX 0x02 /* Transmitter, no error */ 114 #define ENISR_RX_ERR 0x04 /* Receiver, with error */ 115 #define ENISR_TX_ERR 0x08 /* Transmitter, with error */ 116 #define ENISR_OVER 0x10 /* Receiver overwrote the ring */ 117 #define ENISR_COUNTERS 0x20 /* Counters need emptying */ 118 #define ENISR_RDC 0x40 /* remote dma complete */ 119 #define ENISR_RESET 0x80 /* Reset completed */ 120 #define ENISR_ALL 0x3f /* Interrupts we will enable */ 121 122 /* Bits in EN0_DCFG - Data config register */ 123 #define ENDCFG_WTS 0x01 /* word transfer mode selection */ 124 125 /* Page 1 register offsets. */ 126 #define EN1_PHYS 0x01 /* This board's physical enet addr RD WR */ 127 #define EN1_CURPAG 0x07 /* Current memory page RD WR */ 128 #define EN1_MULT 0x08 /* Multicast filter mask array (8 bytes) RD WR */ 129 130 /* Bits in received packet status byte and EN0_RSR*/ 131 #define ENRSR_RXOK 0x01 /* Received a good packet */ 132 #define ENRSR_CRC 0x02 /* CRC error */ 133 #define ENRSR_FAE 0x04 /* frame alignment error */ 134 #define ENRSR_FO 0x08 /* FIFO overrun */ 135 #define ENRSR_MPA 0x10 /* missed pkt */ 136 #define ENRSR_PHY 0x20 /* physical/multicase address */ 137 #define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ 138 #define ENRSR_DEF 0x80 /* deferring */ 139 140 /* Transmitted packet status, EN0_TSR. */ 141 #define ENTSR_PTX 0x01 /* Packet transmitted without error */ 142 #define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ 143 #define ENTSR_COL 0x04 /* The transmit collided at least once. */ 144 #define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ 145 #define ENTSR_CRS 0x10 /* The carrier sense was lost. */ 146 #define ENTSR_FU 0x20 /* A "FIFO underrun" occured during transmit. */ 147 #define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ 148 #define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ 149 150 /* The per-packet-header format. */ 151 struct e8390_pkt_hdr { 152 unsigned char status; /* status */ 153 unsigned char next; /* pointer to next packet. */ 154 unsigned short count; /* header + packet lenght in bytes */ 155 }; 156 #endif /* _8390_h */