root/drivers/scsi/NCR5380.h

/* [previous][next][first][last][top][bottom][index][help] */

INCLUDED FROM


   1 /* 
   2  * NCR 5380 defines
   3  *
   4  * Copyright 1993, Drew Eckhardt
   5  *      Visionary Computing
   6  *      (Unix consulting and custom programming)
   7  *      drew@colorado.edu
   8  *      +1 (303) 440-4894
   9  *
  10  * DISTRIBUTION RELEASE 3
  11  *
  12  * For more information, please consult 
  13  *
  14  * NCR 5380 Family
  15  * SCSI Protocol Controller
  16  * Databook
  17  * NCR Microelectronics
  18  * 1635 Aeroplaza Drive
  19  * Colorado Springs, CO 80916
  20  * 1+ (719) 578-3400
  21  * 1+ (800) 334-5454
  22  */
  23 
  24 /*
  25  * $Log: NCR5380.h,v $
  26  */
  27 
  28 #ifndef NCR5380_H
  29 #define NCR5380_H
  30 
  31 #define NCR5380_PUBLIC_RELEASE 3
  32 
  33 #define NDEBUG_ARBITRATION      0x1
  34 #define NDEBUG_AUTOSENSE        0x2
  35 #define NDEBUG_DMA              0x4
  36 #define NDEBUG_HANDSHAKE        0x8
  37 #define NDEBUG_INFORMATION      0x10
  38 #define NDEBUG_INIT             0x20
  39 #define NDEBUG_INTR             0x40
  40 #define NDEBUG_LINKED           0x80
  41 #define NDEBUG_MAIN             0x100
  42 #define NDEBUG_NO_DATAOUT       0x200
  43 #define NDEBUG_NO_WRITE         0x400
  44 #define NDEBUG_PIO              0x800
  45 #define NDEBUG_PSEUDO_DMA       0x1000
  46 #define NDEBUG_QUEUES           0x2000
  47 #define NDEBUG_RESELECTION      0x4000
  48 #define NDEBUG_SELECTION        0x8000
  49 #define NDEBUG_USLEEP           0x10000
  50 
  51 /* 
  52  * The contents of the OUTPUT DATA register are asserted on the bus when
  53  * either arbitration is occuring or the phase-indicating signals (
  54  * IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
  55  * bit in the INTITIATOR COMMAND register is set.
  56  */
  57 
  58 #define OUTPUT_DATA_REG         0       /* wo DATA lines on SCSI bus */
  59 #define CURRENT_SCSI_DATA_REG   0       /* ro same */
  60 
  61 #define INITIATOR_COMMAND_REG   1       /* rw */
  62 #define ICR_ASSERT_RST          0x80    /* rw Set to assert RST  */
  63 #define ICR_ARBITRATION_PROGRESS 0x40   /* ro Indicates arbitration complete */
  64 #define ICR_TRI_STATE           0x40    /* wo Set to tri-state drivers */
  65 #define ICR_ARBITRATION_LOST    0x20    /* ro Indicates arbitration lost */
  66 #define ICR_DIFF_ENABLE         0x20    /* wo Set to enable diff. drivers */
  67 #define ICR_ASSERT_ACK          0x10    /* rw ini Set to assert ACK */
  68 #define ICR_ASSERT_BSY          0x08    /* rw Set to assert BSY */
  69 #define ICR_ASSERT_SEL          0x04    /* rw Set to assert SEL */
  70 #define ICR_ASSERT_ATN          0x02    /* rw Set to assert ATN */
  71 #define ICR_ASSERT_DATA         0x01    /* rw SCSI_DATA_REG is asserted */
  72 
  73 #ifdef DIFFERENTIAL
  74 #define ICR_BASE                ICR_DIFF_ENABLE
  75 #else
  76 #define ICR_BASE                0
  77 #endif
  78 
  79 #define MODE_REG                2
  80 /*
  81  * Note : BLOCK_DMA code will keep DRQ asserted for the duration of the 
  82  * transfer, causing the chip to hog the bus.  You probably don't want 
  83  * this.
  84  */
  85 #define MR_BLOCK_DMA_MODE       0x80    /* rw block mode DMA */
  86 #define MR_TARGET               0x40    /* rw target mode */
  87 #define MR_ENABLE_PAR_CHECK   0x20      /* rw enable parity checking */
  88 #define MR_ENABLE_PAR_INTR      0x10    /* rw enable bad parity interrupt */
  89 #define MR_ENABLE_EOP_INTR      0x08    /* rw enabble eop interrupt */
  90 #define MR_MONITOR_BSY  0x04    /* rw enable int on unexpected bsy fail */
  91 #define MR_DMA_MODE             0x02    /* rw DMA / pseudo DMA mode */
  92 #define MR_ARBITRATE            0x01    /* rw start arbitration */
  93 
  94 #ifdef PARITY
  95 #define MR_BASE                 MR_ENABLE_PAR_CHECK
  96 #else
  97 #define MR_BASE                 0
  98 #endif
  99 
 100 #define TARGET_COMMAND_REG      3
 101 #define TCR_LAST_BYTE_SENT      0x80    /* ro DMA done */
 102 #define TCR_ASSERT_REQ          0x08    /* tgt rw assert REQ */
 103 #define TCR_ASSERT_MSG          0x04    /* tgt rw assert MSG */
 104 #define TCR_ASSERT_CD           0x02    /* tgt rw assert CD */
 105 #define TCR_ASSERT_IO           0x01    /* tgt rw assert IO */
 106 
 107 #define STATUS_REG              4       /* ro */
 108 /*
 109  * Note : a set bit indicates an active signal, driven by us or another 
 110  * device.
 111  */
 112 #define SR_RST                  0x80    
 113 #define SR_BSY                  0x40
 114 #define SR_REQ                  0x20
 115 #define SR_MSG                  0x10
 116 #define SR_CD                   0x08
 117 #define SR_IO                   0x04
 118 #define SR_SEL                  0x02
 119 #define SR_DBP                  0x01
 120 
 121 /*
 122  * Setting a bit in this register will cause an interrupt to be generated when 
 123  * BSY is false and SEL true and this bit is asserted  on the bus.
 124  */
 125 #define SELECT_ENABLE_REG       4       /* wo */
 126 
 127 #define BUS_AND_STATUS_REG      5       /* ro */
 128 #define BASR_END_DMA_TRANSFER   0x80    /* ro set on end of transfer */
 129 #define BASR_DRQ                0x40    /* ro mirror of DRQ pin */
 130 #define BASR_PARITY_ERROR       0x20    /* ro parity error detected */
 131 #define BASR_IRQ                0x10    /* ro mirror of IRQ pin */
 132 #define BASR_PHASE_MATCH        0x08    /* ro Set when MSG CD IO match TCR */
 133 #define BASR_BUSY_ERROR         0x04    /* ro Unexpected change to inactive state */
 134 #define BASR_ATN                0x02    /* ro BUS status */
 135 #define BASR_ACK                0x01    /* ro BUS status */
 136 
 137 /* Write any value to this register to start a DMA send */
 138 #define START_DMA_SEND_REG      5       /* wo */
 139 
 140 /* 
 141  * Used in DMA transfer mode, data is latched from the SCSI bus on
 142  * the falling edge of REQ (ini) or ACK (tgt)
 143  */
 144 #define INPUT_DATA_REGISTER     6       /* ro */
 145 
 146 /* Write any value to this register to start a DMA recieve */
 147 #define START_DMA_TARGET_RECIEVE_REG    6       /* wo */
 148 
 149 /* Read this register to clear interrupt conditions */
 150 #define RESET_PARITY_INTERRUPT_REG      7       /* ro */
 151 
 152 /* Write any value to this register to start an ini mode DMA recieve */
 153 #define START_DMA_INITIATOR_RECIEVE_REG 7       /* wo */
 154 
 155 /* Note : PHASE_* macros are based on the values of the STATUS register */
 156 #define PHASE_MASK      (SR_MSG | SR_CD | SR_IO)
 157 
 158 #define PHASE_DATAOUT   0
 159 #define PHASE_DATAIN    SR_IO
 160 #define PHASE_CMDOUT    SR_CD
 161 #define PHASE_STATIN    (SR_CD | SR_IO)
 162 #define PHASE_MSGOUT    (SR_MSG | SR_CD)
 163 #define PHASE_MSGIN     (SR_MSG | SR_CD | SR_IO)
 164 #define PHASE_UNKNOWN   0xff
 165 
 166 /* 
 167  * Convert status register phase to something we can use to set phase in 
 168  * the target register so we can get phase mismatch interrupts on DMA 
 169  * transfers.
 170  */
 171  
 172 #define PHASE_SR_TO_TCR(phase) ((phase) >> 2)   
 173 
 174 /*
 175  * The internal should_disconnect() function returns these based on the 
 176  * expected length of a disconnect if a device supports disconnect/
 177  * reconnect.
 178  */
 179 
 180 #define DISCONNECT_NONE         0
 181 #define DISCONNECT_TIME_TO_DATA 1
 182 #define DISCONNECT_LONG         2
 183 
 184 /* 
 185  * These are "special" values for the tag parameter passed to NCR5380_select.
 186  */
 187 
 188 #define TAG_NEXT        -1      /* Use next free tag */
 189 #define TAG_NONE        -2      /* 
 190                                  * Establish I_T_L nexus instead of I_T_L_Q
 191                                  * even on SCSI-II devices.
 192                                  */
 193 
 194 /*
 195  * These are "special" values for the irq field of the instance structure
 196  * and returns from NCR5380_probe_irq.
 197  */
 198 
 199 #define IRQ_NONE        255
 200 #define IRQ_AUTO        254
 201 
 202 
 203 #ifndef ASM
 204 struct NCR5380_hostdata {
 205     NCR5380_implementation_fields;              /* implmenentation specific */
 206     unsigned char id_mask, id_higher_mask;      /* 1 << id, all bits greater */
 207     volatile unsigned char busy[8];             /* index = target, bit = lun */
 208 #ifdef REAL_DMA
 209     volatile int dma_len;                       /* requested length of DMA */
 210 #endif
 211     volatile unsigned char last_message;        /* last message OUT */
 212     volatile Scsi_Cmnd *connected;              /* currently connected command */
 213     volatile Scsi_Cmnd *issue_queue;            /* waiting to be issued */
 214     volatile Scsi_Cmnd *disconnected_queue;     /* waiting for reconnect */
 215 #ifdef USLEEP
 216     unsigned long time_expires;                 /* in jiffies, set prior to sleeping */
 217     struct Scsi_Host *next_timer;
 218 #endif
 219 };
 220 
 221 #ifdef __KERNEL__
 222 static struct Scsi_Host *first_instance;                /* linked list of 5380's */
 223 
 224 #if defined(AUTOPROBE_IRQ)
 225 static int NCR5380_probe_irq (struct Scsi_Host *instance, int possible);
 226 #endif
 227 static void NCR5380_init (struct Scsi_Host *instance);
 228 static void NCR5380_information_transfer (struct Scsi_Host *instance);
 229 static void NCR5380_intr (int irq);
 230 static void NCR5380_main (void);
 231 static void NCR5380_print_options (struct Scsi_Host *instance);
 232 #ifndef NCR5380_abort
 233 static
 234 #endif
 235 int NCR5380_abort (Scsi_Cmnd *cmd, int code);
 236 #ifndef NCR5380_reset
 237 static
 238 #endif
 239 int NCR5380_reset (Scsi_Cmnd *);
 240 #ifndef NCR5380_queue_command
 241 static 
 242 #endif
 243 int NCR5380_queue_command (Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *));
 244 
 245 
 246 static void NCR5380_reselect (struct Scsi_Host *instance);
 247 static int NCR5380_select (struct Scsi_Host *instance, Scsi_Cmnd *cmd, int tag);
 248 #if defined(PSEUDO_DMA) || defined(REAL_DMA)
 249 static int NCR5380_transfer_dma (struct Scsi_Host *instance,
 250         unsigned char *phase, int *count, unsigned char **data);
 251 #endif
 252 static int NCR5380_transfer_pio (struct Scsi_Host *instance,
 253         unsigned char *phase, int *count, unsigned char **data);
 254 
 255 #endif __KERNEL_
 256 #endif /* ndef ASM */
 257 #endif /* NCR5380_H */

/* [previous][next][first][last][top][bottom][index][help] */