1 /* 2 * include/linux/serial.h 3 * 4 * Copyright (C) 1992 by Theodore Ts'o. 5 * 6 * Redistribution of this file is permitted under the terms of the GNU 7 * Public License (GPL) 8 */ 9 10 /* 11 * This is our internal structure for each serial port's state. 12 * 13 * Many fields are paralleled by the structure used by the serial_struct 14 * structure. 15 * 16 * For definitions of the flags field, see tty.h 17 */ 18 19 struct async_struct { 20 int baud_base; 21 int port; 22 int irq; 23 int flags; 24 int type; 25 struct tty_struct *tty; 26 unsigned long timer; 27 int timeout; 28 int xmit_fifo_size; 29 int custom_divisor; 30 int x_char; /* xon/xoff characater */ 31 int event; 32 int line; 33 struct async_struct *next_port; /* For the linked list */ 34 struct async_struct *prev_port; 35 36 }; 37 38 /* 39 * Events are used to schedule things to happen at timer-interrupt 40 * time, instead of at rs interrupt time. 41 */ 42 #define RS_EVENT_READ_PROCESS 0 43 #define RS_EVENT_WRITE_WAKEUP 1 44 #define RS_EVENT_HUP_PGRP 2 45 #define RS_EVENT_BREAK_INT 3 46 #define RS_EVENT_DO_SAK 4 47 48 /* 49 * These are the UART port assignments, expressed as offsets from the base 50 * register. These assignments should hold for any serial port based on 51 * a 8250, 16450, or 16550(A). 52 */ 53 #define UART_RX 0 /* In: Receive buffer (DLAB=0) */ 54 #define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 55 #define UART_DLL 0 /* Out: Devisor Latch Low (DLAB=1) */ 56 #define UART_DLM 1 /* Out: Devisor Latch High (DLAB=1) */ 57 #define UART_IER 1 /* Out: Interrupt Enable Register */ 58 #define UART_IIR 2 /* In: Interrupt ID Register */ 59 #define UART_FCR 2 /* Out: FIFO Control Register */ 60 #define UART_LCR 3 /* Out: Line Control Register */ 61 #define UART_MCR 4 /* Out: Modem Control Register */ 62 #define UART_LSR 5 /* In: Line Status Register */ 63 #define UART_MSR 6 /* In: Modem Status Register */ 64 #define UART_SCR 7 /* I/O: Scratch Register */ 65 66 /* 67 * These are the definitions for the FIFO Control Register 68 */ 69 #define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ 70 #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ 71 #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ 72 #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ 73 #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ 74 #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ 75 #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ 76 #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ 77 #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ 78 79 #define UART_FCR_CLEAR_CMD (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT) 80 #define UART_FCR_SETUP_CMD (UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8) 81 82 /* 83 * These are the definitions for the Line Control Register 84 * 85 * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting 86 * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. 87 */ 88 #define UART_LCR_DLAB 0x80 /* Devisor latch access bit */ 89 #define UART_LCR_SBC 0x40 /* Set break control */ 90 #define UART_LCR_SPAR 0x20 /* Stick parity (?) */ 91 #define UART_LCR_EPAR 0x10 /* Even paraity select */ 92 #define UART_LCR_PARITY 0x08 /* Parity Enable */ 93 #define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ 94 #define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ 95 #define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ 96 #define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ 97 #define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ 98 99 /* 100 * These are the definitions for the Line Status Register 101 */ 102 #define UART_LSR_TEMT 0x40 /* Transmitter empty */ 103 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 104 #define UART_LSR_BI 0x10 /* Break interrupt indicator */ 105 #define UART_LSR_FE 0x08 /* Frame error indicator */ 106 #define UART_LSR_PE 0x04 /* Parity error indicator */ 107 #define UART_LSR_OE 0x02 /* Overrun error indicator */ 108 #define UART_LSR_DR 0x01 /* Receiver data ready */ 109 110 /* 111 * These are the definitions for the Interrupt Indentification Register 112 */ 113 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */ 114 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ 115 116 #define UART_IIR_MSI 0x00 /* Modem status interrupt */ 117 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ 118 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */ 119 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ 120 121 /* 122 * These are the definitions for the Interrupt Enable Register 123 */ 124 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ 125 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ 126 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ 127 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ 128 129 /* 130 * These are the definitions for the Modem Control Register 131 */ 132 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 133 #define UART_MCR_OUT2 0x08 /* Out2 complement */ 134 #define UART_MCR_OUT1 0x04 /* Out1 complement */ 135 #define UART_MCR_RTS 0x02 /* RTS complement */ 136 #define UART_MCR_DTR 0x01 /* DTR complement */ 137 138 /* 139 * These are the definitions for the Modem Status Register 140 */ 141 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 142 #define UART_MSR_RI 0x40 /* Ring Indicator */ 143 #define UART_MSR_DSR 0x20 /* Data Set Ready */ 144 #define UART_MSR_CTS 0x10 /* Clear to Send */ 145 #define UART_MSR_DDCD 0x08 /* Delta DCD */ 146 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ 147 #define UART_MSR_DDSR 0x02 /* Delta DSR */ 148 #define UART_MSR_DCTS 0x01 /* Delta CTS */ 149 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */