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1 /* wereg.h */
2 /*
3 Copyright (C) 1992 Ross Biro
4
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 1, or (at your option)
8 any later version.
9
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
14
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18
19 The Author may be reached as bir7@leland.stanford.edu or
20 C/O Department of Mathematics; Stanford University; Stanford, CA 94305
21 */
22 /* $Id: wereg.h,v 0.8.4.1 1992/11/10 00:17:18 bir7 Exp $ */
23 /* $Log: wereg.h,v $
24 * Revision 0.8.4.1 1992/11/10 00:17:18 bir7
25 * version change only.
26 *
27 * Revision 0.8.3.2 1992/11/10 00:14:47 bir7
28 * Changed malloc to kmalloc and added $iId$ and $Log: wereg.h,v $
29 * Revision 0.8.4.1 1992/11/10 00:17:18 bir7
30 * version change only.
31 *.
32 * */
33
34 /* This is based on if_wereg.h from bsd386 */
35
36 /* Uncomment the next line if you are having troubles with your
37 8 bit card being recognized as 16 bit. */
38 /* #define FORCE_8BIT */
39
40 struct wd_ring
41 {
42 unsigned char status; /* status */
43 /* format of status
44 bit
45 0 packet ok
46 1 crc error
47 2 frame alignment error
48 3 fifo overrun
49 */
50 #define STRECVD 0xf1
51 unsigned char next; /* pointer to next packet. */
52 unsigned short count; /*packet lenght in bytes + 4 */
53 };
54
55 /* Format of command register.
56 bits
57 0 stop
58 1 start
59 2 transmit packet
60 3-5 Remote DMA command
61 6-7 Page Select */
62
63 #define CSTOP 0x1
64 #define CSTART 0x2
65 #define CTRANS 0x4
66 #define CRDMA 0x38
67 #define CRDMA_SHIFT 3
68 #define CPAGE 0xc0
69 #define CPAGE_SHIFT 6
70
71 #define CPAGE1 0x40
72
73
74 #define CPAGE1 0x40
75
76 /* interrupt status defenitions
77 bits
78 0 Recv.
79 1 Transmit
80 2 RcvErr
81 3 Transmit Err
82 4 Overwrite warning
83 5 Counter overflow
84 6 Remote DMA complete
85 7 Reset Status */
86
87 #define IRCV 0x1
88 #define ITRS 0x2
89 #define IRCE 0x4
90 #define ITRE 0x8
91 #define IOVER 0x10
92 #define ICOUNTERS 0x20
93 #define IDMA 0x40
94 #define IRESET 0x80
95 #define IOVER 0x10
96 #define ICOUNTERS 0x20
97 #define IDMA 0x40
98 #define IRESET 0x80
99
100 /* transmit status format
101 bits
102 0 Packet transmitted ok.
103 1 Non Deferred transmition
104 2 Transmit collied
105 3 Transmit aborted
106 4 Carrier Sense Lost
107 5 Fifo Underrun
108 6 CD Heartbeat
109 7 Out of Window Collision */
110
111 #define TROK 0x1
112 #define TRAB 0x4
113
114 /* Some ID stuff */
115 #define WD_ID1 0x03
116 #define WD_ID2 0x05
117 #define WD_CHECK 0xff
118 #define WD_PAGE 256 /* page size in bytes. */
119 #define WD_TXBS 6 /* size of transmit buffer in pages. */
120 #define WD_MAX_PAGES 32 /* Number of pages off ram on card (8k) */
121 #define WD_NIC 16 /* i/o base offset to NIC */
122
123 /* Some configuration stuff. */
124 /* where the memory is mapped in. */
125 #define WD_MEM (dev->mem_start)
126 #define WD_BUFFEND (dev->mem_end)
127 #define WD_MEMSIZE (WD_BUFFEND-WD_MEM)
128 #define WD_BASE (dev->base_addr)
129
130 #define TRANS_MASK 0xa
131 #define RECV_MASK 0x5
132 #define WD_DCONFIG 0x48
133 #define WD_RCONFIG 0x4
134 #define WD_MCONFIG 0x20
135 #define WD_TCONFIG 0x0
136 #define WD_IMEM (((WD_MEM>>13) & 0x3f)|0x40)
137
138 /* WD registers. */
139 #define WD_ROM (WD_BASE+8)
140 #define WD_CTL (WD_BASE+0)
141
142 /* WD NIC register offsets */
143 #define WD_COMM (WD_BASE+WD_NIC+0x00) /* command register */
144 #define WD_PSTRT (WD_BASE+WD_NIC+0x01) /* page start register */
145 #define WD_PSTOP (WD_BASE+WD_NIC+0x02) /* page stop register */
146 #define WD_BNDR (WD_BASE+WD_NIC+0x03) /* Boundary Pointer */
147 #define WD_TRST (WD_BASE+WD_NIC+0x04) /* Transmit Status */
148 #define WD_TRPG (WD_BASE+WD_NIC+0x04) /* Transmit Page */
149 #define WD_TB0 (WD_BASE+WD_NIC+0x05) /* Transmit byte count, low */
150 #define WD_TB1 (WD_BASE+WD_NIC+0x06) /* Transmit byte count, high */
151 #define WD_ISR (WD_BASE+WD_NIC+0x07) /* Interrupt status register */
152 #define WD_RBY0 (WD_BASE+WD_NIC+0x0a) /* remote byte count low. */
153 #define WD_RBY1 (WD_BASE+WD_NIC+0x0b) /* remote byte count high. */
154 #define WD_RCC (WD_BASE+WD_NIC+0x0c) /* receive configuration */
155 #define WD_TRC (WD_BASE+WD_NIC+0x0d) /* transmit configuration */
156 #define WD_DCR (WD_BASE+WD_NIC+0x0e) /* data configuration */
157 #define WD_IMR (WD_BASE+WD_NIC+0x0f) /* Interrupt Mask register. */
158 #define WD_PAR0 (WD_BASE+WD_NIC+0x01)
159 #define WD_CUR (WD_BASE+WD_NIC+0x07)
160 #define WD_MAR0 (WD_BASE+WD_NIC+0x08)
161
162 /* rth additions */
163
164 #define EN_CMD (WD_BASE+0)
165 #define EN_REG1 (WD_BASE+1)
166 #define EN_REG5 (WD_BASE+5)
167 #define EN_SAPROM (WD_BASE+8)
168 #define EN_REGE (WD_BASE+0x0e)
169 #define EN_OFFSET 16
170
171 /* WD Commands for EN_CMD */
172 #define EN_RESET
173 #define EN_MEMEN 0x40
174 #define EN_MEM_MASK 0x3f
175
176 /* WD Bus Register bits */
177 #define BUS16 1
178
179 /* WD REG5 Commands */
180 #define MEM16ENABLE 0x80
181 #define LAN16ENABLE 0x40
182 #define MEMMASK 0x1f
183 #define BIT19 0x1
184
185 /* Memory test pattern to use */
186 #define TESTPATTERN 0x5a
187
188 /* Western Digital Additional Registers */
189
190 /* National Semiconductor Definitions */
191
192 /* Page 0 */
193 #define CR (WD_BASE+WD_NIC+0) /* RW - Command */
194 #define CLDA0 (WD_BASE+WD_NIC+1) /* R - Current Local DMA Address 0 */
195 #define PSTART (WD_BASE+WD_NIC+1) /* W - Page Start Register */
196 #define CLDA1 (WD_BASE+WD_NIC+2) /* R - Current Local DMA Address 1 */
197 #define PSTOP (WD_BASE+WD_NIC+2) /* W - Page Stop Register */
198 #define BNRY (WD_BASE+WD_NIC+3) /* RW - Boundry Pointer */
199 #define TSR (WD_BASE+WD_NIC+4) /* R - Transmit Status Register */
200 #define TPSR (WD_BASE+WD_NIC+4) /* W - Transmit Page Start */
201 #define NCR (WD_BASE+WD_NIC+5) /* R - Number of Collisions */
202 #define TBCR0 (WD_BASE+WD_NIC+5) /* W - Transmit Byte Count 0 */
203 #define FIFO (WD_BASE+WD_NIC+6) /* R - FIFO */
204 #define TBCR1 (WD_BASE+WD_NIC+6) /* W - Transmit Byte Count 1 */
205 #define ISR (WD_BASE+WD_NIC+7) /* RW - Interrupt Status Register */
206 #define CRDA0 (WD_BASE+WD_NIC+8) /* R - Current Remote DMA Address 0 */
207 #define RSAR0 (WD_BASE+WD_NIC+8) /* W - Remote Start Address 0 */
208 #define CRDA1 (WD_BASE+WD_NIC+9) /* R - Current Remote DMA Address 1 */
209 #define RSAR1 (WD_BASE+WD_NIC+9) /* W - Remote Start Address 1 */
210 /* R - Reserved */
211 #define RBCR0 (WD_BASE+WD_NIC+0x0a) /* W - Remote Byte Count 0 */
212 /* R - Reserved */
213 #define RBCR1 (WD_BASE+WD_NIC+0x0b) /* W - Remote Byte Count 1 */
214 #define RSR (WD_BASE+WD_NIC+0x0c) /* R - Receive Status Register */
215 #define RCR (WD_BASE+WD_NIC+0x0c) /* W - Receive Configuration */
216 #define CNTR0 (WD_BASE+WD_NIC+0x0d) /* R - Frame Alignment Errors 0 */
217 #define TCR (WD_BASE+WD_NIC+0x0d) /* W - Transmit Configuration */
218 #define CNTR1 (WD_BASE+WD_NIC+0x0e) /* R - Frame Alignment Errors 1 */
219 #define DCR (WD_BASE+WD_NIC+0x0e) /* W - Data Configuration */
220 #define CNTR2 (WD_BASE+WD_NIC+0x0f) /* R - Missed Packet Errors */
221 #define IMR (WD_BASE+WD_NIC+0x0f) /* W - Interrupt Mask Register */
222
223 /* Page 1 */
224 /* RW - Command */
225 #define PAR0 (WD_BASE+WD_NIC+0x01) /* RW - Physical Address 0 */
226 #define PAR1 (WD_BASE+WD_NIC+0x02) /* RW - Physical Address 1 */
227 #define PAR2 (WD_BASE+WD_NIC+0x03) /* RW - Physical Address 2 */
228 #define PAR3 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 3 */
229 #define PAR4 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 4 */
230 #define PAR5 (WD_BASE+WD_NIC+0x05) /* RW - Physical Address 5 */
231 #define PAR6 (WD_BASE+WD_NIC+0x06) /* RW - Physical Address 6 */
232 #define CURR (WD_BASE+WD_NIC+0x07) /* RW - Current Page */
233 #define MAR0 (WD_BASE+WD_NIC+0x08) /* RW - Multicast Address 0 */
234 #define MAR1 (WD_BASE+WD_NIC+0x09) /* RW - Multicast Address 1 */
235 #define MAR2 (WD_BASE+WD_NIC+0x0a) /* RW - Multicast Address 2 */
236 #define MAR3 (WD_BASE+WD_NIC+0x0b) /* RW - Multicast Address 3 */
237 #define MAR4 (WD_BASE+WD_NIC+0x0c) /* RW - Multicast Address 4 */
238 #define MAR5 (WD_BASE+WD_NIC+0x0d) /* RW - Multicast Address 5 */
239 #define MAR6 (WD_BASE+WD_NIC+0x0e) /* RW - Multicast Address 6 */
240 #define MAR7 (WD_BASE+WD_NIC+0x0f) /* RW - Multicast Address 7 */
241
242 /* Page 2 */
243 /* Page 2 Registers are RW opposite Page 0 */
244 /* and should be used for diagnostic purposes only */
245
246 /* Command Register bits */
247 #define STOP 1 /* In progress jobs finished, software reset */
248 #define STA 2 /* Activate the NIC */
249 #define TXP 4 /* Initiate TX packet */
250 #define RD0 8 /* Remote DMA commands */
251 #define RD1 0x10
252 #define RD2 0x20
253 #define PS0 0x40 /* Page Select */
254 #define PS1 0x80 /* 00 = 0, 01 = 1, 10 = 2, 11 = reserved */
255
256 #define PAGE0 ~(PS0|PS1) /* Remember to AND this */
257 #define PAGE1 PS0 /* these can be OR'd */
258 #define PAGE2 PS1
259 #define NO_DMA RD2
260
261 /* Interrupt Status Register bits */
262 #define PRX 1 /* Packet received with no errors */
263 #define PTX 2 /* Packet transmitted with no errors */
264 #define RXE 4 /* Packet received with errors */
265 #define TXE 8 /* Transmit aborted with errors */
266 #define OVW 0x10 /* Overwrite warning */
267 #define CNT 0x20 /* Counter overflow warning */
268 #define RDC 0x40 /* Remote DMA complete */
269 #define RST 0x80 /* Reset status - does not cause interrupts */
270
271 /* Interrupt Mask Register - 1 = enabled */
272 #define PRXE 1 /* Packet received */
273 #define PTXE 2 /* Packet transmitted */
274 #define RXEE 4 /* Receive error */
275 #define TXEE 8 /* Transmit error */
276 #define OVWE 0x10 /* Overwrite error */
277 #define CNTE 0x20 /* Counter overflow */
278 #define RDCE 0x40 /* Remote DMA complete */
279
280 /* Data Configuration Register */
281 #define WTS 1 /* Word Transfer 0 = byte, 1 = word */
282 #define BOS 2 /* Byte Order 0 = 8086, 1 = 68000 */
283 #define LAS 4 /* Long Address 0 = 16bit, 1 = 32 bit DMA */
284 #define LS 8 /* Loopback = 0, 1 = Normal */
285 #define AR 0x10 /* Autoinitialize = 1 DMA, 0 = software */
286 #define FT0 0x20 /* FIFO Threshold (word mode /2 ) */
287 #define FT1 0x40 /* 00 = 2, 01 = 4, 10 = 8, 11 = 12 bytes */
288
289 /* Transmit Configuration Register */
290 #define CRCI 1 /* CRC inhibit = 1, append = 0 */
291 #define LB0 2 /* Loopback control 00 = normal loopback */
292 #define LB1 4 /* 01 = internal, 10 = external1, 11 = external2 */
293 #define ATD 8 /* Auto Transmit Enable = 1 tx inhibit enabled */
294 #define OFST 0x10 /* Collision offset 1 = modify to low priority mode */
295
296 /* Transmitter Status Register */
297 #define PTXOK 1 /* Packet transmitted without error */
298 /* reserved */
299 #define COL 4 /* Transmit collided, check NCR for count */
300 #define ABT 8 /* Transmit aborted - 16 tries */
301 #define CRS 0x10 /* Carrier Sense lost */
302 #define FU 0x20 /* FIFO underrun */
303 #define CDH 0x40 /* CD Heartbeat failed */
304 #define OWC 0x80 /* Out of window collision */
305
306 /* Receive configuration Register */
307 #define SEP 1 /* Save error packets = 1 */
308 #define ARUNT 2 /* Accept RUNT packets < 64 bytes */
309 #define AB 4 /* Accept Broadcast packets */
310 #define AM 8 /* Accept Multicast packets */
311 #define PRO 0x10 /* Promiscuous mode */
312 #define MON 0x20 /* Monitor mode */
313
314 /* Receive Status Register */
315 #define PRX 1 /* Packet received without error */
316 #define CRC 2 /* CRC error */
317 #define FAE 4 /* Frame Alignment error */
318 #define FO 8 /* FIFO overrun error */
319 #define MPA 0x10 /* Missed packet */
320 #define PHY 0x20 /* Physical = 0, Multicast/Broadcast = 1 */
321 #define DIS 0x40 /* Receiver disabled (monitor mode) */
322 #define DFR 0x80 /* Deferring - jabber on line */
323
324
325 /* rth additions */
326
327 #define EN_CMD (WD_BASE+0)
328 #define EN_REG1 (WD_BASE+1)
329 #define EN_REG5 (WD_BASE+5)
330 #define EN_SAPROM (WD_BASE+8)
331 #define EN_REGE (WD_BASE+0x0e)
332 #define EN_OFFSET 16
333
334 /* WD Commands for EN_CMD */
335 #define EN_RESET
336 #define EN_MEMEN 0x40
337 #define EN_MEM_MASK 0x3f
338
339 /* WD Bus Register bits */
340 #define BUS16 1
341
342 /* WD REG5 Commands */
343 #define MEM16ENABLE 0x80
344 #define LAN16ENABLE 0x40
345 #define MEMMASK 0x1f
346 #define BIT19 0x1
347
348 /* Memory test pattern to use */
349 #define TESTPATTERN 0x5a
350
351 /* Western Digital Additional Registers */
352
353 /* National Semiconductor Definitions */
354
355 /* Page 0 */
356 #define CR (WD_BASE+WD_NIC+0) /* RW - Command */
357 #define CLDA0 (WD_BASE+WD_NIC+1) /* R - Current Local DMA Address 0 */
358 #define PSTART (WD_BASE+WD_NIC+1) /* W - Page Start Register */
359 #define CLDA1 (WD_BASE+WD_NIC+2) /* R - Current Local DMA Address 1 */
360 #define PSTOP (WD_BASE+WD_NIC+2) /* W - Page Stop Register */
361 #define BNRY (WD_BASE+WD_NIC+3) /* RW - Boundry Pointer */
362 #define TSR (WD_BASE+WD_NIC+4) /* R - Transmit Status Register */
363 #define TPSR (WD_BASE+WD_NIC+4) /* W - Transmit Page Start */
364 #define NCR (WD_BASE+WD_NIC+5) /* R - Number of Collisions */
365 #define TBCR0 (WD_BASE+WD_NIC+5) /* W - Transmit Byte Count 0 */
366 #define FIFO (WD_BASE+WD_NIC+6) /* R - FIFO */
367 #define TBCR1 (WD_BASE+WD_NIC+6) /* W - Transmit Byte Count 1 */
368 #define ISR (WD_BASE+WD_NIC+7) /* RW - Interrupt Status Register */
369 #define CRDA0 (WD_BASE+WD_NIC+8) /* R - Current Remote DMA Address 0 */
370 #define RSAR0 (WD_BASE+WD_NIC+8) /* W - Remote Start Address 0 */
371 #define CRDA1 (WD_BASE+WD_NIC+9) /* R - Current Remote DMA Address 1 */
372 #define RSAR1 (WD_BASE+WD_NIC+9) /* W - Remote Start Address 1 */
373 /* R - Reserved */
374 #define RBCR0 (WD_BASE+WD_NIC+0x0a) /* W - Remote Byte Count 0 */
375 /* R - Reserved */
376 #define RBCR1 (WD_BASE+WD_NIC+0x0b) /* W - Remote Byte Count 1 */
377 #define RSR (WD_BASE+WD_NIC+0x0c) /* R - Receive Status Register */
378 #define RCR (WD_BASE+WD_NIC+0x0c) /* W - Receive Configuration */
379 #define CNTR0 (WD_BASE+WD_NIC+0x0d) /* R - Frame Alignment Errors 0 */
380 #define TCR (WD_BASE+WD_NIC+0x0d) /* W - Transmit Configuration */
381 #define CNTR1 (WD_BASE+WD_NIC+0x0e) /* R - Frame Alignment Errors 1 */
382 #define DCR (WD_BASE+WD_NIC+0x0e) /* W - Data Configuration */
383 #define CNTR2 (WD_BASE+WD_NIC+0x0f) /* R - Missed Packet Errors */
384 #define IMR (WD_BASE+WD_NIC+0x0f) /* W - Interrupt Mask Register */
385
386 /* Page 1 */
387 /* RW - Command */
388 #define PAR0 (WD_BASE+WD_NIC+0x01) /* RW - Physical Address 0 */
389 #define PAR1 (WD_BASE+WD_NIC+0x02) /* RW - Physical Address 1 */
390 #define PAR2 (WD_BASE+WD_NIC+0x03) /* RW - Physical Address 2 */
391 #define PAR3 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 3 */
392 #define PAR4 (WD_BASE+WD_NIC+0x04) /* RW - Physical Address 4 */
393 #define PAR5 (WD_BASE+WD_NIC+0x05) /* RW - Physical Address 5 */
394 #define PAR6 (WD_BASE+WD_NIC+0x06) /* RW - Physical Address 6 */
395 #define CURR (WD_BASE+WD_NIC+0x07) /* RW - Current Page */
396 #define MAR0 (WD_BASE+WD_NIC+0x08) /* RW - Multicast Address 0 */
397 #define MAR1 (WD_BASE+WD_NIC+0x09) /* RW - Multicast Address 1 */
398 #define MAR2 (WD_BASE+WD_NIC+0x0a) /* RW - Multicast Address 2 */
399 #define MAR3 (WD_BASE+WD_NIC+0x0b) /* RW - Multicast Address 3 */
400 #define MAR4 (WD_BASE+WD_NIC+0x0c) /* RW - Multicast Address 4 */
401 #define MAR5 (WD_BASE+WD_NIC+0x0d) /* RW - Multicast Address 5 */
402 #define MAR6 (WD_BASE+WD_NIC+0x0e) /* RW - Multicast Address 6 */
403 #define MAR7 (WD_BASE+WD_NIC+0x0f) /* RW - Multicast Address 7 */
404
405 /* Page 2 */
406 /* Page 2 Registers are RW opposite Page 0 */
407 /* and should be used for diagnostic purposes only */
408
409 /* Command Register bits */
410 #define STOP 1 /* In progress jobs finished, software reset */
411 #define STA 2 /* Activate the NIC */
412 #define TXP 4 /* Initiate TX packet */
413 #define RD0 8 /* Remote DMA commands */
414 #define RD1 0x10
415 #define RD2 0x20
416 #define PS0 0x40 /* Page Select */
417 #define PS1 0x80 /* 00 = 0, 01 = 1, 10 = 2, 11 = reserved */
418
419 #define PAGE0 ~(PS0|PS1) /* Remember to AND this */
420 #define PAGE1 PS0 /* these can be OR'd */
421 #define PAGE2 PS1
422 #define NO_DMA RD2
423
424 /* Interrupt Status Register bits */
425 #define PRX 1 /* Packet received with no errors */
426 #define PTX 2 /* Packet transmitted with no errors */
427 #define RXE 4 /* Packet received with errors */
428 #define TXE 8 /* Transmit aborted with errors */
429 #define OVW 0x10 /* Overwrite warning */
430 #define CNT 0x20 /* Counter overflow warning */
431 #define RDC 0x40 /* Remote DMA complete */
432 #define RST 0x80 /* Reset status - does not cause interrupts */
433
434 /* Interrupt Mask Register - 1 = enabled */
435 #define PRXE 1 /* Packet received */
436 #define PTXE 2 /* Packet transmitted */
437 #define RXEE 4 /* Receive error */
438 #define TXEE 8 /* Transmit error */
439 #define OVWE 0x10 /* Overwrite error */
440 #define CNTE 0x20 /* Counter overflow */
441 #define RDCE 0x40 /* Remote DMA complete */
442
443 /* Data Configuration Register */
444 #define WTS 1 /* Word Transfer 0 = byte, 1 = word */
445 #define BOS 2 /* Byte Order 0 = 8086, 1 = 68000 */
446 #define LAS 4 /* Long Address 0 = 16bit, 1 = 32 bit DMA */
447 #define LS 8 /* Loopback = 0, 1 = Normal */
448 #define AR 0x10 /* Autoinitialize = 1 DMA, 0 = software */
449 #define FT0 0x20 /* FIFO Threshold (word mode /2 ) */
450 #define FT1 0x40 /* 00 = 2, 01 = 4, 10 = 8, 11 = 12 bytes */
451
452 /* Transmit Configuration Register */
453 #define CRCI 1 /* CRC inhibit = 1, append = 0 */
454 #define LB0 2 /* Loopback control 00 = normal loopback */
455 #define LB1 4 /* 01 = internal, 10 = external1, 11 = external2 */
456 #define ATD 8 /* Auto Transmit Enable = 1 tx inhibit enabled */
457 #define OFST 0x10 /* Collision offset 1 = modify to low priority mode */
458
459 /* Transmitter Status Register */
460 #define PTXOK 1 /* Packet transmitted without error */
461 /* reserved */
462 #define COL 4 /* Transmit collided, check NCR for count */
463 #define ABT 8 /* Transmit aborted - 16 tries */
464 #define CRS 0x10 /* Carrier Sense lost */
465 #define FU 0x20 /* FIFO underrun */
466 #define CDH 0x40 /* CD Heartbeat failed */
467 #define OWC 0x80 /* Out of window collision */
468
469 /* Receive configuration Register */
470 #define SEP 1 /* Save error packets = 1 */
471 #define ARUNT 2 /* Accept RUNT packets < 64 bytes */
472 #define AB 4 /* Accept Broadcast packets */
473 #define AM 8 /* Accept Multicast packets */
474 #define PRO 0x10 /* Promiscuous mode */
475 #define MON 0x20 /* Monitor mode */
476
477 /* Receive Status Register */
478 #define PRX 1 /* Packet received without error */
479 #define CRC 2 /* CRC error */
480 #define FAE 4 /* Frame Alignment error */
481 #define FO 8 /* FIFO overrun error */
482 #define MPA 0x10 /* Missed packet */
483 #define PHY 0x20 /* Physical = 0, Multicast/Broadcast = 1 */
484 #define DIS 0x40 /* Receiver disabled (monitor mode) */
485 #define DFR 0x80 /* Deferring - jabber on line */
486
487
488
489
490
![[top]](../icons/top.png){kind=icon}
![[bottom]](../icons/n_bottom.png){kind=icon}
*/