| tag | line | file | source code |
|---|
| EL2H | 15 | drivers/net/3c503.h | #define E33G_STARTPG (EL2H+0) /* Start page, matching EN0_STARTPG */ |
| EL2H | 16 | drivers/net/3c503.h | #define E33G_STOPPG (EL2H+1) /* Stop page, must match EN0_STOPPG */ |
| EL2H | 17 | drivers/net/3c503.h | #define E33G_DRQCNT (EL2H+2) /* DMA burst count */ |
| EL2H | 18 | drivers/net/3c503.h | #define E33G_IOBASE (EL2H+3) /* Read of I/O base jumpers. */ |
| EL2H | 20 | drivers/net/3c503.h | #define E33G_ROMBASE (EL2H+4) /* Read of memory base jumpers. */ |
| EL2H | 21 | drivers/net/3c503.h | #define E33G_GACFR (EL2H+5) /* Config/setup bits for the ASIC GA */ |
| EL2H | 22 | drivers/net/3c503.h | #define E33G_CNTRL (EL2H+6) /* Board's main control register */ |
| EL2H | 23 | drivers/net/3c503.h | #define E33G_STATUS (EL2H+7) /* Status on completions. */ |
| EL2H | 24 | drivers/net/3c503.h | #define E33G_IDCFR (EL2H+8) /* Interrupt/DMA config register */ |
| EL2H | 26 | drivers/net/3c503.h | #define E33G_DMAAH (EL2H+9) /* High byte of DMA address reg */ |
| EL2H | 27 | drivers/net/3c503.h | #define E33G_DMAAL (EL2H+10) /* Low byte of DMA address reg */ |
| EL2H | 30 | drivers/net/3c503.h | #define E33G_VP2 (EL2H+11) |
| EL2H | 31 | drivers/net/3c503.h | #define E33G_VP1 (EL2H+12) |
| EL2H | 32 | drivers/net/3c503.h | #define E33G_VP0 (EL2H+13) |
| EL2H | 33 | drivers/net/3c503.h | #define E33G_FIFOH (EL2H+14) /* FIFO for programmed I/O moves */ |
| EL2H | 34 | drivers/net/3c503.h | #define E33G_FIFOL (EL2H+15) /* ... low byte of above. */ |