1 /* depca.c: A DIGITAL DEPCA & EtherWORKS ethernet driver for linux. 2
3 Written 1994 by David C. Davies. 4
5
6 Copyright 1994 David C. Davies 7 and 8 United States Government 9 (as represented by the Director, National Security Agency). 10
11
12 This software may be used and distributed according to the terms of 13 the GNU Public License, incorporated herein by reference. 14
15 This driver is written for the Digital Equipment Corporation series 16 of DEPCA and EtherWORKS ethernet cards: 17
18 DEPCA (the original) 19 DE100 20 DE200 Turbo 21 DE201 Turbo 22 DE202 Turbo (TP BNC) 23 DE210 24 DE422 (EISA) 25
26 The driver has been tested on DE100, DE200 and DE202 cards in a 27 relatively busy network. The DE422 has been tested a little. 28
29 This driver will NOT work for the DE203, DE204 and DE205 series of 30 cards, since they have a new custom ASIC in place of the AMD LANCE 31 chip. 32
33 The author may be reached as davies@wanton.lkg.dec.com or 34 Digital Equipment Corporation, 550 King Street, Littleton MA 01460. 35
36 ========================================================================= 37 The driver was based on the 'lance.c' driver from Donald Becker which is 38 included with the standard driver distribution for linux. Modifications 39 were made to most routines and the hardware recognition routines were 40 written from scratch. Primary references used were: 41
42 1) Lance.c code in /linux/drivers/net/ 43 2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook", 44 AMD, 1992 [(800) 222-9323]. 45 3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)", 46 AMD, Pub. #17881, May 1993. 47 4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA", 48 AMD, Pub. #16907, May 1992 49 5) "DEC EtherWORKS LC Ethernet Controller Owners Manual", 50 Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003 51 6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual", 52 Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003 53 7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR 54 Digital Equipment Corporation, 1989 55 8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual", 56 Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001 57 58 Peter Bauer's depca.c (V0.5) was referred to when debugging this driver. 59 The hash filter code was derived from Reference 3 and has been tested 60 only to the extent that the Table A-1, page A-7, was confirmed to fill 61 the filter bit positions correctly. Hash filtering is not yet 62 implemented in the current driver set. 63
64 The original DEPCA card requires that the ethernet ROM address counter 65 be enabled to count and has an 8 bit NICSR. The ROM counter enabling is 66 only done when a 0x08 is read as the first address octet (to minimise 67 the chances of writing over some other hardware's I/O register). The 68 NICSR accesses have been changed to byte accesses for all the cards 69 supported by this driver, since there is only one useful bit in the MSB 70 (remote boot timeout) and it is not used. Also, there is a maximum of 71 only 48kB network RAM for this card. My thanks to Torbjorn Lindh for 72 help debugging all this (and holding my feet to the fire until I got it 73 right). 74
75 The DE200 series boards have on-board 64kB RAM for use as a shared 76 memory network buffer. Only the DE100 cards make use of a 2kB buffer 77 mode which has not been implemented in this driver (only the 32kB and 78 64kB modes are supported [16kB/48kB for the original DEPCA]). 79
80 At the most only 2 DEPCA cards can be supported on the ISA bus because 81 there is only provision for two I/O base addresses on each card (0x300 82 and 0x200). The I/O address is detected by searching for a byte sequence 83 in the Ethernet station address PROM at the expected I/O address for the 84 Ethernet PROM. The shared memory base address is 'autoprobed' by 85 looking for the self test PROM and detecting the card name. When a 86 second DEPCA is detected, information is placed in the base_addr 87 variable of the next device structure (which is created if necessary), 88 thus enabling ethif_probe initialization for the device. More than 2 89 EISA cards can be supported, but care will be needed assigning the 90 shared memory to ensure that each slot has the correct IRQ, I/O address 91 and shared memory address assigned. 92
93 ************************************************************************ 94
95 NOTE: If you are using two ISA DEPCAs, it is important that you assign 96 the base memory addresses correctly. The driver autoprobes I/O 0x300 97 then 0x200. The base memory address for the first device must be less 98 than that of the second so that the auto probe will correctly assign the 99 I/O and memory addresses on the same card. I can't think of a way to do 100 this unambiguously at the moment, since there is nothing on the cards to 101 tie I/O and memory information together. 102
103 I am unable to test 2 cards together for now, so this code is 104 unchecked. All reports, good or bad, are welcome. 105
106 ************************************************************************ 107
108 The board IRQ setting must be at an unused IRQ which is auto-probed 109 using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are 110 {2,3,4,5,7}, whereas the DE200 is at {5,9,10,11,15}. Note that IRQ2 is 111 really IRQ9 in machines with 16 IRQ lines. 112
113 No 16MB memory limitation should exist with this driver as DMA is not 114 used and the common memory area is in low memory on the network card (my 115 current system has 20MB and I've not had problems yet). 116
117 TO DO: 118 ------ 119
120 1. Implement the 2k buffer mode - does anyone need it?? 121
122 Revision History 123 ---------------- 124
125 Version Date Description 126 127 0.1 25-jan-94 Initial writing. 128 0.2 27-jan-94 Added LANCE TX buffer chaining. 129 0.3 1-feb-94 Added multiple DEPCA support. 130 0.31 4-feb-94 Added DE202 recognition. 131 0.32 19-feb-94 Tidy up. Improve multi-DEPCA support. 132 0.33 25-feb-94 Fix DEPCA ethernet ROM counter enable. 133 Add jabber packet fix from murf@perftech.com 134 and becker@super.org 135 0.34 7-mar-94 Fix DEPCA max network memory RAM & NICSR access. 136 0.35 8-mar-94 Added DE201 recognition. Tidied up. 137 0.351 30-apr-94 Added EISA support. Added DE422 recognition. 138 0.36 16-may-94 DE422 fix released. 139
140 ========================================================================= 141 */ 142
143 staticchar *version = "depca.c:v0.36 5/16/94 davies@wanton.lkg.dec.com\n";
144
145 #include <stdarg.h>
146 #include <linux/config.h>
147 #include <linux/kernel.h>
148 #include <linux/sched.h>
149 #include <linux/string.h>
150 #include <linux/ptrace.h>
151 #include <linux/errno.h>
152 #include <linux/ioport.h>
153 #include <linux/malloc.h>
154 #include <linux/interrupt.h>
155 #include <asm/bitops.h>
156 #include <asm/io.h>
157 #include <asm/dma.h>
158
159 #include <linux/netdevice.h>
160 #include <linux/etherdevice.h>
161 #include <linux/skbuff.h>
162 #include "depca.h"
163
164 #ifdefDEPCA_DEBUG 165 intdepca_debug = DEPCA_DEBUG;
166 #else 167 intdepca_debug = 1;
168 #endif 169
170 #ifndefPROBE_LENGTH 171 #definePROBE_LENGTH 32
172 #endif 173
174 #ifndefPROBE_SEQUENCE 175 #definePROBE_SEQUENCE "FF0055AAFF0055AA"
176 #endif 177
178 #ifndefDEPCA_SIGNATURE 179 #defineDEPCA_SIGNATURE{"DEPCA","DE100",\
180 "DE200","DE201","DE202","DE210",\
181 "DE422",\
182 ""} 183 #defineDEPCA_NAME_LENGTH 8
184 #endif 185
186 #ifndefDEPCA_RAM_BASE_ADDRESSES 187 #defineDEPCA_RAM_BASE_ADDRESSES{0xc0000,0xd0000,0xe0000,0x00000} 188 #endif 189 staticshortmem_chkd = 0; /* holds which base addrs have been */ 190 /* checked, for multi-DEPCA case */ 191
192 #ifndefDEPCA_IO_PORTS 193 #defineDEPCA_IO_PORTS{0x300, 0x200, 0} 194 #endif 195
196 #ifndefDEPCA_TOTAL_SIZE 197 #defineDEPCA_TOTAL_SIZE 0x10
198 #endif 199
200 #ifndefMAX_NUM_DEPCAS 201 #defineMAX_NUM_DEPCAS 2
202 #endif 203
204 #ifndefDEPCA_EISA_IO_PORTS 205 #defineDEPCA_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */ 206 #endif 207
208 #ifndefMAX_EISA_SLOTS 209 #defineMAX_EISA_SLOTS 8
210 #endif 211
212 /* 213 ** Set the number of Tx and Rx buffers. 214 */ 215 #ifndef DEPCA_BUFFER_LOG_SZ
216 #defineRING_SIZE 16 /* 16 buffers */ 217 #else 218 #defineRING_SIZE (1 << (DEPCA_BUFFERS_LOG_SZ))
219 #endif/* DEPCA_BUFFER_LOG_SZ */ 220
221 #definePKT_BUF_SZ 1544 /* Buffer size for each Tx/Rx buffer */ 222 #definePKT_SZ 1514 /* Maximum ethernet packet length */ 223 #defineDAT_SZ 1500 /* Maximum ethernet data length */ 224 #definePKT_HDR_LEN 14 /* Addresses and data length info */ 225
226 #ifdefHAVE_MULTICAST 227 #ifndefCRC_POLYNOMIAL 228 #defineCRC_POLYNOMIAL 0x04c11db7 /* Ethernet CRC polynomial */ 229 #endif/* CRC_POLYNOMIAL */ 230 #endif/* HAVE_MULTICAST */ 231
232 /* 233 ** The DEPCA Rx and Tx ring descriptors. 234 */ 235 structdepca_rx_head{ 236 longbase;
237 shortbuf_length; /* This length is negative 2's complement! */ 238 shortmsg_length; /* This length is "normal". */ 239 };
240
241 structdepca_tx_head{ 242 longbase;
243 shortlength; /* This length is negative 2's complement! */ 244 shortmisc; /* Errors and TDR info */ 245 };
246
247 #defineLA_MASK 0x0000ffff /* LANCE address mask for mapping network RAM 248 to LANCE memory address space */ 249
250 /* 251 ** The Lance initialization block, described in databook, in common memory. 252 */ 253 structdepca_init{ 254 unsignedshortmode; /* Mode register */ 255 unsignedcharphys_addr[ETH_ALEN]; /* Physical ethernet address */ 256 unsignedshortfilter[4]; /* Multicast filter. */ 257 unsignedlongrx_ring; /* Rx ring base pointer & ring length */ 258 unsignedlongtx_ring; /* Tx ring base pointer & ring length */ 259 };
260
261 structdepca_private{ 262 chardevname[8]; /* Not used */ 263 structdepca_rx_head *rx_ring; /* Pointer to start of RX descriptor ring */ 264 structdepca_tx_head *tx_ring; /* Pointer to start of TX descriptor ring */ 265 structdepca_initinit_block;/* Initialization block */ 266 longbus_offset; /* (E)ISA bus address offset vs LANCE */ 267 longdma_buffs; /* Start address of Rx and Tx buffers. */ 268 intcur_rx, cur_tx; /* The next free ring entry */ 269 intdirty_rx, dirty_tx; /* The ring entries to be free()ed. */ 270 intdma;
271 structenet_statisticsstats;
272 char depca_na; /* NICSR access width: 0=>byte, 1=>word */ 273 shortringSize; /* ring size based on available memory */ 274 shortrmask; /* modulus mask based on ring size */ 275 longrlen; /* log2(ringSize) for the descriptors */ 276 };
277
278 /* 279 ** Public Functions 280 */ 281 staticintdepca_open(structdevice *dev);
282 staticintdepca_start_xmit(structsk_buff *skb, structdevice *dev);
283 staticvoiddepca_interrupt(intreg_ptr);
284 staticintdepca_close(structdevice *dev);
285 staticstructenet_statistics *depca_get_stats(structdevice *dev);
286 #ifdefHAVE_MULTICAST 287 staticvoidset_multicast_list(structdevice *dev, intnum_addrs, void *addrs);
288 #endif 289
290 /* 291 ** Private functions 292 */ 293 staticintdepca_probe1(structdevice *dev, shortioaddr);
294 staticvoiddepca_init_ring(structdevice *dev);
295 staticintdepca_rx(structdevice *dev);
296 staticintdepca_tx(structdevice *dev);
297
298 staticvoidLoadCSRs(structdevice *dev);
299 staticintInitRestartDepca(structdevice *dev);
300 staticchar *DepcaSignature(unsignedlongmem_addr);
301 staticintDevicePresent(shortioaddr);
302 #ifdefHAVE_MULTICAST 303 staticvoidSetMulticastFilter(intnum_addrs, char *addrs, char *multicast_table);
304 #endif 305 staticstructdevice *isa_probe(structdevice *dev);
306 staticstructdevice *eisa_probe(structdevice *dev);
307 staticstructdevice *alloc_device(structdevice *dev, intioaddr);
308
309 staticintnum_depcas = 0, num_eth = 0;;
310
311 /* 312 ** Miscellaneous defines... 313 */ 314 #defineSTOP_DEPCA \
315 outw(CSR0, DEPCA_ADDR);\
316 outw(STOP, DEPCA_DATA)
317
318
319
320
321 intdepca_probe(structdevice *dev)
/* */ 322 { 323 intbase_addr = dev->base_addr;
324 intstatus = -ENODEV;
325 structdevice *eth0;
326
327 if (base_addr > 0x1ff) {/* Check a single specified location. */ 328 if (DevicePresent(base_addr) == 0) {/* Is DEPCA really here? */ 329 status = depca_probe1(dev, base_addr);
330 } 331 }elseif (base_addr > 0) {/* Don't probe at all. */ 332 status = -ENXIO;
333 }else{/* First probe for the DEPCA test */ 334 /* pattern in ROM */ 335 eth0=isa_probe(dev);
336 eth0=eisa_probe(eth0);
337 if (dev->priv) status=0;
338 } 339
340 if (status) dev->base_addr = base_addr;
341
342 returnstatus; /* ENODEV would be more accurate. */ 343 } 344
345 staticint 346 depca_probe1(structdevice *dev, shortioaddr)
/* */ 347 { 348 structdepca_private *lp;
349 inti,j, status=0;
350 unsignedlongmem_start, mem_base[] = DEPCA_RAM_BASE_ADDRESSES;
351 char *name=(char *)NULL;
352 unsignedintnicsr, offset, netRAM;
353
354
355 /* 356 ** Stop the DEPCA. Enable the DBR ROM. Disable interrupts and remote boot. 357 */ 358 STOP_DEPCA;
359
360 nicsr = inb(DEPCA_NICSR);
361 nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | IM);
362 outb(nicsr, DEPCA_NICSR);
363
364 if (inw(DEPCA_DATA) == STOP) { 365
366 /* Now find out what kind of DEPCA we have. The DE100 uses a different 367 ** addressing scheme for some registers compared to the DE2xx series. 368 ** Note that a base address location is marked as checked if no DEPCA is 369 ** there or one is found (when the search is immediately terminated). This 370 ** shortens the search time a little for multiple DEPCAs. 371 */ 372
373 for (j = 0, i = 0; mem_base[i] && (j == 0);) { 374 if (((mem_chkd >> i) & 0x01) == 0) {/* has the memory been checked? */ 375 name = DepcaSignature(mem_base[i]);/* check for a DEPCA here */ 376 mem_chkd |= (0x01 << i); /* mark location checked */ 377 if (*name != (char)NULL) {/* one found? */ 378 j = 1; /* set exit flag */ 379 }else{ 380 i++; /* increment search index */ 381 } 382 } 383 } 384
385 if (*name != (char)NULL) {/* found a DEPCA device */ 386 mem_start = mem_base[i];
387 dev->base_addr = ioaddr;
388
389 if ((ioaddr&0x0fff)==DEPCA_EISA_IO_PORTS) {/* EISA slot address */ 390 printk("%s: %s at %#3x (EISA slot %d)",
391 dev->name, name, ioaddr, ((ioaddr>>12)&0x0f));
392 }else{/* ISA port address */ 393 printk("%s: %s at %#3x", dev->name, name, ioaddr);
394 } 395
396 /* There is a 32 byte station address PROM at DEPCA_PROM address. 397 The first six bytes are the station address. They can be read 398 directly since the signature search set up the ROM address 399 counter correctly just before this function. 400
401 For the DE100 we have to be careful about which port is used to 402 read the ROM info. 403 */ 404
405 if (strstr(name,"DE100")!=(char *)NULL) { 406 j = 1;
407 }else{ 408 j = 0;
409 } 410
411 printk(", h/w address ");
412 for (i = 0; i < ETH_ALEN - 1; i++) {/* get the ethernet address */ 413 printk("%2.2x:", dev->dev_addr[i] = inb(DEPCA_PROM + j));
414 } 415 printk("%2.2x", dev->dev_addr[i] = inb(DEPCA_PROM + j));
416
417 for (;i<32;i++) {/* leave ROM counter in known state */ 418 j=inb(DEPCA_PROM);
419 } 420
421 #ifdefHAVE_PORTRESERVE 422 snarf_region(ioaddr, DEPCA_TOTAL_SIZE);
423 #endif 424
425 /* 426 ** Set up the maximum amount of network RAM(kB) 427 */ 428 if (strstr(name,"DEPCA")==(char *)NULL) { 429 netRAM=64;
430 }else{ 431 netRAM=48;
432 } 433
434 /* 435 ** Determine the base address for the DEPCA RAM from the NI-CSR 436 ** and make up a DEPCA-specific-data structure. 437 */ 438
439 if (nicsr & BUF) { 440 offset = 0x8000; /* 32kbyte RAM offset*/ 441 nicsr &= ~BS; /* DEPCA RAM in top 32k */ 442 printk(",\n has %dkB RAM", netRAM - 32);
443 }elseif ((nicsr & _128KB) && (netRAM!=48)) { 444 offset = 0x0000;
445 printk(",\n has 128kB RAM");
446 }else{ 447 offset = 0x0000; /* 64k/48k bytes RAM */ 448 printk(",\n has %dkB RAM", netRAM);
449 } 450
451 mem_start += offset; /* (E)ISA start address */ 452 printk(" at 0x%.5lx", mem_start);
453
454 /* 455 ** Enable the shadow RAM. 456 */ 457 if (strstr(name,"DEPCA")==(char *)NULL) { 458 nicsr |= SHE;
459 outb(nicsr, DEPCA_NICSR);
460 } 461
462 /* 463 ** Calculate the ring size based on the available RAM 464 ** found above. Allocate an equal number of buffers, each 465 ** of size PKT_BUF_SZ (1544 bytes) to the Tx and Rx, allowing one 466 ** descriptor entry (8 bytes) for each buffer. Make sure 467 ** that this ring size is <= RING_SIZE. The ring size must be 468 ** a power of 2. 469 */ 470
471 j = (((netRAM << 10) - offset - sizeof(structdepca_private)) /
472 (PKT_BUF_SZ + 8)) >> 1;
473 for (i=0;j>1;i++) { 474 j >>= 1;
475 } 476
477 /* Hold the ring size information here before the depca 478 ** private structure is allocated. Need this for the memory 479 ** space calculations. 480 */ 481 j = 1 << i;
482
483 /* 484 ** Set up memory information in the device structure. 485 ** Align the descriptor rings on an 8 byte (quadword) boundary. 486 ** 487 ** depca_private area 488 ** rx ring descriptors 489 ** tx ring descriptors 490 ** rx buffers 491 ** tx buffers 492 ** 493 */ 494
495 /* private area & initialise */ 496 dev->priv = (void *)((mem_start + 0x07) & ~0x07);
497 lp = (structdepca_private *)dev->priv;
498 memset(dev->priv, 0, sizeof(structdepca_private));
499
500 /* Tx & Rx descriptors (aligned to a quadword boundary) */ 501 mem_start = ((((unsignedlong)dev->priv +
502 sizeof(structdepca_private)) +
503 (unsignedlong)0x07) & (unsignedlong)~0x07);
504 lp->rx_ring = (structdepca_rx_head *)mem_start;
505
506 mem_start += (sizeof(structdepca_rx_head) * j);
507 lp->tx_ring = (structdepca_tx_head *)mem_start;
508
509 mem_start += (sizeof(structdepca_tx_head) * j);
510 lp->bus_offset = mem_start & 0x00ff0000;
511 mem_start &= LA_MASK; /* LANCE re-mapped start address */ 512
513 lp->dma_buffs = mem_start;
514
515 mem_start += (PKT_BUF_SZ * j);
516 /* (mem_start now points to the start of the Tx buffers) */ 517
518 /* Initialise the data structures wrt CPU */ 519 memset(lp->rx_ring, 0, sizeof(structdepca_rx_head)*j);
520 memset(lp->tx_ring, 0, sizeof(structdepca_tx_head)*j);
521
522 /* This should never happen. */ 523 if ((int)(lp->rx_ring) & 0x07) { 524 printk("\n **ERROR** DEPCA Rx and Tx descriptor rings not on a quadword boundary.\n");
525 return -ENXIO;
526 } 527
528 /* 529 ** Finish initialising the ring information. 530 */ 531 lp->ringSize = j;
532 if (lp->ringSize > RING_SIZE) lp->ringSize = RING_SIZE;
533 lp->rmask = lp->ringSize - 1;
534
535 /* 536 ** calculate the real RLEN size for the descriptors. It is 537 ** log2(ringSize). 538 */ 539 for (i=0, j = lp->ringSize; j>1; i++) { 540 j >>= 1;
541 } 542 lp->rlen = (unsignedlong)(i << 29);
543
544 /* 545 ** load the initialisation block 546 */ 547 depca_init_ring(dev);
548
549 /* 550 ** Initialise the control and status registers 551 */ 552 LoadCSRs(dev);
553
554 /* 555 ** Enable DEPCA board interrupts for autoprobing 556 */ 557 nicsr = ((nicsr & ~IM)|IEN);
558 outb(nicsr, DEPCA_NICSR);
559
560 /* The DMA channel may be passed in on this parameter. */ 561 dev->dma = 0;
562
563 /* To auto-IRQ we enable the initialization-done and DMA err, 564 interrupts. For now we will always get a DMA error. */ 565 if (dev->irq < 2) { 566 autoirq_setup(0);
567
568 /* Trigger an initialization just for the interrupt. */ 569 outw(INEA | INIT, DEPCA_DATA);
570
571 dev->irq = autoirq_report(1);
572 if (dev->irq) { 573 printk(" and uses IRQ%d.\n", dev->irq);
574 }else{ 575 printk(" and failed to detect IRQ line.\n");
576 status = -EAGAIN;
577 } 578 }else{ 579 printk(" and assigned IRQ%d.\n", dev->irq);
580 } 581 }else{ 582 status = -ENXIO;
583 } 584 if (!status) { 585 if (depca_debug > 0) { 586 printk(version);
587 } 588
589 /* The DEPCA-specific entries in the device structure. */ 590 dev->open = &depca_open;
591 dev->hard_start_xmit = &depca_start_xmit;
592 dev->stop = &depca_close;
593 dev->get_stats = &depca_get_stats;
594 #ifdefHAVE_MULTICAST 595 dev->set_multicast_list = &set_multicast_list;
596 #endif 597
598 dev->mem_start = 0;
599
600 /* Fill in the generic field of the device structure. */ 601 ether_setup(dev);
602 } 603 }else{ 604 status = -ENXIO;
605 } 606
607 returnstatus;
608 } 609
610
611 staticint 612 depca_open(structdevice *dev)
/* */ 613 { 614 structdepca_private *lp = (structdepca_private *)dev->priv;
615 inti,nicsr,ioaddr = dev->base_addr;
616
617 if (request_irq(dev->irq, &depca_interrupt)) { 618 printk("depca_open(): Requested IRQ%d is busy\n",dev->irq);
619 return -EAGAIN;
620 } 621
622 irq2dev_map[dev->irq] = dev;
623
624 /* 625 ** Stop the DEPCA & get the board status information. 626 */ 627 STOP_DEPCA;
628 nicsr = inb(DEPCA_NICSR);
629
630 /* 631 ** Re-initialize the DEPCA... 632 */ 633 depca_init_ring(dev); /* initialize the descriptor rings */ 634 LoadCSRs(dev);
635
636 if (depca_debug > 1){ 637 printk("%s: depca open with irq %d\n",dev->name,dev->irq);
638 printk("Descriptor head addresses:\n");
639 printk("\t0x%8.8lx 0x%8.8lx\n",(long)lp->rx_ring,(long)lp->tx_ring);
640 printk("Descriptor addresses:\n");
641 for (i=0;i<lp->ringSize;i++){ 642 printk("\t0x%8.8lx 0x%8.8lx\n",(long)&lp->rx_ring[i].base,
643 (long)&lp->tx_ring[i].base);
644 } 645 printk("Buffer addresses:\n");
646 for (i=0;i<lp->ringSize;i++){ 647 printk("\t0x%8.8lx 0x%8.8lx\n",(long)lp->rx_ring[i].base,
648 (long)lp->tx_ring[i].base);
649 } 650 printk("Initialisation block at 0x%8.8lx\n",(long)&lp->init_block);
651 printk("\tmode: 0x%4.4x\n",lp->init_block.mode);
652 printk("\tphysical address: ");
653 for (i=0;i<6;i++){ 654 printk("%2.2x:",(short)lp->init_block.phys_addr[i]);
655 } 656 printk("\n\tlogical address filter: 0x");
657 for (i=0;i<4;i++){ 658 printk("%2.2x",(short)lp->init_block.filter[i]);
659 } 660 printk("\n\trx_ring at: 0x%8.8lx\n",(long)lp->init_block.rx_ring);
661 printk("\ttx_ring at: 0x%8.8lx\n",(long)lp->init_block.tx_ring);
662 printk("dma_buffs: 0x%8.8lx\n",(long)lp->dma_buffs);
663 printk("Ring size: %d\nMask: 0x%2.2x\nLog2(ringSize): 0x%8.8lx\n",
664 (short)lp->ringSize,
665 (char)lp->rmask,
666 (long)lp->rlen);
667 outw(CSR2,DEPCA_ADDR);
668 printk("CSR2&1: 0x%4.4x",inw(DEPCA_DATA));
669 outw(CSR1,DEPCA_ADDR);
670 printk("%4.4x\n",inw(DEPCA_DATA));
671 outw(CSR3,DEPCA_ADDR);
672 printk("CSR3: 0x%4.4x\n",inw(DEPCA_DATA));
673 } 674
675 /* 676 ** Enable DEPCA board interrupts 677 */ 678 nicsr = ((nicsr & ~IM & ~LED)|SHE|IEN);
679 outb(nicsr, DEPCA_NICSR);
680 outw(CSR0,DEPCA_ADDR);
681
682 dev->tbusy = 0;
683 dev->interrupt = 0;
684 dev->start = 1;
685
686 InitRestartDepca(dev); /* ignore the return status */ 687
688 if (depca_debug > 1){ 689 printk("CSR0: 0x%4.4x\n",inw(DEPCA_DATA));
690 printk("nicsr: 0x%02x\n",inb(DEPCA_NICSR));
691 } 692
693 return 0; /* Always succeed */ 694 } 695
696 /* Initialize the lance Rx and Tx descriptor rings. */ 697 staticvoid 698 depca_init_ring(structdevice *dev)
/* */ 699 { 700 structdepca_private *lp = (structdepca_private *)dev->priv;
701 unsignedlongi;
702
703 lp->init_block.mode = DTX | DRX; /* Disable Rx and Tx. */ 704 lp->cur_rx = lp->cur_tx = 0;
705 lp->dirty_rx = lp->dirty_tx = 0;
706
707 /* Initialize the base addresses and length of each buffer in the ring */ 708 for (i = 0; i < lp->ringSize; i++) { 709 lp->rx_ring[i].base = (lp->dma_buffs + i*PKT_BUF_SZ) | R_OWN;
710 lp->rx_ring[i].buf_length = -PKT_BUF_SZ;
711 lp->tx_ring[i].base = (lp->dma_buffs + (i+lp->ringSize) * PKT_BUF_SZ) &
712 (unsignedlong)(0x00ffffff);
713 } 714
715 /* Set up the initialization block */ 716 for (i = 0; i < ETH_ALEN; i++) { 717 lp->init_block.phys_addr[i] = dev->dev_addr[i];
718 } 719 for (i = 0; i < 4; i++) { 720 lp->init_block.filter[i] = 0x0000;
721 } 722 lp->init_block.rx_ring = ((unsignedlong)lp->rx_ring & LA_MASK) | lp->rlen;
723 lp->init_block.tx_ring = ((unsignedlong)lp->tx_ring & LA_MASK) | lp->rlen;
724
725 lp->init_block.mode = 0x0000; /* Enable the Tx and Rx */ 726 } 727
728 /* 729 ** Writes a socket buffer to TX descriptor ring and starts transmission 730 */ 731 staticint 732 depca_start_xmit(structsk_buff *skb, structdevice *dev)
/* */ 733 { 734 structdepca_private *lp = (structdepca_private *)dev->priv;
735 intioaddr = dev->base_addr;
736 intstatus = 0;
737
738 /* Transmitter timeout, serious problems. */ 739 if (dev->tbusy) { 740 inttickssofar = jiffies - dev->trans_start;
741 if (tickssofar < 10) { 742 status = -1;
743 }else{ 744 printk("%s: transmit timed out, status %04x, resetting.\n",
745 dev->name, inw(DEPCA_DATA));
746
747 STOP_DEPCA;
748 depca_init_ring(dev);
749 LoadCSRs(dev);
750 InitRestartDepca(dev);
751 dev->tbusy=0;
752 dev->trans_start = jiffies;
753 } 754 returnstatus;
755 } 756
757 if (skb == NULL) { 758 dev_tint(dev);
759 return 0;
760 } 761
762 if (skb->len <= 0) { 763 return 0;
764 } 765
766 if (depca_debug > 3) { 767 outw(CSR0, DEPCA_ADDR);
768 printk("%s: depca_start_xmit() called, csr0 %4.4x.\n", dev->name,
769 inw(DEPCA_DATA));
770 } 771
772 /* Block a timer-based transmit from overlapping. This could better be 773 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */ 774 if (set_bit(0, (void*)&dev->tbusy) != 0)
775 printk("%s: Transmitter access conflict.\n", dev->name);
776
777 /* 778 ** The TX buffer, skb, has to be copied into the local network RAM 779 ** for the LANCE to access it. The skb may be at > 16MB for large 780 ** (memory) systems. 781 */ 782 {/* Fill in a Tx ring entry */ 783 unsignedchar *buf;
784 intentry = lp->cur_tx++;
785 intlen;
786 longskbL = skb->len;
787 char *p = (char *) skb->data;
788
789 entry &= lp->rmask; /* Ring around buffer number. */ 790 buf = (unsignedchar *)((lp->tx_ring[entry].base+lp->bus_offset) &
791 0x00ffffff);
792
793 /* Wait for a full ring to free up */ 794 while (lp->tx_ring[entry].base < 0);
795
796 /* 797 ** Caution: the write order is important here... don't set up the 798 ** ownership rights until all the other information is in place. 799 */ 800 len = ((skbL > PKT_SZ) ? PKT_SZ : skbL); /* skb too long */ 801 if (len < ETH_ZLEN) len = ETH_ZLEN; /* len too short */ 802 skbL -= len;
803 lp->tx_ring[entry].length = -len;
804
805 /* Clears various error flags */ 806 lp->tx_ring[entry].misc = 0x0000;
807
808 /* copy the data from the socket buffer to the net memory */ 809 memcpy((unsignedchar *)(buf), skb->data, len);
810
811 /* Hand over buffer ownership to the LANCE */ 812 if (skbL <= 0) lp->tx_ring[entry].base |= (T_ENP);
813 lp->tx_ring[entry].base |= (T_OWN|T_STP);
814
815 /* Trigger an immediate send demand. */ 816 outw(CSR0, DEPCA_ADDR);
817 outw(INEA | TDMD, DEPCA_DATA);
818
819 dev->trans_start = jiffies;
820
821 for (p += len; skbL > 0; p += len) { 822
823 /* Get new buffer pointer */ 824 entry = lp->cur_tx++;
825 entry &= lp->rmask; /* Ring around buffer number. */ 826 buf = (unsignedchar *)((lp->tx_ring[entry].base+lp->bus_offset) &
827 0x00ffffff);
828
829 /* Wait for a full ring to free up */ 830 while (lp->tx_ring[entry].base < 0);
831 dev->tbusy=0;
832
833 /* Copy ethernet header to the new buffer */ 834 memcpy((unsignedchar *)buf, skb->data, PKT_HDR_LEN);
835
836 /* Determine length of data buffer */ 837 len = ((skbL > DAT_SZ) ? DAT_SZ : skbL); /* skbL too long */ 838 if (len < ETH_ZLEN) len = ETH_ZLEN; /* len too short */ 839 skbL -= len;
840 lp->tx_ring[entry].length = -len;
841
842 /* Clears various error flags */ 843 lp->tx_ring[entry].misc = 0x0000;
844
845 /* copy the data from the socket buffer to the net memory */ 846 memcpy((unsignedchar *)(buf + PKT_HDR_LEN), (unsignedchar *)p, len);
847
848 /* Hand over buffer ownership to the LANCE */ 849 if (skbL <= 0) lp->tx_ring[entry].base |= T_ENP;
850 lp->tx_ring[entry].base |= T_OWN;
851 } 852
853 if (depca_debug > 4) { 854 unsignedchar *pkt =
855 (unsignedchar *)((lp->tx_ring[entry].base+lp->bus_offset) &
856 0x00ffffff);
857
858 printk("%s: tx ring[%d], %#lx, sk_buf %#lx len %d.\n",
859 dev->name, entry, (unsignedlong) &lp->tx_ring[entry],
860 lp->tx_ring[entry].base, -lp->tx_ring[entry].length);
861 printk("%s: Tx %2.2x %2.2x %2.2x ... %2.2x %2.2x %2.2x %2.2x...%2.2x len %2.2x %2.2x %2.2x %2.2x.\n",
862 dev->name, pkt[0], pkt[1], pkt[2], pkt[5], pkt[6],
863 pkt[7], pkt[8], pkt[11], pkt[12], pkt[13],
864 pkt[14], pkt[15]);
865 } 866
867 /* Check if the TX ring is full or not - 'tbusy' cleared if not full. */ 868 if (lp->tx_ring[(entry+1) & lp->rmask].base >= 0) { 869 dev->tbusy=0;
870 } 871
872 dev_kfree_skb (skb, FREE_WRITE);
873 } 874
875 return 0;
876 } 877
878 /* 879 ** The DEPCA interrupt handler. 880 */ 881 staticvoid 882 depca_interrupt(intreg_ptr)
/* */ 883 { 884 intirq = -(((structpt_regs *)reg_ptr)->orig_eax+2);
885 structdevice *dev = (structdevice *)(irq2dev_map[irq]);
886 structdepca_private *lp;
887 intcsr0, ioaddr, nicsr;
888
889 if (dev == NULL) { 890 printk ("depca_interrupt(): irq %d for unknown device.\n", irq);
891 }else{ 892 lp = (structdepca_private *)dev->priv;
893 ioaddr = dev->base_addr;
894
895 if (dev->interrupt)
896 printk("%s: Re-entering the interrupt handler.\n", dev->name);
897
898 dev->interrupt = MASK_INTERRUPTS;
899
900 /* mask the DEPCA board interrupts and turn on the LED */ 901 nicsr = inb(DEPCA_NICSR);
902 nicsr |= (IM|LED);
903 outb(nicsr, DEPCA_NICSR);
904
905 outw(CSR0, DEPCA_ADDR);
906 csr0 = inw(DEPCA_DATA);
907
908 /* Acknowledge all of the current interrupt sources ASAP. */ 909 outw(csr0 & ~(INEA|TDMD|STOP|STRT|INIT), DEPCA_DATA);
910
911 if (depca_debug > 5)
912 printk("%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
913 dev->name, csr0, inw(DEPCA_DATA));
914
915 if (csr0 & RINT) /* Rx interrupt (packet arrived) */ 916 depca_rx(dev);
917
918 if (csr0 & TINT) /* Tx interrupt (packet sent) */ 919 depca_tx(dev);
920
921 /* Clear the interrupts we've handled. */ 922 outw(CSR0, DEPCA_ADDR);
923 outw(BABL|CERR|MISS|MERR|RINT|TINT|IDON|INEA, DEPCA_DATA);
924
925 if (depca_debug > 4) { 926 printk("%s: exiting interrupt, csr%d=%#4.4x.\n",
927 dev->name, inw(DEPCA_ADDR),
928 inw(DEPCA_DATA));
929 } 930
931 /* Unmask the DEPCA board interrupts and turn off the LED */ 932 nicsr = (nicsr & ~IM & ~LED);
933 outb(nicsr, DEPCA_NICSR);
934 dev->interrupt = UNMASK_INTERRUPTS;
935 } 936
937 return;
938 } 939
940 staticint 941 depca_rx(structdevice *dev)
/* */ 942 { 943 structdepca_private *lp = (structdepca_private *)dev->priv;
944 intentry = lp->cur_rx & lp->rmask;
945
946 /* If we own the next entry, it's a new packet. Send it up. */ 947 for (; lp->rx_ring[entry].base >= 0; entry = (++lp->cur_rx) & lp->rmask) { 948 intstatus = lp->rx_ring[entry].base >> 16 ;
949 intchained;
950
951 /* 952 ** There is a tricky error noted by John Murphy, <murf@perftech.com> 953 ** to Russ Nelson: even with full-sized buffers, it's possible for a 954 ** jabber packet to use two buffers, with only the last one correctly 955 ** noting the error. 956 */ 957
958 /* Check for a chaining buffer */ 959 chained = 0;
960 if (status == R_STP) { 961 chained = 1;
962
963 /* 964 ** Wait for next buffer to complete to check for errors. This 965 ** is slow but infrequent and allows for correct hardware buffer 966 ** chaining (whilst defeating the chaining's purpose). 967 */ 968 while ((status=(lp->rx_ring[(entry+1)&lp->rmask].base >> 16)) < 0);
969
970 /* NB: 'status' now comes from the buffer following 'entry'. */ 971 } 972
973 if (status & R_ERR) {/* There was an error. */ 974 lp->stats.rx_errors++; /* Update the error stats. */ 975 if (status & R_FRAM) lp->stats.rx_frame_errors++;
976 if (status & R_OFLO) lp->stats.rx_over_errors++;
977 if (status & R_CRC) lp->stats.rx_crc_errors++;
978 if (status & R_BUFF) lp->stats.rx_fifo_errors++;
979 }else{/* Malloc up new buffer, compatible with net-2e. */ 980 shortpkt_len = lp->rx_ring[entry].msg_length;
981 structsk_buff *skb;
982
983 skb = alloc_skb(pkt_len, GFP_ATOMIC);
984 if (skb == NULL) { 985 printk("%s: Memory squeeze, deferring packet.\n", dev->name);
986 lp->stats.rx_dropped++; /* Really, deferred. */ 987 break;
988 } 989 skb->len = pkt_len;
990 skb->dev = dev;
991 memcpy(skb->data,
992 (unsignedchar *)((lp->rx_ring[entry].base+lp->bus_offset) &
993 0x00ffffff),
994 pkt_len);
995 /* 996 ** Notify the upper protocol layers that there is another 997 ** packet to handle 998 */ 999 netif_rx(skb);
1000 lp->stats.rx_packets++;
1001 }1002
1003 /* turn over ownership of the current entry back to the LANCE */1004 lp->rx_ring[entry].base |= R_OWN;
1005 if (chained && (status & R_ERR)) {/* next entry also bad */1006 entry = (++lp->cur_rx) & lp->rmask;
1007 lp->rx_ring[entry].base |= R_OWN;
1008 }1009 }1010
1011 /* 1012 ** We should check that at least two ring entries are free. If not,1013 ** we should free one and mark stats->rx_dropped++. 1014 */1015
1016 return 0;
1017 }1018
1019 /*1020 ** Buffer sent - check for buffer errors.1021 */1022 staticint1023 depca_tx(structdevice *dev)
/* */1024 {1025 structdepca_private *lp = (structdepca_private *)dev->priv;
1026 intdirty_tx = lp->dirty_tx & lp->rmask;
1027
1028 if (depca_debug > 5)
1029 printk("%s: Cleaning tx ring, dirty %d clean %d.\n",
1030 dev->name, dirty_tx, (lp->cur_tx & lp->rmask));
1031
1032 /* 1033 ** While the dirty entry is not the current one AND 1034 ** the LANCE doesn't own it... 1035 */1036 for (; dirty_tx!=(lp->cur_tx & lp->rmask) && lp->tx_ring[dirty_tx].base>0;
1037 dirty_tx = ++lp->dirty_tx & lp->rmask) {1038 unsignedlong *tmdp = (unsignedlong *)(&lp->tx_ring[dirty_tx]);
1039 intstatus = lp->tx_ring[dirty_tx].base >> 16;
1040
1041 if (status < 0) {/* Packet not yet sent! */1042 printk("interrupt for packet not yet sent!\n");
1043 break;
1044 }1045 if (status & T_ERR) {/* There was an major error, log it. */1046 interr_status = lp->tx_ring[dirty_tx].misc;
1047
1048 lp->stats.tx_errors++;
1049 if (err_status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
1050 if (err_status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
1051 if (err_status & TMD3_LCOL) lp->stats.tx_window_errors++;
1052 if (err_status & TMD3_UFLO) lp->stats.tx_fifo_errors++;
1053 /* We should re-init() after the FIFO error. */1054 }elseif (status & (T_MORE | T_ONE)) {1055 lp->stats.collisions++;
1056 }else{1057 lp->stats.tx_packets++;
1058 }1059
1060 if (depca_debug > 5)
1061 printk("%s: Tx done entry %d, %4.4lx %4.4lx %4.4lx %4.4lx.\n",
1062 dev->name, dirty_tx,
1063 tmdp[0], tmdp[1], tmdp[2], tmdp[3]);
1064 }1065 /*mark_bh(INET_BH);*/1066 return 0;
1067 }1068
1069 staticint1070 depca_close(structdevice *dev)
/* */1071 {1072 intioaddr = dev->base_addr;
1073
1074 dev->start = 0;
1075 dev->tbusy = 1;
1076
1077 outw(CSR0, DEPCA_ADDR);
1078
1079 if (depca_debug > 1) {1080 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1081 dev->name, inw(DEPCA_DATA));
1082 }1083
1084 /* 1085 ** We stop the DEPCA here -- it occasionally polls1086 ** memory if we don't. 1087 */1088 outw(STOP, DEPCA_DATA);
1089
1090 free_irq(dev->irq);
1091
1092 irq2dev_map[dev->irq] = 0;
1093
1094 return 0;
1095 }1096
1097 staticvoidLoadCSRs(structdevice *dev)
/* */1098 {1099 structdepca_private *lp = (structdepca_private *)dev->priv;
1100 intioaddr = dev->base_addr;
1101
1102 outw(CSR1, DEPCA_ADDR); /* initialisation block address LSW */1103 outw((unsignedshort)((unsignedlong)(&lp->init_block) & LA_MASK),
1104 DEPCA_DATA);
1105 outw(CSR2, DEPCA_ADDR); /* initialisation block address MSW */1106 outw((unsignedshort)(((unsignedlong)(&lp->init_block) & LA_MASK) >> 16),
1107 DEPCA_DATA);
1108 outw(CSR3, DEPCA_ADDR); /* ALE control */1109 outw(ACON, DEPCA_DATA);
1110 outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */1111 }1112
1113 staticintInitRestartDepca(structdevice *dev)
/* */1114 {1115 structdepca_private *lp = (structdepca_private *)dev->priv;
1116 intioaddr = dev->base_addr;
1117 inti, status=0;
1118
1119 outw(CSR0, DEPCA_ADDR); /* point back to CSR0 */1120 outw(INIT, DEPCA_DATA); /* initialize DEPCA */1121
1122 /* wait for lance to complete initialisation */1123 for (i=0;(i<100) && !(inw(DEPCA_DATA) & IDON); i++);
1124
1125 if (i!=100) {1126 /* clear IDON by writing a "1", enable interrupts and start lance */1127 outw(IDON | INEA | STRT, DEPCA_DATA);
1128 if (depca_debug > 2) {1129 printk("%s: DEPCA open after %d ticks, init block %#lx csr0 %4.4x.\n",
1130 dev->name, i, (long) &lp->init_block, inw(DEPCA_DATA));
1131 }1132 }else{1133 status = -1;
1134 printk("%s: DEPCA unopened after %d ticks, init block %#lx csr0 %4.4x.\n",
1135 dev->name, i, (long) &lp->init_block, inw(DEPCA_DATA));
1136 }1137
1138 returnstatus;
1139 }1140
1141 staticstructenet_statistics *
1142 depca_get_stats(structdevice *dev)
/* */1143 {1144 structdepca_private *lp = (structdepca_private *)dev->priv;
1145
1146 /* Null body since there is no framing error counter */1147
1148 return &lp->stats;
1149 }1150
1151 #ifdefHAVE_MULTICAST1152 /*1153 ** Set or clear the multicast filter for this adaptor.1154 ** num_addrs == -1 Promiscuous mode, receive all packets1155 ** num_addrs == 0 Normal mode, clear multicast list1156 ** num_addrs > 0 Multicast mode, receive normal and MC packets, and do1157 ** best-effort filtering.1158 */1159 staticvoid1160 set_multicast_list(structdevice *dev, intnum_addrs, void *addrs)
/* */1161 {1162 shortioaddr = dev->base_addr;
1163 structdepca_private *lp = (structdepca_private *)dev->priv;
1164
1165 /* We take the simple way out and always enable promiscuous mode. */1166 STOP_DEPCA; /* Temporarily stop the depca. */1167
1168 lp->init_block.mode = PROM; /* Set promiscuous mode */1169 if (num_addrs >= 0) {1170 shortmulticast_table[4];
1171 inti;
1172
1173 SetMulticastFilter(num_addrs, (char *)addrs, (char *)multicast_table);
1174
1175 /* We don't use the multicast table, but rely on upper-layer filtering. */1176 memset(multicast_table, (num_addrs==0) ? 0 : -1, sizeof(multicast_table));
1177
1178 for (i = 0; i < 4; i++) {1179 lp->init_block.filter[i] = multicast_table[i];
1180 }1181 lp->init_block.mode &= ~PROM; /* Unset promiscuous mode */1182 }else{1183 lp->init_block.mode |= PROM; /* Set promiscuous mode */1184 }1185
1186 outw(CSR0, DEPCA_ADDR);
1187 outw(IDON|INEA|STRT, DEPCA_DATA); /* Resume normal operation. */1188 }1189
1190 /*1191 ** Calculate the hash code and update the logical address filter1192 ** from a list of ethernet multicast addresses.1193 ** Derived from a 'C' program in the AMD data book:1194 ** "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)", 1195 ** Pub #17781, Rev. A, May 19931196 */1197 staticvoidSetMulticastFilter(intnum_addrs, char *addrs, char *multicast_table)
/* */1198 {1199 charj, ctrl, bit, octet, hashcode;
1200 shortinti;
1201 longintCRC, poly = (longint) CRC_POLYNOMIAL;
1202
1203 for (i=0;i<num_addrs;i++) {/* for each address in the list */1204 if (((char) *(addrs+ETH_ALEN*i) & 0x01) == 1) {/* is multicast address? */1205 CRC = (longint) 0xffffffff; /* init CRC for each address */1206 for (octet=0;octet<ETH_ALEN;octet++) {/* for each address octet */1207 for(j=0;j<8;j++) {/* process each address bit */1208 bit = (((char)* (addrs+ETH_ALEN*i+octet)) >> j) & 0x01;
1209 ctrl = ((CRC < 0) ? 1 : 0); /* shift the control bit */1210 CRC <<= 1; /* shift the CRC */1211 if (bit ^ ctrl) {/* (bit) XOR (control bit) */1212 CRC ^= poly; /* (CRC) XOR (polynomial) */1213 }1214 }1215 }1216 hashcode = (CRC & 0x00000001); /* hashcode is 6 LSb of CRC ... */1217 for (j=0;j<5;j++) {/* ... in reverse order. */1218 hashcode <<= 1;
1219 CRC >>= 1;
1220 hashcode |= (CRC & 0x00000001);
1221 }1222 octet = hashcode >> 3; /* bit[3-5] -> octet in filter */1223 /* bit[0-2] -> bit in octet */1224 multicast_table[octet] |= (1 << (hashcode & 0x07));
1225 }1226 }1227 return;
1228 }1229
1230 #endif/* HAVE_MULTICAST */1231
1232 /*1233 ** ISA bus I/O device probe1234 */1235 staticstructdevice *isa_probe(dev)
/* */1236 structdevice *dev;
1237 {1238 int *port, ports[] = DEPCA_IO_PORTS;
1239 intstatus;
1240
1241 for (status = -ENODEV, port = &ports[0];
1242 *port && (num_depcas < MAX_NUM_DEPCAS); port++) {1243 intioaddr = *port;
1244
1245 #ifdefHAVE_PORTRESERVE1246 if (check_region(ioaddr, DEPCA_TOTAL_SIZE))
1247 continue;
1248 #endif1249
1250 if (DevicePresent(ioaddr) == 0) {1251 if (num_depcas > 0) {/* only gets here in autoprobe */1252 dev = alloc_device(dev, ioaddr);
1253 }else{1254 if ((status = depca_probe1(dev, ioaddr)) == 0) {1255 num_depcas++;
1256 }1257 }1258 num_eth++;
1259 }1260 }1261 returndev;
1262 }1263
1264 /*1265 ** EISA bus I/O device probe. Probe from slot 1 since slot 0 is usually1266 ** the motherboard.1267 */1268 staticstructdevice *eisa_probe(dev)
/* */1269 structdevice *dev;
1270 {1271 inti, ioaddr = DEPCA_EISA_IO_PORTS;
1272 intstatus;
1273
1274 ioaddr+=0x1000; /* get the first slot address */1275 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, ioaddr+=0x1000) {1276
1277 #ifdefHAVE_PORTRESERVE1278 if (check_region(ioaddr, DEPCA_TOTAL_SIZE))
1279 continue;
1280 #endif1281 if (DevicePresent(ioaddr) == 0) {1282 if (num_depcas > 0) {/* only gets here in autoprobe */1283 dev = alloc_device(dev, ioaddr);
1284 }else{1285 if ((status = depca_probe1(dev, ioaddr)) == 0) {1286 num_depcas++;
1287 }1288 }1289 num_eth++;
1290 }1291 }1292 returndev;
1293 }1294
1295 /*1296 ** Allocate the device by pointing to the next available space in the1297 ** device structure. Should one not be available, it is created.1298 */1299 staticstructdevice *alloc_device(dev, ioaddr)
/* */1300 structdevice *dev;
1301 intioaddr;
1302 {1303 /*1304 ** Check the device structures for an end of list or unused device1305 */1306 while (dev->next != (structdevice *)NULL) {1307 if (dev->next->base_addr == 0xffe0) break;
1308 dev = dev->next; /* walk through eth device list */1309 num_eth++; /* increment eth device number */1310 }1311
1312 /*1313 ** If no more device structures, malloc one up. If memory could1314 ** not be allocated, print an error message.1315 */1316 if (dev->next == (structdevice *)NULL) {1317 dev->next = (structdevice *)kmalloc(sizeof(structdevice) + 8,
1318 GFP_KERNEL);
1319 if (dev->next == (structdevice *)NULL) {1320 printk("eth%d: Device not initialised, insufficient memory\n",
1321 num_eth);
1322 }1323 }1324
1325 /*1326 ** If the memory was allocated, point to the new memory area1327 ** and initialize it (name, I/O address, next device (NULL) and1328 ** initialisation probe routine).1329 */1330 if ((dev->next != (structdevice *)NULL) &&
1331 (num_eth > 0) && (num_eth < 9999)) {1332 dev = dev->next; /* point to the new device */1333 dev->name = (char *)(dev + sizeof(structdevice));
1334 sprintf(dev->name,"eth%d", num_eth);/* New device name */1335 dev->base_addr = ioaddr; /* assign the io address */1336 dev->next = (structdevice *)NULL; /* mark the end of list */1337 dev->init = &depca_probe; /* initialisation routine */1338 num_depcas++;
1339 }1340
1341 returndev;
1342 }1343
1344 /*1345 ** Look for a particular board name in the on-board Remote Diagnostics1346 ** and Boot (RDB) ROM. This will also give us a clue to the network RAM1347 ** base address.1348 */1349 staticchar *DepcaSignature(unsignedlongmem_addr)
/* */1350 {1351 unsignedlongi,j,k;
1352 staticcharsignatures[][DEPCA_NAME_LENGTH] = DEPCA_SIGNATURE;
1353 staticcharthisName[DEPCA_NAME_LENGTH];
1354 chartmpstr[17];
1355
1356 for (i=0;i<16;i++) {/* copy the first 16 bytes of ROM to */1357 tmpstr[i] = *(unsignedchar *)(mem_addr+0xc000+i); /* a temporary string */1358 }1359 tmpstr[i]=(char)NULL;
1360
1361 strcpy(thisName,"");
1362 for (i=0;*signatures[i]!=(char)NULL && *thisName==(char)NULL;i++) {1363 for (j=0,k=0;j<16 && k<strlen(signatures[i]);j++) {1364 if (signatures[i][k] == tmpstr[j]) {/* track signature */1365 k++;
1366 }else{/* lost signature; begin search again */1367 k=0;
1368 }1369 }1370 if (k == strlen(signatures[i])) {1371 strcpy(thisName,signatures[i]);
1372 }1373 }1374
1375 returnthisName; /* return the device name string */1376 }1377
1378 /*1379 ** Look for a special sequence in the Ethernet station address PROM that1380 ** is common across all DEPCA products. Note that the original DEPCA needs1381 ** its ROM address counter to be initialized and enabled. Only enable1382 ** if the first address octet is a 0x08 - this minimises the chances of1383 ** messing around with some other hardware, but it assumes that this DEPCA1384 ** card initialized itself correctly. It also assumes that all past and1385 ** future DEPCA/EtherWORKS cards will have ethernet addresses beginning with1386 ** a 0x08.1387 */1388
1389 staticintDevicePresent(shortioaddr)
/* */1390 {1391 staticshortfp=1,sigLength=0;
1392 staticchardevSig[] = PROBE_SEQUENCE;
1393 chardata;
1394 inti, j, nicsr, status = 0;
1395 staticcharasc2hex(charvalue);
1396
1397 /*1398 ** Initialize the counter on a DEPCA card. Two reads to ensure DEPCA ethernet1399 ** address counter is a) cleared and b) the correct data read.1400 */1401 data = inb(DEPCA_PROM); /* clear counter */1402 data = inb(DEPCA_PROM); /* read data */1403
1404 /*1405 ** Enable counter1406 */1407 if (data == 0x08) {1408 nicsr = inb(DEPCA_NICSR);
1409 nicsr |= AAC;
1410 outb(nicsr, DEPCA_NICSR);
1411 }1412
1413 /* 1414 ** Convert the ascii signature to a hex equivalent & pack in place 1415 */1416 if (fp) {/* only do this once!... */1417 for (i=0,j=0;devSig[i]!=(char)NULL && !status;i+=2,j++) {1418 if ((devSig[i]=asc2hex(devSig[i]))>=0) {1419 devSig[i]<<=4;
1420 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){1421 devSig[j]=devSig[i]+devSig[i+1];
1422 }else{1423 status= -1;
1424 }1425 }else{1426 status= -1;
1427 }1428 }1429 sigLength=j;
1430 fp = 0;
1431 }1432
1433 /* 1434 ** Search the Ethernet address ROM for the signature. Since the ROM address1435 ** counter can start at an arbitrary point, the search must include the entire1436 ** probe sequence length plus the (length_of_the_signature - 1).1437 ** Stop the search IMMEDIATELY after the signature is found so that the1438 ** PROM address counter is correctly positioned at the start of the1439 ** ethernet address for later read out.1440 */1441 if (!status) {1442 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {1443 data = inb(DEPCA_PROM);
1444 if (devSig[j] == data) {/* track signature */1445 j++;
1446 }else{/* lost signature; begin search again */1447 j=0;
1448 }1449 }1450
1451 if (j!=sigLength) {1452 status = -ENODEV; /* search failed */1453 }1454 }1455
1456 returnstatus;
1457 }1458
1459 staticcharasc2hex(charvalue)
/* */1460 {1461 value -= 0x30; /* normalise to 0..9 range */1462 if (value >= 0) {1463 if (value > 9) {/* but may not be 10..15 */1464 value &= 0x1f; /* make A..F & a..f be the same */1465 value -= 0x07; /* normalise to 10..15 range */1466 if ((value < 0x0a) || (value > 0x0f)) {/* if outside range then... */1467 value = -1; /* ...signal error */1468 }1469 }1470 }else{/* outside 0..9 range... */1471 value = -1; /* ...signal error */1472 }1473 returnvalue; /* return hex char or error */1474 }1475
1476
1477 /*1478 * Local variables:1479 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c depca.c"1480 * End:1481 */1482
1483
1484