drivers/net/depca.c

/* */
This source file includes following definitions.
depca_probe
depca_probe1
depca_open
depca_init_ring
depca_start_xmit
depca_interrupt
depca_rx
depca_tx
depca_close
LoadCSRs
InitRestartDepca
depca_get_stats
set_multicast_list
SetMulticastFilter
DepcaSignature
DevicePresent
asc2hex
   1 /*  depca.c: A DIGITAL DEPCA  & EtherWORKS ethernet driver for linux.
   2 
   3     Written 1994 by David C. Davies.
   4 
   5 
   6                       Copyright 1994 David C. Davies
   7                                    and 
   8                          United States Government
   9          (as represented by the Director, National Security Agency).  
  10 
  11 
  12     This software may be used and distributed according to the terms of
  13     the GNU Public License, incorporated herein by reference.
  14 
  15     This driver is written for the Digital Equipment Corporation series
  16     of DEPCA and EtherWORKS ethernet cards:
  17 
  18         DEPCA       (the original)
  19         DE100
  20         DE200 Turbo
  21         DE201 Turbo
  22         DE202 Turbo (TP BNC)
  23         DE210
  24 
  25     The  driver has been tested on DE100, DE200 and DE202 cards  in  a
  26     relatively busy network.
  27 
  28     This driver  will  not work  for the DE203,  DE204  and DE205 series  of
  29     cards, since they have a new custom ASIC in place of the AMD LANCE chip.
  30 
  31     The author may be reached as davies@wanton.lkg.dec.com or
  32     Digital Equipment Corporation, 146 Main Street, Maynard MA 01754.
  33 
  34     =========================================================================
  35     The driver was based on the 'lance.c' driver from Donald Becker which is
  36     included with the standard driver distribution for linux. Modifications
  37     were made to most routines and the hardware recognition routines were
  38     written from scratch. Primary references used were:
  39 
  40     1) Lance.c code in /linux/drivers/net/
  41     2) "Ethernet/IEEE 802.3 Family. 1992 World Network Data Book/Handbook",
  42        AMD, 1992 [(800) 222-9323].
  43     3) "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)",
  44        AMD, Pub. #17881, May 1993.
  45     4) "Am79C960 PCnet-ISA(tm), Single-Chip Ethernet Controller for ISA",
  46        AMD, Pub. #16907, May 1992
  47     5) "DEC EtherWORKS LC Ethernet Controller Owners Manual",
  48        Digital Equipment corporation, 1990, Pub. #EK-DE100-OM.003
  49     6) "DEC EtherWORKS Turbo Ethernet Controller Owners Manual",
  50        Digital Equipment corporation, 1990, Pub. #EK-DE200-OM.003
  51     7) "DEPCA Hardware Reference Manual", Pub. #EK-DEPCA-PR
  52        Digital Equipment Corporation, 1989
  53     8) "DEC EtherWORKS Turbo_(TP BNC) Ethernet Controller Owners Manual",
  54        Digital Equipment corporation, 1991, Pub. #EK-DE202-OM.001
  55     
  56     Peter Bauer's depca.c (V0.5) was referred to when debugging this driver.
  57     The hash filter code was  derived from Reference  3 and has been  tested
  58     only to the extent that the Table  A-1, page A-7,  was confirmed to fill
  59     the   filter bit   positions  correctly.  Hash   filtering  is  not  yet
  60     implemented in the current driver set.
  61 
  62     The original DEPCA  card requires that  the ethernet ROM address counter
  63     be enabled to count and has an 8 bit NICSR.  The ROM counter enabling is
  64     only done when  a 0x08 is read as  the first address octet  (to minimise
  65     the chances of  writing over some other hardware's  I/O  register).  The
  66     size of the NICSR is tested by a word read: if  both bytes are the same,
  67     the register  is 8 bits wide.   Also,  there is a   maximum of only 48kB
  68     network  RAM for   this card.  My   thanks  to Torbjorn Lindh   for help
  69     debugging all this  (and holding  my  feet to the   fire until I got  it
  70     right).
  71 
  72     The DE200  series  boards have  on-board 64kB  RAM for  use  as a shared
  73     memory network  buffer. Only the DE100  cards make use  of a  2kB buffer
  74     mode which has not  been implemented in  this driver (only the 32kB  and
  75     64kB modes are supported [16kB/48kB for the original DEPCA]).
  76 
  77     At the  most only 2 DEPCA  cards can be supported  because there is only
  78     provision for two I/O base addresses on the cards (0x300 and 0x200). The
  79     base  address is  'autoprobed' by  looking  for  the self  test PROM and
  80     detecting the  card name.  The shared memory  base address is decoded by
  81     'autoprobing' the Ethernet PROM address information. The second DEPCA is
  82     detected and information placed  in the base_addr  variable of the  next
  83     device  structure   (which is created    if  necessary),  thus  enabling
  84     ethif_probe initialization for the device.
  85 
  86     ************************************************************************
  87 
  88     NOTE: If you are using two  DEPCAs, it is important  that you assign the
  89     base memory addresses  correctly.  The driver  autoprobes I/O 0x300 then
  90     0x200.  The base memory  address for the  first device must be less than
  91     that of the second so that the auto probe will  correctly assign the I/O
  92     and  memory addresses on  the same card.  I can't  think of  a way to do
  93     this unambiguously at the moment, since there is nothing on the cards to
  94     tie I/O and memory information together.
  95 
  96     I am unable  to  test  2 cards   together for now,    so this  code   is
  97     unchecked. All reports, good or bad, are welcome.
  98 
  99     ************************************************************************
 100 
 101     The board IRQ   setting must be  at an  unused IRQ which  is auto-probed
 102     using Donald Becker's autoprobe routines. DEPCA and DE100 board IRQs are
 103     {2,3,4,5,7}, whereas the  DE200 is at {5,9,10,11,15}.  Note that IRQ2 is
 104     really IRQ9 in machines with 16 IRQ lines.
 105 
 106     No 16MB memory  limitation should exist with this  driver as DMA is  not
 107     used and the common memory area is in low memory on the network card (my
 108     current system has 20MB and I've not had problems yet).
 109 
 110     TO DO:
 111     ------
 112 
 113     1. Implement the 2k buffer mode - does anyone need it??
 114 
 115     Revision History
 116     ----------------
 117 
 118     Version   Date        Description
 119   
 120       0.1   25-jan-94     Initial writing.
 121       0.2   27-jan-94     Added LANCE TX buffer chaining.
 122       0.3    1-feb-94     Added multiple DEPCA support.
 123       0.31   4-feb-94     Added DE202 recognition.
 124       0.32  19-feb-94     Tidy up. Improve multi-DEPCA support.
 125       0.33  25-feb-94     Fix DEPCA ethernet ROM counter enable.
 126                           Add jabber packet fix from murf@perftech.com
 127                           and becker@super.org
 128       0.34   7-mar-94     Fix DEPCA max network memory RAM & NICSR access.
 129       0.35   8-mar-94     Added DE201 recognition.
 130 
 131     =========================================================================
 132 */
 133 
 134 static char *version = "depca.c:v0.35 3/8/94 davies@wanton.lkg.dec.com\n";
 135 
 136 #include <stdarg.h>
 137 #include <linux/config.h>
 138 #include <linux/kernel.h>
 139 #include <linux/sched.h>
 140 #include <linux/string.h>
 141 #include <linux/ptrace.h>
 142 #include <linux/errno.h>
 143 #include <linux/ioport.h>
 144 #include <linux/malloc.h>
 145 #include <linux/interrupt.h>
 146 #include <asm/bitops.h>
 147 #include <asm/io.h>
 148 #include <asm/dma.h>
 149 
 150 #include <linux/netdevice.h>
 151 #include "iow.h"                    /* left in for pl13/14 compatibility... */
 152 #include <linux/etherdevice.h>
 153 #include <linux/skbuff.h>
 154 #include "depca.h"
 155 
 156 #ifdef DEPCA_DEBUG
 157 int depca_debug = DEPCA_DEBUG;
 158 #else
 159 int depca_debug = 1;
 160 #endif
 161 
 162 #ifndef DEPCA_IRQ
 163 /*#define DEPCA_IRQ     {5,9,10,11,15,0}*/
 164 #define DEPCA_IRQ       5
 165 #endif
 166 
 167 #ifndef PROBE_LENGTH
 168 #define PROBE_LENGTH    32
 169 #endif
 170 
 171 #ifndef PROBE_SEQUENCE
 172 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
 173 #endif
 174 
 175 #ifndef DEPCA_SIGNATURE
 176 #define DEPCA_SIGNATURE {"DEPCA","DE100","DE200","DE201","DE202","DE210",""}
 177 #define DEPCA_NAME_LENGTH 8
 178 #endif
 179 
 180 #ifndef DEPCA_RAM_BASE_ADDRESSES
 181 #define DEPCA_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0xe0000,0x00000}
 182 #endif
 183 static short mem_chkd = 0;               /* holds which base addrs have been */
 184                                          /* checked, for multi-DEPCA case */
 185 
 186 #ifndef DEPCA_IO_PORTS
 187 #define DEPCA_IO_PORTS {0x300, 0x200, 0}
 188 #endif
 189 
 190 #ifndef DEPCA_TOTAL_SIZE
 191 #define DEPCA_TOTAL_SIZE 0x10
 192 #endif
 193 
 194 #ifndef MAX_NUM_DEPCAS
 195 #define MAX_NUM_DEPCAS 2
 196 #endif
 197 
 198 /*
 199 ** Set the number of Tx and Rx buffers. 
 200 */
 201 #ifndef DEPCA_BUFFER_LOG_SZ
 202 #define RING_SIZE       16              /* 16 buffers */
 203 #else
 204 #define RING_SIZE       (1 << (DEPCA_BUFFERS_LOG_SZ))
 205 #endif  /* DEPCA_BUFFER_LOG_SZ */
 206 
 207 #define PKT_BUF_SZ      1544            /* Buffer size for each Tx/Rx buffer */
 208 #define PKT_SZ          1514            /* Maximum ethernet packet length */
 209 #define DAT_SZ          1500            /* Maximum ethernet data length */
 210 #define PKT_HDR_LEN     14              /* Addresses and data length info */
 211 
 212 #ifdef HAVE_MULTICAST
 213 #ifndef CRC_POLYNOMIAL
 214 #define CRC_POLYNOMIAL 0x04c11db7       /* Ethernet CRC polynomial */
 215 #endif /* CRC_POLYNOMIAL */
 216 #endif /* HAVE_MULTICAST */
 217 
 218 /*
 219 ** The DEPCA Rx and Tx ring descriptors. 
 220 */
 221 struct depca_rx_head {
 222     long base;
 223     short buf_length;           /* This length is negative 2's complement! */
 224     short msg_length;           /* This length is "normal". */
 225 };
 226 
 227 struct depca_tx_head {
 228     long base;
 229     short length;               /* This length is negative 2's complement! */
 230     short misc;                 /* Errors and TDR info */
 231 };
 232 
 233 struct depca_ring_info {
 234 };
 235 
 236 /*
 237 ** The Lance initialization block, described in databook, in common memory.
 238 */
 239 struct depca_init {
 240     unsigned short mode;        /* Mode register */
 241     unsigned char phys_addr[ETH_ALEN];  /* Physical ethernet address */
 242     unsigned short filter[4];   /* Multicast filter. */
 243     unsigned long rx_ring;      /* Rx ring base pointer & ring length */
 244     unsigned long tx_ring;      /* Tx ring base pointer & ring length */
 245 };
 246 
 247 struct depca_private {
 248     char devname[8];            /* Not used */
 249     struct depca_rx_head *rx_ring; /* Pointer to start of RX descriptor ring */
 250     struct depca_tx_head *tx_ring; /* Pointer to start of TX descriptor ring */
 251     struct depca_init   init_block;/* Initialization block */
 252     long dma_buffs;             /* Start address of Rx and Tx buffers. */
 253     int cur_rx, cur_tx;         /* The next free ring entry */
 254     int dirty_rx, dirty_tx;     /* The ring entries to be free()ed. */
 255     int dma;
 256     struct enet_statistics stats;
 257     char depca_na;              /* NICSR access width: 0=>byte, 1=>word */
 258     short ringSize;             /* ring size based on available memory */
 259     short rmask;                /* modulus mask based on ring size */
 260     long rlen;                  /* log2(ringSize) for the descriptors */
 261 };
 262 
 263 /*
 264 ** Public Functions
 265 */
 266 static int depca_open(struct device *dev);
 267 static int depca_start_xmit(struct sk_buff *skb, struct device *dev);
 268 static void depca_interrupt(int reg_ptr);
 269 static int depca_close(struct device *dev);
 270 static struct enet_statistics *depca_get_stats(struct device *dev);
 271 #ifdef HAVE_MULTICAST
 272 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
 273 #endif
 274 
 275 /*
 276 ** Private functions
 277 */
 278 static int depca_probe1(struct device *dev, short ioaddr);
 279 static void depca_init_ring(struct device *dev);
 280 static int depca_rx(struct device *dev);
 281 static int depca_tx(struct device *dev);
 282 
 283 static void LoadCSRs(struct device *dev);
 284 static int InitRestartDepca(struct device *dev);
 285 static char *DepcaSignature(unsigned long mem_addr);
 286 static int DevicePresent(short ioaddr);
 287 #ifdef HAVE_MULTICAST
 288 static void SetMulticastFilter(int num_addrs, char *addrs, char *multicast_table);
 289 #endif
 290 
 291 static int depca_na;
 292 static int num_depcas = 0, num_eth = 0;;
 293 
 294 /*
 295 ** Miscellaneous defines...
 296 */
 297 #define STOP_DEPCA \
 298     outw(CSR0, DEPCA_ADDR);\
 299     outw(STOP, DEPCA_DATA)
 300 
 301 #define GET_NICSR(a,b) \
 302     if (depca_na) { \
 303       (a) = inw((b)); \
 304     } else { \
 305       (a) = inb((b)); \
 306     }
 307 
 308 #define PUT_NICSR(a,b) \
 309     if (depca_na) { \
 310       outw((a), (b)); \
 311     } else { \
 312       outb((a), (b)); \
 313     }
 314 
 315 
 316 
 317 
 318 int depca_probe(struct device *dev)
     /*  */
 319 {
 320     int *port, ports[] = DEPCA_IO_PORTS;
 321     int base_addr = dev->base_addr;
 322     int status;
 323     struct device *eth0 = (struct device *) NULL;
 324 
 325     if (base_addr > 0x1ff) {          /* Check a single specified location. */
 326       status = -ENODEV;
 327       if (DevicePresent(base_addr) == 0) { /* Is DEPCA really here? */
 328         status = depca_probe1(dev, base_addr);
 329       }
 330     } else if (base_addr > 0) {       /* Don't probe at all. */
 331                 status = -ENXIO;
 332     } else {                          /* First probe for the DEPCA test */
 333                                       /* pattern in ROM */
 334 
 335       for (status = -ENODEV, port = &ports[0]; 
 336                             *port && (num_depcas < MAX_NUM_DEPCAS); port++) {
 337         int ioaddr = *port;
 338 
 339 #ifdef HAVE_PORTRESERVE
 340         if (check_region(ioaddr, DEPCA_TOTAL_SIZE))
 341             continue;
 342 #endif
 343         if (DevicePresent(ioaddr) == 0) {
 344           if (num_depcas > 0) {        /* only gets here in autoprobe */
 345 
 346             /*
 347             ** Check the device structures for an end of list or unused device
 348             */
 349             while (dev->next != (struct device *)NULL) {
 350               if (dev->next->base_addr == 0xffe0) break;
 351               dev = dev->next;         /* walk through eth device list */
 352               num_eth++;               /* increment eth device number */
 353             }
 354 
 355             /*
 356             ** If no more device structures, malloc one up. If memory could
 357             ** not be allocated, print an error message.
 358             ** 
 359             */
 360             if (dev->next == (struct device *)NULL) {
 361               dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
 362                                                                   GFP_KERNEL);
 363             } else {
 364               printk("eth%d: Device not initialised, insufficient memory\n",
 365                                                                       num_eth);
 366             }
 367 
 368             /*
 369             ** If the memory was allocated, point to the new memory area
 370             ** and initialize it (name, I/O address, next device (NULL) and
 371             ** initialisation probe routine).
 372             */
 373             if ((dev->next != (struct device *)NULL) &&
 374                 (num_eth > 0) && (num_eth < 9999)) {
 375               dev = dev->next;         /* point to the new device */
 376               dev->name = (char *)(dev + sizeof(struct device));
 377               sprintf(dev->name,"eth%d", num_eth); /* New device name */
 378               dev->base_addr = ioaddr; /* assign the io address */
 379               dev->next = (struct device *)NULL; /* mark the end of list */
 380               dev->init = &depca_probe;/* initialisation routine */
 381             }
 382           } else {
 383             eth0 = dev;                /* remember the first device */
 384             status = depca_probe1(dev, ioaddr);
 385           }
 386           num_depcas++;
 387           num_eth++;
 388         }
 389       }
 390       if (eth0) dev = eth0;             /* restore the first device */
 391     }
 392 
 393     if (status) dev->base_addr = base_addr;
 394 
 395     return status;                      /* ENODEV would be more accurate. */
 396 }
 397 
 398 static int
 399 depca_probe1(struct device *dev, short ioaddr)
     /*  */
 400 {
 401     struct depca_private *lp;
 402     int i,j, status=0;
 403     unsigned long mem_start, mem_base[] = DEPCA_RAM_BASE_ADDRESSES;
 404     char *name=(char *)NULL;
 405     unsigned int nicsr, offset, netRAM;
 406 
 407 
 408     /*
 409     ** Stop the DEPCA. Enable the DBR ROM and the ethernet ROM address counter
 410     ** (for the really old DEPCAs). Disable interrupts and remote boot.
 411     */
 412     STOP_DEPCA;
 413 
 414     GET_NICSR(nicsr, DEPCA_NICSR);
 415     nicsr = ((nicsr & ~SHE & ~RBE & ~IEN) | AAC | IM);
 416     PUT_NICSR(nicsr, DEPCA_NICSR);
 417 
 418     if (inw(DEPCA_DATA) == STOP) {
 419 
 420     /* Now find out what kind of DEPCA we have. The DE100 uses a different
 421     ** addressing scheme for some registers compared to the DE2xx series.
 422     ** Note that a base address location is marked as checked if no DEPCA is
 423     ** there or one is found (when the search is immediately terminated). This
 424     ** shortens the search time a little for multiple DEPCAs.
 425     */
 426 
 427       for (j = 0, i = 0; mem_base[i] && (j == 0);) {
 428         if (((mem_chkd >> i) & 0x01) == 0) { /* has the memory been checked? */
 429           name = DepcaSignature(mem_base[i]);/* check for a DEPCA here */
 430           mem_chkd |= (0x01 << i);           /* mark location checked */
 431           if (*name != (char)NULL) {         /* one found? */
 432             j = 1;                           /* set exit flag */
 433           } else {
 434             i++;                             /* increment search index */
 435           }
 436         }
 437       }
 438 
 439       if (*name != (char)NULL) {          /* found a DEPCA device */
 440         mem_start = mem_base[i];
 441         dev->base_addr = ioaddr;
 442 
 443         printk("%s: DEPCA at %#3x is a %s, ", dev->name, ioaddr, name);
 444 
 445       /* There is a 32 byte station address PROM at DEPCA_PROM address.
 446          The first six bytes are the station address. They can be read
 447          directly since the signature search set up the ROM address 
 448          counter correctly just before this function.
 449 
 450          For the DE100 we have to be careful about which port is used to
 451          read the ROM info.
 452       */
 453 
 454         if (strstr(name,"DE100")!=(char *)NULL) {
 455           j = 1;
 456         } else {
 457           j = 0;
 458         }
 459 
 460         printk("ethernet address ");
 461         for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet address */
 462           printk("%2.2x:", dev->dev_addr[i] = inb(DEPCA_PROM + j));
 463         }
 464         printk("%2.2x", dev->dev_addr[i] = inb(DEPCA_PROM + j));
 465 
 466         for (;i<32;i++) {                /* leave ROM counter in known state */
 467           j=inb(DEPCA_PROM);
 468         }
 469 
 470 #ifdef HAVE_PORTRESERVE
 471         snarf_region(ioaddr, DEPCA_TOTAL_SIZE);
 472 #endif
 473 
 474         /*
 475         ** Set up the maximum amount of network RAM(kB)
 476         */
 477         if (strstr(name,"DEPCA")==(char *)NULL) {
 478           netRAM=64;
 479         } else {
 480           netRAM=48;
 481         }
 482 
 483         /* 
 484          ** Determine the base address for the DEPCA RAM from the NI-CSR
 485          ** and make up a DEPCA-specific-data structure. 
 486         */
 487 
 488         if (nicsr & BUF) {
 489           offset = 0x8000;              /* 32kbyte RAM offset*/
 490           nicsr &= ~BS;                 /* DEPCA RAM in top 32k */
 491           printk(",\n      with %dkB RAM", netRAM-(offset >> 10));
 492         } else {
 493           offset = 0x0000;              /* 64k/48k bytes RAM */
 494           printk(",\n      with %dkB RAM", netRAM);
 495         }
 496 
 497         mem_start += offset;
 498         printk(" starting at 0x%.5lx", mem_start);
 499 
 500         /*
 501          ** Enable the shadow RAM.
 502         */
 503         nicsr |= SHE;
 504         PUT_NICSR(nicsr, DEPCA_NICSR);
 505  
 506         /*
 507         ** Calculate the ring size based on the available RAM
 508         ** found above. Allocate an equal number of buffers, each
 509         ** of size PKT_BUF_SZ (1544 bytes) to the Tx and Rx, allowing one
 510         ** descriptor entry (8 bytes) for each buffer. Make sure
 511         ** that this ring size is <= RING_SIZE. The ring size must be
 512         ** a power of 2.
 513         */
 514 
 515         j = (((netRAM << 10) - offset - sizeof(struct depca_private)) / 
 516                                                        (PKT_BUF_SZ + 8)) >> 1;
 517         for (i=0;j>1;i++) {
 518           j >>= 1;
 519         }
 520 
 521         /* Hold the ring size information here before the depca
 522         ** private structure is allocated. Need this for the memory
 523         ** space calculations.
 524         */
 525         j = 1 << i;
 526 
 527         /*
 528         ** Set up memory information in the device structure.
 529         ** Align the descriptor rings on an 8 byte (quadword) boundary.
 530         **
 531         **     depca_private area
 532         **     rx ring descriptors
 533         **     tx ring descriptors
 534         **     rx buffers
 535         **     tx buffers
 536         **
 537         */
 538 
 539         /* private area & initialise */
 540         dev->priv = (void *)((mem_start + 0x07) & ~0x07);      
 541         lp = (struct depca_private *)dev->priv;
 542         memset(dev->priv, 0, sizeof(struct depca_private));
 543 
 544         /* Tx & Rx descriptors (aligned to a quadword boundary) */
 545         mem_start = ((((unsigned long)dev->priv + 
 546                         sizeof(struct depca_private)) +
 547                         (unsigned long)0x07) & (unsigned long)~0x07);
 548         lp->rx_ring = (struct depca_rx_head *)mem_start;
 549 
 550         mem_start += (sizeof(struct depca_rx_head) * j);
 551         lp->tx_ring = (struct depca_tx_head *)mem_start;
 552 
 553         mem_start += (sizeof(struct depca_tx_head) * j);
 554         lp->dma_buffs = mem_start & 0x00ffffff;
 555 
 556         mem_start += (PKT_BUF_SZ * j);
 557         /* (mem_start now points to the start of the Tx buffers) */
 558 
 559         /* Initialise the data structures */
 560         memset(lp->rx_ring, 0, sizeof(struct depca_rx_head)*j);
 561         memset(lp->tx_ring, 0, sizeof(struct depca_tx_head)*j);
 562 
 563         /* This should never happen. */
 564         if ((int)(lp->rx_ring) & 0x07) {
 565           printk("\n **ERROR** DEPCA Rx and Tx descriptor rings not on a quadword boundary.\n");
 566           return -ENXIO;
 567         }
 568 
 569         /*
 570         ** Finish initialising the ring information.
 571         */
 572         lp->ringSize = j;
 573         if (lp->ringSize > RING_SIZE) lp->ringSize = RING_SIZE;
 574         lp->rmask = lp->ringSize - 1;
 575 
 576         /*
 577         ** calculate the real RLEN size for the descriptors. It is
 578         ** log2(ringSize).
 579         */
 580         for (i=0, j = lp->ringSize; j>1; i++) {
 581           j >>= 1;
 582         }
 583         lp->rlen = (unsigned long)(i << 29);
 584 
 585         /*
 586         ** load the initialisation block
 587         */
 588         depca_init_ring(dev);
 589 
 590         /*
 591         ** Initialise the control and status registers
 592         */
 593         LoadCSRs(dev);
 594 
 595         /*
 596         ** Store the NICSR width for this DEPCA
 597         */
 598         lp->depca_na = depca_na;
 599 
 600         /*
 601         ** Enable DEPCA board interrupts for autoprobing
 602         */
 603         nicsr = ((nicsr & ~IM)|IEN);
 604         PUT_NICSR(nicsr, DEPCA_NICSR);
 605 
 606         /* The DMA channel may be passed in on this parameter. */
 607         dev->dma = 0;
 608         
 609         /* To auto-IRQ we enable the initialization-done and DMA err,
 610          interrupts. For now we will always get a DMA error. */
 611         if (dev->irq < 2) {
 612           autoirq_setup(0);
 613 
 614           /* Trigger an initialization just for the interrupt. */
 615           outw(INEA | INIT, DEPCA_DATA);
 616           
 617           dev->irq = autoirq_report(1);
 618           if (dev->irq) {
 619             printk(" and probed IRQ%d.\n", dev->irq);
 620           } else {
 621             printk(". Failed to detect IRQ line.\n");
 622             status = -EAGAIN;
 623           }
 624         } else {
 625           printk(". Assigned IRQ%d.\n", dev->irq);
 626         }
 627       } else {
 628         status = -ENXIO;
 629       }
 630       if (!status) {
 631         if (depca_debug > 0) {
 632           printk(version);
 633         }
 634 
 635         /* The DEPCA-specific entries in the device structure. */
 636         dev->open = &depca_open;
 637         dev->hard_start_xmit = &depca_start_xmit;
 638         dev->stop = &depca_close;
 639         dev->get_stats = &depca_get_stats;
 640 #ifdef HAVE_MULTICAST
 641         dev->set_multicast_list = &set_multicast_list;
 642 #endif
 643 
 644         dev->mem_start = 0;
 645         
 646         /* Fill in the generic field of the device structure. */
 647         for (i = 0; i < DEV_NUMBUFFS; i++) {
 648           dev->buffs[i] = NULL;
 649         }
 650 
 651         dev->hard_header     = eth_header;
 652         dev->add_arp         = eth_add_arp;
 653         dev->queue_xmit      = dev_queue_xmit;
 654         dev->rebuild_header  = eth_rebuild_header;
 655         dev->type_trans      = eth_type_trans;
 656         
 657         dev->type            = ARPHRD_ETHER;
 658         dev->hard_header_len = ETH_HLEN;
 659         dev->mtu             = 1500; /* eth_mtu */
 660         dev->addr_len        = ETH_ALEN;
 661 
 662         for (i = 0; i < dev->addr_len; i++) {
 663           dev->broadcast[i]=0xff;
 664         }
 665         
 666         /* New-style flags. */
 667         dev->flags           = IFF_BROADCAST;
 668         dev->family          = AF_INET;
 669         dev->pa_addr         = 0;
 670         dev->pa_brdaddr      = 0;
 671         dev->pa_mask         = 0;
 672         dev->pa_alen         = sizeof(unsigned long);
 673       }
 674     } else {
 675       status = -ENXIO;
 676     }
 677 
 678     return status;
 679 }
 680 
 681 
 682 static int
 683 depca_open(struct device *dev)
     /*  */
 684 {
 685     struct depca_private *lp = (struct depca_private *)dev->priv;
 686     int i,nicsr,ioaddr = dev->base_addr;
 687 
 688     if (request_irq(dev->irq, &depca_interrupt)) {
 689         printk("depca_open(): Requested IRQ%d is busy\n",dev->irq);
 690         return -EAGAIN;
 691     }
 692 
 693     irq2dev_map[dev->irq] = dev;
 694 
 695     /*
 696     ** Stop the DEPCA & get the board status information.  
 697     */
 698     depca_na=lp->depca_na;
 699     STOP_DEPCA;
 700     GET_NICSR(nicsr, DEPCA_NICSR);
 701 
 702     /* 
 703     ** Re-initialize the DEPCA... 
 704     */
 705     depca_init_ring(dev);                 /* initialize the descriptor rings */
 706     LoadCSRs(dev);
 707 
 708     if (depca_debug > 1){
 709       printk("%s: depca open with irq %d\n",dev->name,dev->irq);
 710       printk("Descriptor head addresses:\n");
 711       printk("\t0x%8.8lx  0x%8.8lx\n",(long)lp->rx_ring,(long)lp->tx_ring);
 712       printk("Descriptor addresses:\n");
 713       for (i=0;i<lp->ringSize;i++){
 714         printk("\t0x%8.8lx  0x%8.8lx\n",(long)&lp->rx_ring[i].base,
 715                                         (long)&lp->tx_ring[i].base);
 716       }
 717       printk("Buffer addresses:\n");
 718       for (i=0;i<lp->ringSize;i++){
 719         printk("\t0x%8.8lx  0x%8.8lx\n",(long)lp->rx_ring[i].base,
 720                                         (long)lp->tx_ring[i].base);
 721       }
 722       printk("Initialisation block at 0x%8.8lx\n",(long)&lp->init_block);
 723       printk("\tmode: 0x%4.4x\n",lp->init_block.mode);
 724       printk("\tphysical address: ");
 725       for (i=0;i<6;i++){
 726         printk("%2.2x:",(short)lp->init_block.phys_addr[i]);
 727       }
 728       printk("\n\tlogical address filter: 0x");
 729       for (i=0;i<4;i++){
 730         printk("%2.2x",(short)lp->init_block.filter[i]);
 731       }
 732       printk("\n\trx_ring at: 0x%8.8lx\n",(long)lp->init_block.rx_ring);
 733       printk("\ttx_ring at: 0x%8.8lx\n",(long)lp->init_block.tx_ring);
 734       printk("dma_buffs: 0x%8.8lx\n",(long)lp->dma_buffs);
 735       printk("Ring size: %d\nMask: 0x%2.2x\nLog2(ringSize): 0x%8.8lx\n", 
 736                                          (short)lp->ringSize, 
 737                                           (char)lp->rmask,
 738                                           (long)lp->rlen);
 739       outw(CSR2,DEPCA_ADDR);
 740       printk("CSR2&1: 0x%4.4x",inw(DEPCA_DATA));
 741       outw(CSR1,DEPCA_ADDR);
 742       printk("%4.4x\n",inw(DEPCA_DATA));
 743       outw(CSR3,DEPCA_ADDR);
 744       printk("CSR3: 0x%4.4x\n",inw(DEPCA_DATA));
 745     }
 746 
 747     /*
 748     ** Enable DEPCA board interrupts
 749     */
 750     nicsr = ((nicsr & ~IM & ~LED)|SHE|IEN);
 751     PUT_NICSR(nicsr, DEPCA_NICSR);
 752     outw(CSR0,DEPCA_ADDR);
 753 
 754     dev->tbusy = 0;                         
 755     dev->interrupt = 0;
 756     dev->start = 1;
 757 
 758     InitRestartDepca(dev);                /* ignore the return status */
 759 
 760     if (depca_debug > 1){
 761       printk("CSR0: 0x%4.4x\n",inw(DEPCA_DATA));
 762       GET_NICSR(nicsr, DEPCA_NICSR);
 763       printk("nicsr: 0x%4.4x\n",nicsr);
 764     }
 765 
 766     return 0;                             /* Always succeed */
 767 }
 768 
 769 /* Initialize the lance Rx and Tx descriptor rings. */
 770 static void
 771 depca_init_ring(struct device *dev)
     /*  */
 772 {
 773     struct depca_private *lp = (struct depca_private *)dev->priv;
 774     unsigned long i;
 775 
 776     lp->init_block.mode = DTX | DRX;         /* Disable Rx and Tx. */
 777     lp->cur_rx = lp->cur_tx = 0;
 778     lp->dirty_rx = lp->dirty_tx = 0;
 779 
 780     /* Initialize the base addresses and length of each buffer in the ring */
 781     for (i = 0; i < lp->ringSize; i++) {
 782         lp->rx_ring[i].base = (lp->dma_buffs + i*PKT_BUF_SZ) | R_OWN;
 783         lp->rx_ring[i].buf_length = -PKT_BUF_SZ;
 784         lp->tx_ring[i].base = (lp->dma_buffs + (i+lp->ringSize) * PKT_BUF_SZ) &
 785                                                    (unsigned long)(0x00ffffff);
 786     }
 787 
 788     /* Set up the initialization block */
 789     for (i = 0; i < ETH_ALEN; i++) {
 790       lp->init_block.phys_addr[i] = dev->dev_addr[i];
 791     }
 792     for (i = 0; i < 4; i++) {
 793       lp->init_block.filter[i] = 0x0000;
 794     }
 795     lp->init_block.rx_ring = (unsigned long)lp->rx_ring | lp->rlen;
 796     lp->init_block.tx_ring = (unsigned long)lp->tx_ring | lp->rlen;
 797 
 798     lp->init_block.mode = 0x0000;            /* Enable the Tx and Rx */ 
 799 }
 800 
 801 /* 
 802 ** Writes a socket buffer to TX descriptor ring and starts transmission 
 803 */
 804 static int
 805 depca_start_xmit(struct sk_buff *skb, struct device *dev)
     /*  */
 806 {
 807     struct depca_private *lp = (struct depca_private *)dev->priv;
 808     int ioaddr = dev->base_addr;
 809     int status = 0;
 810 
 811     /* Transmitter timeout, serious problems. */
 812     if (dev->tbusy) {
 813       int tickssofar = jiffies - dev->trans_start;
 814       if (tickssofar < 10) {
 815         status = -1;
 816       } else {
 817         STOP_DEPCA;
 818         printk("%s: transmit timed out, status %4.4x, resetting.\n",
 819                dev->name, inw(DEPCA_DATA));
 820         
 821         depca_init_ring(dev);
 822         LoadCSRs(dev);
 823         InitRestartDepca(dev);
 824         dev->tbusy=0;
 825         dev->trans_start = jiffies;
 826       }
 827       return status;
 828     }
 829 
 830     if (skb == NULL) {
 831         dev_tint(dev);
 832         return 0;
 833     }
 834 
 835     /* Fill in the ethernet header. */
 836     if (!skb->arp  &&  dev->rebuild_header(skb->data, dev)) {
 837         skb->dev = dev;
 838         arp_queue (skb);
 839         return 0;
 840     }
 841     skb->arp=1;
 842 
 843     if (skb->len <= 0) {
 844       return 0;
 845     }
 846 
 847     if (depca_debug > 3) {
 848         outw(CSR0, DEPCA_ADDR);
 849         printk("%s: depca_start_xmit() called, csr0 %4.4x.\n", dev->name,
 850                inw(DEPCA_DATA));
 851     }
 852 
 853     /* Block a timer-based transmit from overlapping.  This could better be
 854        done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
 855     if (set_bit(0, (void*)&dev->tbusy) != 0)
 856         printk("%s: Transmitter access conflict.\n", dev->name);
 857 
 858     /*
 859     ** The TX buffer, skb, has to be copied into the local network RAM
 860     ** for the LANCE to access it. The skb may be at > 16MB for large 
 861     ** (memory) systems.
 862     */
 863     {                           /* Fill in a Tx ring entry */
 864       unsigned char *buf;
 865       int entry = lp->cur_tx++;
 866       int len;
 867       long skbL = skb->len;
 868       char *p = (char *) skb->data;
 869 
 870       entry &= lp->rmask;                   /* Ring around buffer number. */
 871       buf = (unsigned char *)(lp->tx_ring[entry].base & 0x00ffffff);
 872 
 873       /* Wait for a full ring to free up */
 874       while (lp->tx_ring[entry].base < 0);
 875 
 876       /* 
 877       ** Caution: the write order is important here... don't set up the
 878       ** ownership rights until all the other information is in place.
 879       */
 880       len = ((skbL > PKT_SZ) ? PKT_SZ : skbL); /* skb too long */
 881       if (len < ETH_ZLEN) len = ETH_ZLEN;      /* len too short */
 882       skbL -= len;
 883       lp->tx_ring[entry].length = -len;
 884 
 885       /* Clears various error flags */
 886       lp->tx_ring[entry].misc = 0x0000;
 887 
 888       /* copy the data from the socket buffer to the net memory */
 889       memcpy((unsigned char *)(buf), skb->data, len);
 890 
 891       /* Hand over buffer ownership to the LANCE */
 892       if (skbL <= 0) lp->tx_ring[entry].base |= (T_ENP);
 893       lp->tx_ring[entry].base |= (T_OWN|T_STP);
 894 
 895       /* Trigger an immediate send demand. */
 896       outw(CSR0, DEPCA_ADDR);
 897       outw(INEA | TDMD, DEPCA_DATA);
 898 
 899       dev->trans_start = jiffies;
 900 
 901       for (p += len; skbL > 0; p += len) {
 902 
 903         /* Get new buffer pointer */
 904         entry = lp->cur_tx++;
 905         entry &= lp->rmask;                 /* Ring around buffer number. */
 906         buf = (unsigned char *)(lp->tx_ring[entry].base & 0x00ffffff);
 907 
 908         /* Wait for a full ring to free up */
 909         while (lp->tx_ring[entry].base < 0);
 910         dev->tbusy=0;
 911 
 912         /* Copy ethernet header to the new buffer */
 913         memcpy((unsigned char *)buf, skb->data, PKT_HDR_LEN);
 914 
 915         /* Determine length of data buffer */
 916         len = ((skbL > DAT_SZ) ? DAT_SZ : skbL); /* skbL too long */
 917         if (len < ETH_ZLEN) len = ETH_ZLEN;      /* len too short */
 918         skbL -= len;
 919         lp->tx_ring[entry].length = -len;
 920 
 921         /* Clears various error flags */
 922         lp->tx_ring[entry].misc = 0x0000;
 923 
 924         /* copy the data from the socket buffer to the net memory */
 925         memcpy((unsigned char *)(buf + PKT_HDR_LEN), (unsigned char *)p, len);
 926 
 927         /* Hand over buffer ownership to the LANCE */
 928         if (skbL <= 0) lp->tx_ring[entry].base |= T_ENP;
 929         lp->tx_ring[entry].base |= T_OWN;
 930       }
 931 
 932       if (depca_debug > 4) {
 933         unsigned char *pkt =
 934           (unsigned char *)(lp->tx_ring[entry].base & 0x00ffffff);
 935 
 936         printk("%s: tx ring[%d], %#lx, sk_buf %#lx len %d.\n",
 937                dev->name, entry, (unsigned long) &lp->tx_ring[entry],
 938                lp->tx_ring[entry].base, -lp->tx_ring[entry].length);
 939         printk("%s:  Tx %2.2x %2.2x %2.2x ... %2.2x  %2.2x %2.2x %2.2x...%2.2x len %2.2x %2.2x  %2.2x %2.2x.\n",
 940                dev->name, pkt[0], pkt[1], pkt[2], pkt[5], pkt[6],
 941                pkt[7], pkt[8], pkt[11], pkt[12], pkt[13],
 942                pkt[14], pkt[15]);
 943       }
 944       
 945       /* Check if the TX ring is full or not - 'tbusy' cleared if not full. */
 946       if (lp->tx_ring[(entry+1) & lp->rmask].base >= 0) {
 947         dev->tbusy=0;
 948       }
 949 
 950       if (skb->free) {
 951         kfree_skb (skb, FREE_WRITE);
 952       }
 953     }
 954 
 955     return 0;
 956 }
 957 
 958 /*
 959 ** The DEPCA interrupt handler. 
 960 */
 961 static void
 962 depca_interrupt(int reg_ptr)
     /*  */
 963 {
 964     int irq = -(((struct pt_regs *)reg_ptr)->orig_eax+2);
 965     struct device *dev = (struct device *)(irq2dev_map[irq]);
 966     struct depca_private *lp;
 967     int csr0, ioaddr, nicsr;
 968 
 969     if (dev == NULL) {
 970         printk ("depca_interrupt(): irq %d for unknown device.\n", irq);
 971         return;
 972     } else {
 973       lp = (struct depca_private *)dev->priv;
 974       ioaddr = dev->base_addr;
 975       depca_na = lp->depca_na;
 976     }
 977 
 978     if (dev->interrupt)
 979         printk("%s: Re-entering the interrupt handler.\n", dev->name);
 980 
 981     dev->interrupt = MASK_INTERRUPTS;
 982 
 983     /* mask the DEPCA board interrupts and turn on the LED */
 984     GET_NICSR(nicsr, DEPCA_NICSR);
 985     nicsr |= (IM|LED);
 986     PUT_NICSR(nicsr, DEPCA_NICSR);
 987 
 988     outw(CSR0, DEPCA_ADDR);
 989     csr0 = inw(DEPCA_DATA);
 990 
 991     /* Acknowledge all of the current interrupt sources ASAP. */
 992     outw(csr0 & ~(INEA|TDMD|STOP|STRT|INIT), DEPCA_DATA);
 993 
 994     if (depca_debug > 5)
 995         printk("%s: interrupt  csr0=%#2.2x new csr=%#2.2x.\n",
 996                dev->name, csr0, inw(DEPCA_DATA));
 997 
 998     if (csr0 & RINT)            /* Rx interrupt (packet arrived) */
 999         depca_rx(dev);
1000 
1001     if (csr0 & TINT)            /* Tx interrupt (packet sent) */
1002         depca_tx(dev);
1003 
1004     /* Clear the interrupts we've handled. */
1005     outw(CSR0, DEPCA_ADDR);
1006     outw(BABL|CERR|MISS|MERR|RINT|TINT|IDON|INEA, DEPCA_DATA);
1007 
1008     if (depca_debug > 4) {
1009       printk("%s: exiting interrupt, csr%d=%#4.4x.\n",
1010              dev->name, inw(DEPCA_ADDR),
1011              inw(DEPCA_DATA));
1012     }
1013 
1014     /* Unmask the DEPCA board interrupts and turn off the LED */
1015     nicsr = (nicsr & ~IM & ~LED);
1016     PUT_NICSR(nicsr, DEPCA_NICSR);
1017 
1018     dev->interrupt = UNMASK_INTERRUPTS;
1019     return;
1020 }
1021 
1022 static int
1023 depca_rx(struct device *dev)
     /*  */
1024 {
1025     struct depca_private *lp = (struct depca_private *)dev->priv;
1026     int entry = lp->cur_rx & lp->rmask;
1027 
1028     /* If we own the next entry, it's a new packet. Send it up. */
1029     for (; lp->rx_ring[entry].base >= 0; entry = (++lp->cur_rx) & lp->rmask) {
1030         int status = lp->rx_ring[entry].base >> 16 ;
1031         int chained;
1032 
1033         /*
1034         ** There is a tricky error noted by John Murphy, <murf@perftech.com>
1035         ** to Russ Nelson: even with full-sized buffers, it's possible for a
1036         ** jabber packet to use two buffers, with only the last one correctly
1037         ** noting the error.
1038         */
1039 
1040         /* Check for a chaining buffer */
1041         chained = 0;
1042         if (status == R_STP) { 
1043           chained = 1;
1044 
1045           /* 
1046           ** Wait for next buffer to complete to check for errors. This
1047           ** is slow but infrequent and allows for correct hardware buffer
1048           ** chaining (whilst defeating the chaining's purpose).
1049           */
1050           while ((status=(lp->rx_ring[(entry+1)&lp->rmask].base >> 16)) < 0);
1051 
1052           /* NB: 'status' now comes from the buffer following 'entry'. */
1053         }
1054           
1055         if (status & R_ERR) {                  /* There was an error. */
1056             lp->stats.rx_errors++;             /* Update the error stats. */
1057             if (status & R_FRAM) lp->stats.rx_frame_errors++;
1058             if (status & R_OFLO) lp->stats.rx_over_errors++;
1059             if (status & R_CRC)  lp->stats.rx_crc_errors++;
1060             if (status & R_BUFF) lp->stats.rx_fifo_errors++;
1061         } else {          /* Malloc up new buffer, compatible  with net-2e. */
1062             short pkt_len = lp->rx_ring[entry].msg_length;
1063             struct sk_buff *skb;
1064 
1065             skb = alloc_skb(pkt_len, GFP_ATOMIC);
1066             if (skb == NULL) {
1067                 printk("%s: Memory squeeze, deferring packet.\n", dev->name);
1068                 lp->stats.rx_dropped++; /* Really, deferred. */
1069                 break;
1070             }
1071             skb->len = pkt_len;
1072             skb->dev = dev;
1073             memcpy(skb->data,
1074                    (unsigned char *)(lp->rx_ring[entry].base & 0x00ffffff),
1075                    pkt_len);
1076             /* 
1077             ** Notify the upper protocol layers that there is another 
1078             ** packet to handle
1079             */
1080             netif_rx(skb);
1081             lp->stats.rx_packets++;
1082         }
1083 
1084         /* turn over ownership of the current entry back to the LANCE */
1085         lp->rx_ring[entry].base |= R_OWN;
1086         if (chained && (status & R_ERR)) {          /* next entry also bad */
1087           entry = (++lp->cur_rx) & lp->rmask;
1088           lp->rx_ring[entry].base |= R_OWN;
1089         }
1090     }
1091 
1092     /* 
1093     ** We should check that at least two ring entries are free.  If not,
1094     ** we should free one and mark stats->rx_dropped++. 
1095     */
1096 
1097     return 0;
1098 }
1099 
1100 /*
1101 ** Buffer sent - check for buffer errors.
1102 */
1103 static int
1104 depca_tx(struct device *dev)
     /*  */
1105 {
1106   struct depca_private *lp = (struct depca_private *)dev->priv;
1107   int dirty_tx = lp->dirty_tx & lp->rmask;
1108 
1109   if (depca_debug > 5)
1110     printk("%s: Cleaning tx ring, dirty %d clean %d.\n",
1111            dev->name, dirty_tx, (lp->cur_tx & lp->rmask));
1112   
1113   /* 
1114   ** While the dirty entry is not the current one AND 
1115   ** the LANCE doesn't own it... 
1116   */
1117   for (; dirty_tx!=(lp->cur_tx & lp->rmask) && lp->tx_ring[dirty_tx].base>0;
1118                                        dirty_tx = ++lp->dirty_tx & lp->rmask) {
1119     unsigned long *tmdp = (unsigned long *)(&lp->tx_ring[dirty_tx]);
1120     int status = lp->tx_ring[dirty_tx].base >> 16;
1121 
1122     if (status < 0) {                          /* Packet not yet sent! */
1123       printk("interrupt for packet not yet sent!\n");
1124       break;
1125     }
1126     if (status & T_ERR) { /* There was an major error, log it. */
1127       int err_status = lp->tx_ring[dirty_tx].misc;
1128 
1129       lp->stats.tx_errors++;
1130       if (err_status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
1131       if (err_status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
1132       if (err_status & TMD3_LCOL) lp->stats.tx_window_errors++;
1133       if (err_status & TMD3_UFLO) lp->stats.tx_fifo_errors++;
1134       /* We should re-init() after the FIFO error. */
1135     } else if (status & (T_MORE | T_ONE)) {
1136       lp->stats.collisions++;
1137     } else {
1138       lp->stats.tx_packets++;
1139     }
1140 
1141     if (depca_debug > 5)
1142       printk("%s: Tx done entry %d, %4.4lx %4.4lx %4.4lx %4.4lx.\n",
1143              dev->name, dirty_tx,
1144              tmdp[0], tmdp[1], tmdp[2], tmdp[3]);
1145   }
1146   /*mark_bh(INET_BH);*/
1147   return 0;
1148 }
1149 
1150 static int
1151 depca_close(struct device *dev)
     /*  */
1152 {
1153     int ioaddr = dev->base_addr;
1154 
1155     dev->start = 0;
1156     dev->tbusy = 1;
1157 
1158     outw(CSR0, DEPCA_ADDR);
1159 
1160     if (depca_debug > 1) {
1161       printk("%s: Shutting down ethercard, status was %2.2x.\n",
1162              dev->name, inw(DEPCA_DATA));
1163     }
1164 
1165     /* 
1166     ** We stop the DEPCA here -- it occasionally polls
1167     ** memory if we don't. 
1168     */
1169     outw(STOP, DEPCA_DATA);
1170 
1171     free_irq(dev->irq);
1172 
1173     irq2dev_map[dev->irq] = 0;
1174 
1175     return 0;
1176 }
1177 
1178 static void LoadCSRs(struct device *dev)
     /*  */
1179 {
1180   struct depca_private *lp = (struct depca_private *)dev->priv;
1181   int ioaddr = dev->base_addr;
1182 
1183   outw(CSR1, DEPCA_ADDR);                /* initialisation block address LSW */
1184   outw((unsigned short)(unsigned long)&lp->init_block, DEPCA_DATA);
1185   outw(CSR2, DEPCA_ADDR);                /* initialisation block address MSW */
1186   outw((unsigned short)((unsigned long)&lp->init_block >> 16), DEPCA_DATA);
1187   outw(CSR3, DEPCA_ADDR);                /* ALE control */
1188   outw(ACON, DEPCA_DATA);
1189   outw(CSR0, DEPCA_ADDR);                /* point back to CSR0 */
1190 }
1191 
1192 static int InitRestartDepca(struct device *dev)
     /*  */
1193 {
1194   struct depca_private *lp = (struct depca_private *)dev->priv;
1195   int ioaddr = dev->base_addr;
1196   int i, status=0;
1197 
1198   outw(CSR0, DEPCA_ADDR);                /* point back to CSR0 */
1199   outw(INIT, DEPCA_DATA);                /* initialize DEPCA */
1200 
1201   /* wait for lance to complete initialisation */
1202   for (i=0;(i<100) && !(inw(DEPCA_DATA) & IDON); i++); 
1203 
1204   if (i!=100) {
1205     /* clear IDON by writing a "1", enable interrupts and start lance */
1206     outw(IDON | INEA | STRT, DEPCA_DATA);
1207     if (depca_debug > 2) {
1208       printk("%s: DEPCA open after %d ticks, init block %#lx csr0 %4.4x.\n",
1209              dev->name, i, (long) &lp->init_block, inw(DEPCA_DATA));
1210     }
1211   } else {
1212     status = -1;
1213     printk("%s: DEPCA unopened after %d ticks, init block %#lx csr0 %4.4x.\n",
1214            dev->name, i, (long) &lp->init_block, inw(DEPCA_DATA));
1215   }
1216 
1217   return status;
1218 }
1219 
1220 static struct enet_statistics *
1221 depca_get_stats(struct device *dev)
     /*  */
1222 {
1223     struct depca_private *lp = (struct depca_private *)dev->priv;
1224 
1225     /* Null body since there is no framing error counter */
1226 
1227     return &lp->stats;
1228 }
1229 
1230 #ifdef HAVE_MULTICAST
1231 /*
1232 ** Set or clear the multicast filter for this adaptor.
1233 ** num_addrs == -1      Promiscuous mode, receive all packets
1234 ** num_addrs == 0       Normal mode, clear multicast list
1235 ** num_addrs > 0        Multicast mode, receive normal and MC packets, and do
1236 **                      best-effort filtering.
1237 */
1238 static void
1239 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
     /*  */
1240 {
1241   short ioaddr = dev->base_addr;
1242   struct depca_private *lp = (struct depca_private *)dev->priv;
1243   
1244   /* We take the simple way out and always enable promiscuous mode. */
1245   STOP_DEPCA;                       /* Temporarily stop the depca.  */
1246 
1247   lp->init_block.mode = PROM;       /* Set promiscuous mode */
1248   if (num_addrs >= 0) {
1249     short multicast_table[4];
1250     int i;
1251 
1252     SetMulticastFilter(num_addrs, (char *)addrs, (char *)multicast_table);
1253 
1254     /* We don't use the multicast table, but rely on upper-layer filtering. */
1255     memset(multicast_table, (num_addrs==0) ? 0 : -1, sizeof(multicast_table));
1256 
1257     for (i = 0; i < 4; i++) {
1258       lp->init_block.filter[i] = multicast_table[i];
1259     }
1260     lp->init_block.mode &= ~PROM; /* Unset promiscuous mode */
1261   } else {
1262     lp->init_block.mode |= PROM;    /* Set promiscuous mode */
1263   }
1264 
1265   outw(CSR0, DEPCA_ADDR);
1266   outw(IDON|INEA|STRT, DEPCA_DATA); /* Resume normal operation. */
1267 }
1268 
1269 /*
1270 ** Calculate the hash code and update the logical address filter
1271 ** from a list of ethernet multicast addresses.
1272 ** Derived from a 'C' program in the AMD data book:
1273 ** "Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE)", 
1274 ** Pub #17781, Rev. A, May 1993
1275 */
1276 static void SetMulticastFilter(int num_addrs, char *addrs, char *multicast_table)
     /*  */
1277 {
1278   char j, ctrl, bit, octet, hashcode;
1279   short int i;
1280   long int CRC, poly = (long int) CRC_POLYNOMIAL;
1281 
1282   for (i=0;i<num_addrs;i++) {                /* for each address in the list */
1283     if (((char) *(addrs+ETH_ALEN*i) & 0x01) == 1) {/* is multicast address? */ 
1284       CRC = (long int) 0xffffffff;           /* init CRC for each address */
1285       for (octet=0;octet<ETH_ALEN;octet++) { /* for each address octet */
1286         for(j=0;j<8;j++) {                   /* process each address bit */
1287           bit = (((char)* (addrs+ETH_ALEN*i+octet)) >> j) & 0x01;
1288           ctrl = ((CRC < 0) ? 1 : 0);        /* shift the control bit */
1289           CRC <<= 1;                         /* shift the CRC */
1290           if (bit ^ ctrl) {                  /* (bit) XOR (control bit) */
1291             CRC ^= poly;                     /* (CRC) XOR (polynomial) */
1292           }
1293         }
1294       }
1295       hashcode = (CRC & 0x00000001);         /* hashcode is 6 LSb of CRC ... */
1296       for (j=0;j<5;j++) {                    /* ... in reverse order. */
1297         hashcode <<= 1;
1298         CRC >>= 1;
1299         hashcode |= (CRC & 0x00000001);
1300       }                                      
1301       octet = hashcode >> 3;                  /* bit[3-5] -> octet in filter */
1302                                               /* bit[0-2] -> bit in octet */
1303       multicast_table[octet] |= (1 << (hashcode & 0x07));
1304     }
1305   }
1306   return;
1307 }
1308 
1309 #endif  /* HAVE_MULTICAST */
1310 
1311 /*
1312 ** Look for a particular board name in the on-board Remote Diagnostics
1313 ** and Boot (RDB) ROM. This will also give us a clue to the network RAM
1314 ** base address.
1315 */
1316 static char *DepcaSignature(unsigned long mem_addr)
     /*  */
1317 {
1318   unsigned long i,j,k;
1319   static char signatures[][DEPCA_NAME_LENGTH] = DEPCA_SIGNATURE;
1320   static char thisName[DEPCA_NAME_LENGTH];
1321   char tmpstr[17];
1322 
1323   for (i=0;i<16;i++) {                  /* copy the first 16 bytes of ROM to */
1324     tmpstr[i] = *(unsigned char *)(mem_addr+0xc000+i); /* a temporary string */
1325   }
1326   tmpstr[i]=(char)NULL;
1327 
1328   strcpy(thisName,"");
1329   for (i=0;*signatures[i]!=(char)NULL && *thisName==(char)NULL;i++) {
1330     for (j=0,k=0;j<16 && k<strlen(signatures[i]);j++) {
1331       if (signatures[i][k] == tmpstr[j]) {              /* track signature */
1332         k++;
1333       } else {                     /* lost signature; begin search again */
1334         k=0;
1335       }
1336     }
1337     if (k == strlen(signatures[i])) {
1338       strcpy(thisName,signatures[i]);
1339     }
1340   }
1341 
1342   return thisName;                    /* return the device name string */
1343 }
1344 
1345 /*
1346 ** Look for a special sequence in the Ethernet station address PROM that
1347 ** is common across all DEPCA products. Note that the original DEPCA needs
1348 ** its ROM address counter to be initialized and enabled. Only enable
1349 ** if the first address octet is a 0x08 - this minimises the chances of
1350 ** messing around with some other hardware, but it assumes that this DEPCA
1351 ** card initialized itself correctly. It also assumes that all past and
1352 ** future DEPCA/EtherWORKS cards will have ethernet addresses beginning with
1353 ** a 0x08. The choice of byte or word addressing is made here based on whether
1354 ** word read of the NICSR returns two identical lower and upper bytes: if so
1355 ** the register is 8 bits wide.
1356 */
1357 
1358 static int DevicePresent(short ioaddr)
     /*  */
1359 {
1360   static short fp=1,sigLength=0;
1361   static char devSig[] = PROBE_SEQUENCE;
1362   char data;
1363   unsigned char LSB,MSB;
1364   int i, j, nicsr, status = 0;
1365   static char asc2hex(char value);
1366 
1367 /*
1368 ** Initialize the counter on a DEPCA card. Two reads to ensure DEPCA ethernet
1369 ** address counter is a) cleared and b) the correct data read.
1370 */
1371   data = inb(DEPCA_PROM);                /* clear counter */
1372   data = inb(DEPCA_PROM);                /* read data */
1373 
1374 /*
1375 ** Determine whether a byte or word access should be made on the NICSR.
1376 ** Since the I/O 'functions' are actually in-line code, the choice not to use
1377 ** pointers to functions vs. just set a conditional, is made for us. This code
1378 ** assumes that the NICSR has an asymmetric bit pattern already in it.
1379 */
1380   nicsr = inw(DEPCA_NICSR);
1381   LSB = nicsr & 0xff;
1382   MSB = (((unsigned) nicsr) >> 8) & 0xff;
1383   if (MSB == LSB) {
1384     depca_na = 0;        /* byte accesses */
1385   } else {
1386     depca_na = 1;        /* word accesses */
1387   }
1388 
1389 /*
1390 ** Enable counter
1391 */
1392   if (data == 0x08) {
1393     nicsr |= AAC;
1394     PUT_NICSR(nicsr, DEPCA_NICSR);
1395   }
1396   
1397 /* 
1398 ** Convert the ascii signature to a hex equivalent & pack in place 
1399 */
1400   if (fp) {                               /* only do this once!... */
1401     for (i=0,j=0;devSig[i]!=(char)NULL && !status;i+=2,j++) {
1402       if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1403         devSig[i]<<=4;
1404         if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1405           devSig[j]=devSig[i]+devSig[i+1];
1406         } else {
1407           status= -1;
1408         }
1409       } else {
1410         status= -1;
1411       }
1412     }
1413     sigLength=j;
1414     fp = 0;
1415   }
1416 
1417 /* 
1418 ** Search the Ethernet address ROM for the signature. Since the ROM address
1419 ** counter can start at an arbitrary point, the search must include the entire
1420 ** probe sequence length plus the length of the (signature - 1).
1421 ** Stop the search IMMEDIATELY after the signature is found so that the
1422 ** PROM address counter is correctly positioned at the start of the
1423 ** ethernet address for later read out.
1424 */
1425   if (!status) {
1426     for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1427       data = inb(DEPCA_PROM);
1428       if (devSig[j] == data) {    /* track signature */
1429         j++;
1430       } else {                    /* lost signature; begin search again */
1431         j=0;
1432       }
1433     }
1434 
1435     if (j!=sigLength) {
1436       status = -ENODEV;           /* search failed */
1437     }
1438   }
1439 
1440   return status;
1441 }
1442 
1443 static char asc2hex(char value)
     /*  */
1444 {
1445   value -= 0x30;                  /* normalise to 0..9 range */
1446   if (value >= 0) {
1447     if (value > 9) {              /* but may not be 10..15 */
1448       value &= 0x1f;              /* make A..F & a..f be the same */
1449       value -= 0x07;              /* normalise to 10..15 range */
1450       if ((value < 0x0a) || (value > 0x0f)) { /* if outside range then... */
1451         value = -1;               /* ...signal error */
1452       }
1453     }
1454   } else {                        /* outside 0..9 range... */
1455     value = -1;                   /* ...signal error */
1456   }
1457   return value;                   /* return hex char or error */
1458 }
1459 
1460 
1461 /*
1462  * Local variables:
1463  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c depca.c"
1464  * End:
1465  */
1466 
1467 
1468
/* */
root/drivers/net/depca.c

DEFINITIONS
