This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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125 static char *version = "ewrk3.c:v0.30 11/1/94 davies@wanton.lkg.dec.com\n";
126
127 #include <stdarg.h>
128 #include <linux/config.h>
129 #include <linux/kernel.h>
130 #include <linux/sched.h>
131 #include <linux/string.h>
132 #include <linux/ptrace.h>
133 #include <linux/errno.h>
134 #include <linux/ioport.h>
135 #include <linux/malloc.h>
136 #include <linux/interrupt.h>
137 #include <asm/bitops.h>
138 #include <asm/io.h>
139 #include <asm/dma.h>
140 #include <asm/segment.h>
141
142 #include <linux/netdevice.h>
143 #include <linux/etherdevice.h>
144 #include <linux/skbuff.h>
145
146 #include <linux/time.h>
147 #include <linux/types.h>
148 #include <linux/unistd.h>
149
150 #ifdef MODULE
151 #include <linux/module.h>
152 #include "/linux/tools/version.h"
153 #endif
154
155 #include "ewrk3.h"
156
157 #ifdef EWRK3_DEBUG
158 static int ewrk3_debug = EWRK3_DEBUG;
159 #else
160 static int ewrk3_debug = 1;
161 #endif
162
163 #ifndef PROBE_LENGTH
164 #define PROBE_LENGTH 32
165 #endif
166
167 #ifndef PROBE_SEQUENCE
168 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
169 #endif
170
171 #ifndef EWRK3_SIGNATURE
172 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
173 #define EWRK3_NAME_LENGTH 8
174 #endif
175
176 #ifndef EWRK3_RAM_BASE_ADDRESSES
177 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
178 #endif
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194 #define EWRK3_IO_BASE 0x100
195 #define EWRK3_IOP_INC 0x20
196 #define EWRK3_IO_SEARCH 0x007dff7f
197 static long mem_chkd = EWRK3_IO_SEARCH;
198
199
200 #ifndef MAX_NUM_EWRK3S
201 #define MAX_NUM_EWRK3S 21
202 #endif
203
204 #ifndef EWRK3_EISA_IO_PORTS
205 #define EWRK3_EISA_IO_PORTS 0x0c00
206 #endif
207
208 #ifndef MAX_EISA_SLOTS
209 #define MAX_EISA_SLOTS 8
210 #define EISA_SLOT_INC 0x1000
211 #endif
212
213 #ifndef CRC_POLYNOMIAL
214 #define CRC_POLYNOMIAL 0x04c11db7
215 #endif
216
217
218
219
220 #define IO_ONLY 0x00
221 #define SHMEM_2K 0x800
222 #define SHMEM_32K 0x8000
223 #define SHMEM_64K 0x10000
224
225
226
227
228 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
229
230 #define ENABLE_IRQs \
231 icr |= irq_mask;\
232 outb(icr, EWRK3_ICR)
233
234 #define DISABLE_IRQs \
235 icr = inb(EWRK3_ICR);\
236 icr &= ~irq_mask;\
237 outb(icr, EWRK3_ICR)
238
239
240
241
242 #define START_EWRK3 \
243 csr = inb(EWRK3_CSR);\
244 csr &= ~(TXD|RXD);\
245 outb(csr, EWRK3_CSR)
246
247 #define STOP_EWRK3 \
248 csr = (TXD|RXD);\
249 outb(csr, EWRK3_CSR)
250
251
252
253
254 #define EWRK3_PKT_STAT_SZ 16
255 #define EWRK3_PKT_BIN_SZ 128
256
257
258 struct ewrk3_private {
259 long shmem_base;
260 long shmem_length;
261 struct enet_statistics stats;
262 struct {
263 unsigned long bins[EWRK3_PKT_STAT_SZ];
264 unsigned long unicast;
265 unsigned long multicast;
266 unsigned long broadcast;
267 unsigned long excessive_collisions;
268 unsigned long tx_underruns;
269 unsigned long excessive_underruns;
270 } pktStats;
271 short mPage;
272 unsigned char lemac;
273 unsigned char hard_strapped;
274 unsigned char lock;
275 unsigned char txc;
276 };
277
278
279
280
281 #define FORCE_2K_MODE \
282 shmem_length = SHMEM_2K;\
283 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
284
285
286
287
288 static int ewrk3_open(struct device *dev);
289 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
290 static void ewrk3_interrupt(int reg_ptr);
291 static int ewrk3_close(struct device *dev);
292 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
293 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
294 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq);
295
296
297
298
299 static int ewrk3_hw_init(struct device *dev, short iobase);
300 static void ewrk3_init(struct device *dev);
301 static int ewrk3_rx(struct device *dev);
302 static int ewrk3_tx(struct device *dev);
303
304 static void EthwrkSignature(char * name, char *eeprom_image);
305 static int DevicePresent(short iobase);
306 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
307
308 static int Read_EEPROM(short iobase, unsigned char eaddr);
309 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
310 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
311
312 #ifndef MODULE
313 static struct device *isa_probe(struct device *dev);
314 static struct device *eisa_probe(struct device *dev);
315 static struct device *alloc_device(struct device *dev, int iobase);
316
317 static int num_ewrk3s = 0, num_eth = 0, autoprobed = 0;
318 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
319
320 #else
321 int init_module(void);
322 void cleanup_module(void);
323
324 #endif
325
326
327
328
329 #define INIT_EWRK3 {\
330 int i;\
331 outb(EEPROM_INIT, EWRK3_IOPR);\
332 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
333 }
334
335
336
337
338 int ewrk3_probe(struct device *dev)
339 {
340 int base_addr = dev->base_addr;
341 int status = -ENODEV;
342 #ifndef MODULE
343 struct device *eth0;
344 #endif
345
346 if (base_addr > 0x0ff) {
347 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==0) {
348 if (DevicePresent(base_addr) == 0) {
349 status = ewrk3_hw_init(dev, base_addr);
350 } else {
351 printk("ewrk3_probe(): No device found\n");
352 }
353 } else {
354 status = ewrk3_hw_init(dev, base_addr);
355 }
356 } else if (base_addr > 0) {
357 status = -ENXIO;
358
359 #ifdef MODULE
360 } else {
361 printk("Autoprobing is not supported when loading a module based driver.\n");
362 status = -EIO;
363 #else
364 } else if (!autoprobed) {
365
366 eth0=isa_probe(dev);
367 eth0=eisa_probe(eth0);
368 if (dev->priv) status=0;
369 autoprobed = 1;
370 } else {
371 status = -ENXIO;
372 #endif
373
374 }
375
376 if (status) dev->base_addr = base_addr;
377
378 return status;
379 }
380
381 static int
382 ewrk3_hw_init(struct device *dev, short iobase)
383 {
384 struct ewrk3_private *lp;
385 int i, status=0;
386 unsigned long mem_start, shmem_length;
387 char name[EWRK3_NAME_LENGTH + 1];
388 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
389 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
390
391
392
393
394
395 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
396 INIT_EWRK3;
397
398 nicsr = inb(EWRK3_CSR);
399
400
401
402
403 DISABLE_IRQs;
404
405 if (nicsr == TXD|RXD) {
406
407
408
409
410 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
411 union {
412 short val;
413 char c[2];
414 } tmp;
415
416 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
417 eeprom_image[i] = tmp.c[0];
418 eeprom_image[i+1] = tmp.c[1];
419
420 chksum += eeprom_image[i] + eeprom_image[i+1];
421 }
422
423 if (chksum != 0) {
424 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
425 status = -ENXIO;
426 } else {
427
428
429
430 EthwrkSignature(name, eeprom_image);
431
432 if (*name != '\0') {
433 dev->base_addr = iobase;
434
435 if (iobase > 0x400) {
436 outb(eisa_cr, EISA_CR);
437 }
438
439 lemac = eeprom_image[EEPROM_CHIPVER];
440 cmr = inb(EWRK3_CMR);
441
442 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
443 ((lemac == LeMAC2) && !(cmr & HS))) {
444 printk("%s: %s at %#3x", dev->name, name, iobase);
445 hard_strapped = 1;
446 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
447
448 printk("%s: %s at %#3x (EISA slot %d)",
449 dev->name, name, iobase, ((iobase>>12)&0x0f));
450 } else {
451 printk("%s: %s at %#3x", dev->name, name, iobase);
452 }
453
454 if (!status) {
455 printk(", h/w address ");
456 if (lemac == LeMAC2) {
457 for (i = 0;i < ETH_ALEN - 1;i++) {
458 printk("%2.2x:", dev->dev_addr[i] =
459 eeprom_image[EEPROM_PADDR0 + i]);
460 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
461 }
462 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
463 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
464 } else {
465 DevicePresent(iobase);
466 for (i = 0; i < ETH_ALEN - 1; i++) {
467 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
468 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
469 }
470 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
471 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
472 }
473
474 if (aprom_crc(dev, eeprom_image, lemac)) {
475 printk(" which has an EEPROM CRC error.\n");
476 status = -ENXIO;
477 } else {
478 if (lemac == LeMAC2) {
479 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
480 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
481 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
482 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
483 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
484 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
485 }
486 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
487 outb(cmr, EWRK3_CMR);
488
489 cr = inb(EWRK3_CR);
490 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
491 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
492 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
493 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
494 outb(cr, EWRK3_CR);
495
496
497
498
499
500 mem_start = inb(EWRK3_MBR);
501 shmem_length = 0;
502 if (mem_start != 0) {
503 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
504 mem_start *= SHMEM_64K;
505 shmem_length = SHMEM_64K;
506 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
507 mem_start *= SHMEM_32K;
508 shmem_length = SHMEM_32K;
509 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
510 mem_start = mem_start * SHMEM_2K + 0x80000;
511 shmem_length = SHMEM_2K;
512 } else {
513 status = -ENXIO;
514 }
515 }
516
517
518
519
520
521
522
523 if (!status) {
524 if (hard_strapped) {
525 printk(" is hard strapped.\n");
526 } else if (mem_start) {
527 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
528 printk(" at 0x%.5lx", mem_start);
529 } else {
530 printk(" is in I/O only mode");
531 }
532
533
534 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
535 GFP_KERNEL);
536 lp = (struct ewrk3_private *)dev->priv;
537 memset(dev->priv, 0, sizeof(struct ewrk3_private));
538 lp->shmem_base = mem_start;
539 lp->shmem_length = shmem_length;
540 lp->lemac = lemac;
541 lp->hard_strapped = hard_strapped;
542
543 lp->mPage = 64;
544 if (cmr & DRAM) lp->mPage <<= 1 ;
545
546 if (!hard_strapped) {
547
548
549
550 icr |= IE;
551 outb(icr, EWRK3_ICR);
552
553
554 dev->dma = 0;
555
556
557
558 if (dev->irq < 2) {
559 #ifndef MODULE
560 unsigned char irqnum;
561
562 autoirq_setup(0);
563
564
565
566
567 icr |=TNEM;
568 outb(1,EWRK3_TDQ);
569 outb(icr, EWRK3_ICR);
570
571 irqnum = irq[((icr & IRQ_SEL) >> 4)];
572
573 dev->irq = autoirq_report(1);
574 if ((dev->irq) && (irqnum == dev->irq)) {
575 printk(" and uses IRQ%d.\n", dev->irq);
576 } else {
577 if (!dev->irq) {
578 printk(" and failed to detect IRQ line.\n");
579 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
580 printk(" and an illegal IRQ line detected.\n");
581 } else {
582 printk(", but incorrect IRQ line detected.\n");
583 }
584 status = -ENXIO;
585 }
586
587 DISABLE_IRQs;
588
589 #endif
590 } else {
591 printk(" and requires IRQ%d.\n", dev->irq);
592 }
593 }
594 } else {
595 status = -ENXIO;
596 }
597 }
598 }
599 } else {
600 status = -ENXIO;
601 }
602 }
603
604 if (!status) {
605 if (ewrk3_debug > 0) {
606 printk(version);
607 }
608
609
610 dev->open = &ewrk3_open;
611 dev->hard_start_xmit = &ewrk3_queue_pkt;
612 dev->stop = &ewrk3_close;
613 dev->get_stats = &ewrk3_get_stats;
614 #ifdef HAVE_MULTICAST
615 dev->set_multicast_list = &set_multicast_list;
616 #endif
617 dev->do_ioctl = &ewrk3_ioctl;
618
619 dev->mem_start = 0;
620
621
622 ether_setup(dev);
623 }
624 } else {
625 status = -ENXIO;
626 }
627
628 return status;
629 }
630
631
632 static int
633 ewrk3_open(struct device *dev)
634 {
635 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
636 int i, iobase = dev->base_addr;
637 int status = 0;
638 unsigned char icr, csr;
639
640
641
642
643 STOP_EWRK3;
644
645 if (!lp->hard_strapped) {
646 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
647 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
648 status = -EAGAIN;
649 } else {
650
651 irq2dev_map[dev->irq] = dev;
652
653
654
655
656 ewrk3_init(dev);
657
658 if (ewrk3_debug > 1){
659 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
660 printk("\tphysical address: ");
661 for (i=0;i<6;i++){
662 printk("%2.2x:",(short)dev->dev_addr[i]);
663 }
664 printk("\n");
665 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
666 if (lp->shmem_length == 0) {
667 printk("\tno shared memory, I/O only mode\n");
668 } else {
669 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
670 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
671 }
672 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
673 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
674 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
675 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
676 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
677 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
678 }
679
680 dev->tbusy = 0;
681 dev->start = 1;
682 dev->interrupt = UNMASK_INTERRUPTS;
683
684
685
686
687 icr = inb(EWRK3_ICR);
688 ENABLE_IRQs;
689
690 }
691 } else {
692 dev->start = 0;
693 dev->tbusy = 1;
694 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
695 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
696 }
697
698 #ifdef MODULE
699 MOD_INC_USE_COUNT;
700 #endif
701
702
703 return status;
704 }
705
706
707
708
709 static void
710 ewrk3_init(struct device *dev)
711 {
712 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
713 char csr, page;
714 short iobase = dev->base_addr;
715
716
717
718
719 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
720
721
722
723
724 while (inb(EWRK3_TQ));
725 while (inb(EWRK3_TDQ));
726 while (inb(EWRK3_RQ));
727 while (inb(EWRK3_FMQ));
728
729
730
731
732 for (page=1;page<lp->mPage;page++) {
733 outb(page, EWRK3_FMQ);
734 }
735
736 lp->lock = 0;
737
738 START_EWRK3;
739 }
740
741
742
743
744 static int
745 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
746 {
747 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
748 int iobase = dev->base_addr;
749 int status = 0;
750 unsigned char icr, csr;
751
752
753 if (dev->tbusy || lp->lock) {
754 int tickssofar = jiffies - dev->trans_start;
755 if (tickssofar < 10) {
756 status = -1;
757 } else if (!lp->hard_strapped) {
758 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
759 dev->name, inb(EWRK3_CSR));
760
761
762
763
764 DISABLE_IRQs;
765
766
767
768
769 STOP_EWRK3;
770
771 ewrk3_init(dev);
772
773
774
775
776 ENABLE_IRQs;
777
778 dev->tbusy=0;
779 dev->trans_start = jiffies;
780 }
781 } else if (skb == NULL) {
782 dev_tint(dev);
783 } else if (skb->len > 0) {
784
785
786
787
788
789 if (set_bit(0, (void*)&dev->tbusy) != 0)
790 printk("%s: Transmitter access conflict.\n", dev->name);
791
792 DISABLE_IRQs;
793
794
795
796
797 if (inb(EWRK3_FMQC) > 0) {
798 unsigned char *buf;
799 unsigned char page;
800
801 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
802 buf = NULL;
803
804
805
806
807 while (set_bit(0, (void *)&lp->lock) != 0);
808 if (lp->shmem_length == IO_ONLY) {
809 outb(page, EWRK3_IOPR);
810 } else if (lp->shmem_length == SHMEM_2K) {
811 buf = (char *) lp->shmem_base;
812 outb(page, EWRK3_MPR);
813 } else if (lp->shmem_length == SHMEM_32K) {
814 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
815 outb((page >> 4), EWRK3_MPR);
816 } else if (lp->shmem_length == SHMEM_64K) {
817 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
818 outb((page >> 5), EWRK3_MPR);
819 } else {
820 status = -1;
821 printk("%s: Oops - your private data area is hosed!\n",dev->name);
822 }
823
824 if (!status) {
825
826
827
828
829
830
831 if (lp->shmem_length == IO_ONLY) {
832 int i;
833 unsigned char *p = skb->data;
834
835 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
836 outb((char)(skb->len & 0xff), EWRK3_DATA);
837 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
838 outb((char)0x04, EWRK3_DATA);
839 for (i=0; i<skb->len; i++) {
840 outb(*p++, EWRK3_DATA);
841 }
842 outb(page, EWRK3_TQ);
843 } else {
844 *buf++ = (char)(QMODE | PAD | IFC);
845 *buf++ = (char)(skb->len & 0xff);
846 if (lp->txc) {
847 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
848 *buf++ = 0x04;
849 *(buf + skb->len) = 0x00;
850 memcpy(buf, skb->data, PRELOAD);
851 outb(page, EWRK3_TQ);
852 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
853 *(buf + skb->len) = 0xff;
854 } else {
855 *buf++ = (char)((skb->len >> 8) & 0xff);
856 *buf++ = 0x04;
857 memcpy(buf, skb->data, skb->len);
858 outb(page, EWRK3_TQ);
859 }
860 }
861
862 dev->trans_start = jiffies;
863
864 dev_kfree_skb (skb, FREE_WRITE);
865
866 } else {
867 outb(page, EWRK3_FMQ);
868 }
869 lp->lock = 0;
870 } else {
871 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
872 (unsigned char) page);
873 }
874 } else {
875 printk("ewrk3_queue_pkt(): No free resources...\n");
876 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
877 }
878
879
880 if (inb(EWRK3_FMQC) > 0) {
881 dev->tbusy = 0;
882 }
883
884 ENABLE_IRQs;
885 }
886
887 return status;
888 }
889
890
891
892
893 static void
894 ewrk3_interrupt(int reg_ptr)
895 {
896 int irq = -(((struct pt_regs *)reg_ptr)->orig_eax+2);
897 struct device *dev = (struct device *)(irq2dev_map[irq]);
898 struct ewrk3_private *lp;
899 int iobase;
900 unsigned char icr, cr, csr;
901
902 if (dev == NULL) {
903 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
904 } else {
905 lp = (struct ewrk3_private *)dev->priv;
906 iobase = dev->base_addr;
907
908 if (dev->interrupt)
909 printk("%s: Re-entering the interrupt handler.\n", dev->name);
910
911 dev->interrupt = MASK_INTERRUPTS;
912
913
914 csr = inb(EWRK3_CSR);
915
916
917
918
919 DISABLE_IRQs;
920
921 cr = inb(EWRK3_CR);
922 cr |= LED;
923 outb(cr, EWRK3_CR);
924
925 if (csr & RNE)
926 ewrk3_rx(dev);
927
928 if (csr & TNE)
929 ewrk3_tx(dev);
930
931
932
933
934
935
936
937 if (inb(EWRK3_FMQC)) {
938 irq_mask |= TXDM|RXDM;
939 csr &= ~(TXD|RXD);
940 outb(csr, EWRK3_CSR);
941 dev->tbusy = 0;
942 mark_bh(NET_BH);
943 } else {
944 irq_mask &= ~(TXDM|RXDM);
945 }
946
947
948 cr &= ~LED;
949 outb(cr, EWRK3_CR);
950
951 dev->interrupt = UNMASK_INTERRUPTS;
952
953 ENABLE_IRQs;
954 }
955
956 return;
957 }
958
959 static int
960 ewrk3_rx(struct device *dev)
961 {
962 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
963 int i, iobase = dev->base_addr;
964 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
965 int status = 0;
966
967 while (inb(EWRK3_RQC) && !status) {
968 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
969 buf = NULL;
970
971
972
973
974
975 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
976 if (lp->shmem_length == IO_ONLY) {
977 tmpPage = inb(EWRK3_IOPR);
978 } else {
979 tmpPage = inb(EWRK3_MPR);
980 }
981 }
982
983
984
985
986 if (lp->shmem_length == IO_ONLY) {
987 outb(page, EWRK3_IOPR);
988 } else if (lp->shmem_length == SHMEM_2K) {
989 buf = (char *) lp->shmem_base;
990 outb(page, EWRK3_MPR);
991 } else if (lp->shmem_length == SHMEM_32K) {
992 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
993 outb((page >> 4), EWRK3_MPR);
994 } else if (lp->shmem_length == SHMEM_64K) {
995 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
996 outb((page >> 5), EWRK3_MPR);
997 } else {
998 status = -1;
999 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1000 }
1001
1002 if (!status) {
1003 char rx_status;
1004 int pkt_len;
1005
1006 if (lp->shmem_length == IO_ONLY) {
1007 rx_status = inb(EWRK3_DATA);
1008 pkt_len = inb(EWRK3_DATA);
1009 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1010 } else {
1011 rx_status = (char)(*buf++);
1012 pkt_len = (short)(*buf+((*(buf+1))<<8));
1013 buf+=3;
1014 }
1015
1016 if (!(rx_status & ROK)) {
1017 lp->stats.rx_errors++;
1018 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1019 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1020 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1021 } else {
1022 struct sk_buff *skb;
1023
1024 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1025 skb->len = pkt_len;
1026 skb->dev = dev;
1027
1028 if (lp->shmem_length == IO_ONLY) {
1029 unsigned char *p = skb->data;
1030
1031 *p = inb(EWRK3_DATA);
1032 for (i=0; i<skb->len; i++) {
1033 *p++ = inb(EWRK3_DATA);
1034 }
1035 } else {
1036 memcpy(skb->data, buf, pkt_len);
1037 }
1038
1039
1040
1041
1042
1043 netif_rx(skb);
1044
1045
1046
1047
1048 lp->stats.rx_packets++;
1049 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1050 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1051 lp->pktStats.bins[i]++;
1052 i = EWRK3_PKT_STAT_SZ;
1053 }
1054 }
1055 buf = skb->data;
1056 if (buf[0] & 0x01) {
1057 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1058 lp->pktStats.broadcast++;
1059 } else {
1060 lp->pktStats.multicast++;
1061 }
1062 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1063 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1064 lp->pktStats.unicast++;
1065 }
1066
1067 lp->pktStats.bins[0]++;
1068 if (lp->pktStats.bins[0] == 0) {
1069 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1070 }
1071 } else {
1072 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1073 lp->stats.rx_dropped++;
1074 break;
1075 }
1076 }
1077 }
1078
1079
1080
1081 outb(page, EWRK3_FMQ);
1082
1083 if (tmpLock) {
1084 if (lp->shmem_length == IO_ONLY) {
1085 outb(tmpPage, EWRK3_IOPR);
1086 } else {
1087 outb(tmpPage, EWRK3_MPR);
1088 }
1089 }
1090 lp->lock = 0;
1091 } else {
1092 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1093 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1094 }
1095 }
1096 return status;
1097 }
1098
1099
1100
1101
1102 static int
1103 ewrk3_tx(struct device *dev)
1104 {
1105 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1106 int iobase = dev->base_addr;
1107 unsigned char tx_status;
1108
1109 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1110 if (tx_status & VSTS) {
1111 if (tx_status & MAC_TXE) {
1112 lp->stats.tx_errors++;
1113 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1114 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1115 if (tx_status & MAC_CTU) {
1116 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1117 lp->pktStats.tx_underruns++;
1118 } else {
1119 lp->pktStats.excessive_underruns++;
1120 }
1121 } else if (tx_status & MAC_COLL) {
1122 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1123 lp->stats.collisions++;
1124 } else {
1125 lp->pktStats.excessive_collisions++;
1126 }
1127 }
1128 } else {
1129 lp->stats.tx_packets++;
1130 }
1131 }
1132 }
1133
1134 return 0;
1135 }
1136
1137 static int
1138 ewrk3_close(struct device *dev)
1139 {
1140 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1141 int iobase = dev->base_addr;
1142 unsigned char icr, csr;
1143
1144 dev->start = 0;
1145 dev->tbusy = 1;
1146
1147 if (ewrk3_debug > 1) {
1148 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1149 dev->name, inb(EWRK3_CSR));
1150 }
1151
1152
1153
1154
1155 DISABLE_IRQs;
1156
1157 STOP_EWRK3;
1158
1159
1160
1161
1162
1163
1164
1165 while (inb(EWRK3_TQ));
1166 while (inb(EWRK3_TDQ));
1167 while (inb(EWRK3_RQ));
1168
1169 if (!lp->hard_strapped) {
1170 free_irq(dev->irq);
1171
1172 irq2dev_map[dev->irq] = 0;
1173 }
1174
1175 #ifdef MODULE
1176 MOD_DEC_USE_COUNT;
1177 #endif
1178
1179 return 0;
1180 }
1181
1182 static struct enet_statistics *
1183 ewrk3_get_stats(struct device *dev)
1184 {
1185 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1186
1187
1188
1189 return &lp->stats;
1190 }
1191
1192
1193
1194
1195
1196
1197
1198
1199 static void
1200 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1201 {
1202 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1203 int iobase = dev->base_addr;
1204 char *multicast_table;
1205 unsigned char csr;
1206
1207 csr = inb(EWRK3_CSR);
1208
1209 if (lp->shmem_length == IO_ONLY) {
1210 multicast_table = (char *) PAGE0_HTE;
1211 } else {
1212 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1213 }
1214
1215 if (num_addrs >= 0) {
1216 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1217 csr &= ~PME;
1218 csr |= MCE;
1219 outb(csr, EWRK3_CSR);
1220 } else {
1221 csr |= PME;
1222 csr &= ~MCE;
1223 outb(csr, EWRK3_CSR);
1224 }
1225 }
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1236 {
1237 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1238 int iobase = dev->base_addr;
1239 char j, ctrl, bit, octet;
1240 short *p = (short *) multicast_table;
1241 unsigned short hashcode;
1242 int i;
1243 long int crc, poly = (long int) CRC_POLYNOMIAL;
1244
1245 while (set_bit(0, (void *)&lp->lock) != 0);
1246
1247 if (lp->shmem_length == IO_ONLY) {
1248 outb(0, EWRK3_IOPR);
1249 outw((short)((long)multicast_table), EWRK3_PIR1);
1250 } else {
1251 outb(0, EWRK3_MPR);
1252 }
1253
1254 if (num_addrs == HASH_TABLE_LEN) {
1255 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1256 if (lp->shmem_length == IO_ONLY) {
1257 outb(0xff, EWRK3_DATA);
1258 } else {
1259 *p++ = 0xffff;
1260 i++;
1261 }
1262 }
1263 } else if (num_addrs == 0) {
1264 if (lp->shmem_length == IO_ONLY) {
1265 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1266 outb(0x00, EWRK3_DATA);
1267 }
1268 } else {
1269 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1270 }
1271 } else {
1272 for (i=0;i<num_addrs;i++) {
1273 if (((char) *(addrs+ETH_ALEN*i) & 0x01) == 1) {
1274 crc = (long int) 0xffffffff;
1275 for (octet=0;octet<ETH_ALEN;octet++) {
1276 for(j=0;j<8;j++) {
1277 bit = (((char)* (addrs+ETH_ALEN*i+octet)) >> j) & 0x01;
1278 ctrl = ((crc < 0) ? 1 : 0);
1279 crc <<= 1;
1280 if (bit ^ ctrl) {
1281 crc ^= poly;
1282 }
1283 }
1284 }
1285 hashcode = (crc & 0x01);
1286 for (j=0;j<8;j++) {
1287 hashcode <<= 1;
1288 crc >>= 1;
1289 hashcode |= (crc & 0x01);
1290 }
1291 octet = hashcode >> 3;
1292
1293 if (lp->shmem_length == IO_ONLY) {
1294 unsigned char tmp;
1295
1296 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1297 tmp = inb(EWRK3_DATA);
1298 tmp |= (1 << (hashcode & 0x07));
1299 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1300 outb(tmp, EWRK3_DATA);
1301 } else {
1302 multicast_table[octet] |= (1 << (hashcode & 0x07));
1303 }
1304 }
1305 }
1306 }
1307
1308 lp->lock = 0;
1309
1310 return;
1311 }
1312
1313 #ifndef MODULE
1314
1315
1316
1317 static struct device *isa_probe(struct device *dev)
1318 {
1319 int i, iobase, status;
1320 unsigned long int tmp = mem_chkd;
1321
1322 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1323 i < 24;
1324 iobase += EWRK3_IOP_INC, i++) {
1325 if (tmp & 0x01) {
1326 if (DevicePresent(iobase) == 0) {
1327
1328
1329
1330
1331 if (num_ewrk3s > 0) {
1332 dev = alloc_device(dev, iobase);
1333 } else {
1334 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1335 num_ewrk3s++;
1336 }
1337 }
1338 num_eth++;
1339 } else {
1340 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1341 }
1342 }
1343 tmp >>= 1;
1344 }
1345
1346 return dev;
1347 }
1348
1349
1350
1351
1352
1353 static struct device *eisa_probe(struct device *dev)
1354 {
1355 int i, iobase = EWRK3_EISA_IO_PORTS;
1356 int status;
1357
1358 iobase+=EISA_SLOT_INC;
1359 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1360
1361 if (DevicePresent(iobase) == 0) {
1362
1363
1364
1365
1366 mem_chkd |= (0x01 << (i + 24));
1367 if (num_ewrk3s > 0) {
1368 dev = alloc_device(dev, iobase);
1369 } else {
1370 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1371 num_ewrk3s++;
1372 }
1373 }
1374 num_eth++;
1375 }
1376 }
1377 return dev;
1378 }
1379
1380
1381
1382
1383
1384 static struct device *alloc_device(struct device *dev, int iobase)
1385 {
1386
1387
1388
1389 while (dev->next != NULL) {
1390 if (dev->next->base_addr == 0xffe0) break;
1391 dev = dev->next;
1392 num_eth++;
1393 }
1394
1395
1396
1397
1398
1399 if (dev->next == NULL) {
1400 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1401 GFP_KERNEL);
1402 if (dev->next == NULL) {
1403 printk("eth%d: Device not initialised, insufficient memory\n",
1404 num_eth);
1405 }
1406 }
1407
1408
1409
1410
1411
1412
1413 if ((dev->next != NULL) &&
1414 (num_eth > 0) && (num_eth < 9999)) {
1415 dev = dev->next;
1416 dev->name = (char *)(dev + sizeof(struct device));
1417 sprintf(dev->name,"eth%d", num_eth);
1418 dev->base_addr = iobase;
1419 dev->next = NULL;
1420 dev->init = &ewrk3_probe;
1421 num_ewrk3s++;
1422 }
1423
1424 return dev;
1425 }
1426 #endif
1427
1428
1429
1430
1431 static int Read_EEPROM(short iobase, unsigned char eaddr)
1432 {
1433 int i;
1434
1435 outb((eaddr & 0x3f), EWRK3_PIR1);
1436 outb(EEPROM_RD, EWRK3_IOPR);
1437 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1438
1439 return inw(EWRK3_EPROM1);
1440 }
1441
1442
1443
1444
1445 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1446 {
1447 int i;
1448
1449 outb(EEPROM_WR_EN, EWRK3_IOPR);
1450 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1451 outw(data, EWRK3_EPROM1);
1452 outb((eaddr & 0x3f), EWRK3_PIR1);
1453 outb(EEPROM_WR, EWRK3_IOPR);
1454 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1455 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1456 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1457
1458 return 0;
1459 }
1460
1461
1462
1463
1464 static void EthwrkSignature(char *name, char *eeprom_image)
1465 {
1466 unsigned long i,j,k;
1467 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1468
1469 strcpy(name, "");
1470 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1471 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1472 if (signatures[i][k] == eeprom_image[j]) {
1473 k++;
1474 } else {
1475 k=0;
1476 }
1477 }
1478 if (k == strlen(signatures[i])) {
1479 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1480 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1481 name[EWRK3_NAME_LENGTH] = '\0';
1482 }
1483 }
1484 }
1485
1486 return;
1487 }
1488
1489
1490
1491
1492
1493
1494 static int DevicePresent(short iobase)
1495 {
1496 static short fp=1,sigLength=0;
1497 static char devSig[] = PROBE_SEQUENCE;
1498 char data;
1499 int i, j, status = 0;
1500 static char asc2hex(char value);
1501
1502
1503
1504
1505 if (fp) {
1506 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1507 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1508 devSig[i]<<=4;
1509 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1510 devSig[j]=devSig[i]+devSig[i+1];
1511 } else {
1512 status= -1;
1513 }
1514 } else {
1515 status= -1;
1516 }
1517 }
1518 sigLength=j;
1519 fp = 0;
1520 }
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530 if (!status) {
1531 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1532 data = inb(EWRK3_APROM);
1533 if (devSig[j] == data) {
1534 j++;
1535 } else {
1536 j=0;
1537 }
1538 }
1539
1540 if (j!=sigLength) {
1541 status = -ENODEV;
1542 }
1543 }
1544
1545 return status;
1546 }
1547
1548 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1549 {
1550 long k;
1551 unsigned short j,chksum;
1552 unsigned char crc, lfsr, sd, status = 0;
1553 int iobase = dev->base_addr;
1554
1555 if (chipType == LeMAC2) {
1556 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1557 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1558 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1559 crc = (crc >> 1) + lfsr;
1560 }
1561 }
1562 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1563 } else {
1564 for (k=0,j=0;j<3;j++) {
1565 k <<= 1 ;
1566 if (k > 0xffff) k-=0xffff;
1567 k += inw(EWRK3_PAR0 + (j<<1));
1568 if (k > 0xffff) k-=0xffff;
1569 }
1570 if (k == 0xffff) k=0;
1571 chksum = inb(EWRK3_APROM);
1572 chksum |= (inb(EWRK3_APROM)<<8);
1573 if (k != chksum) status = -1;
1574 }
1575
1576 return status;
1577 }
1578
1579
1580
1581
1582
1583 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq)
1584 {
1585 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1586 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1587 int i, j, iobase = dev->base_addr, status = 0;
1588 unsigned char csr;
1589 union {
1590 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1591 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1592 } tmp;
1593
1594 switch(ioc->cmd) {
1595 case EWRK3_GET_HWADDR:
1596 for (i=0; i<ETH_ALEN; i++) {
1597 tmp.addr[i] = dev->dev_addr[i];
1598 }
1599 ioc->len = ETH_ALEN;
1600 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1601
1602 break;
1603 case EWRK3_SET_HWADDR:
1604 if (suser()) {
1605 csr = inb(EWRK3_CSR);
1606 csr |= (TXD|RXD);
1607 outb(csr, EWRK3_CSR);
1608
1609 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1610 for (i=0; i<ETH_ALEN; i++) {
1611 dev->dev_addr[i] = tmp.addr[i];
1612 outb(tmp.addr[i], EWRK3_PAR0 + i);
1613 }
1614
1615 csr &= ~(TXD|RXD);
1616 outb(csr, EWRK3_CSR);
1617 } else {
1618 status = -EPERM;
1619 }
1620
1621 break;
1622 case EWRK3_SET_PROM:
1623 if (suser()) {
1624 csr = inb(EWRK3_CSR);
1625 csr |= PME;
1626 csr &= ~MCE;
1627 outb(csr, EWRK3_CSR);
1628 } else {
1629 status = -EPERM;
1630 }
1631
1632 break;
1633 case EWRK3_CLR_PROM:
1634 if (suser()) {
1635 csr = inb(EWRK3_CSR);
1636 csr &= ~PME;
1637 outb(csr, EWRK3_CSR);
1638 } else {
1639 status = -EPERM;
1640 }
1641
1642 break;
1643 case EWRK3_SAY_BOO:
1644 printk("%s: Boo!\n", dev->name);
1645
1646 break;
1647 case EWRK3_GET_MCA:
1648 while (set_bit(0, (void *)&lp->lock) != 0);
1649 if (lp->shmem_length == IO_ONLY) {
1650 outb(0, EWRK3_IOPR);
1651 outw(PAGE0_HTE, EWRK3_PIR1);
1652 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1653 tmp.addr[i] = inb(EWRK3_DATA);
1654 }
1655 } else {
1656 outb(0, EWRK3_MPR);
1657 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1658 }
1659 ioc->len = (HASH_TABLE_LEN >> 3);
1660 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1661 lp->lock = 0;
1662
1663 break;
1664 case EWRK3_SET_MCA:
1665 if (suser()) {
1666 if (ioc->len != HASH_TABLE_LEN) {
1667 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1668 }
1669 set_multicast_list(dev, ioc->len, tmp.addr);
1670 } else {
1671 status = -EPERM;
1672 }
1673
1674 break;
1675 case EWRK3_CLR_MCA:
1676 if (suser()) {
1677 set_multicast_list(dev, 0, NULL);
1678 } else {
1679 status = -EPERM;
1680 }
1681
1682 break;
1683 case EWRK3_MCA_EN:
1684 if (suser()) {
1685 csr = inb(EWRK3_CSR);
1686 csr |= MCE;
1687 csr &= ~PME;
1688 outb(csr, EWRK3_CSR);
1689 } else {
1690 status = -EPERM;
1691 }
1692
1693 break;
1694 case EWRK3_GET_STATS:
1695 cli();
1696 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1697 ioc->len = EWRK3_PKT_STAT_SZ;
1698 sti();
1699
1700 break;
1701 case EWRK3_CLR_STATS:
1702 if (suser()) {
1703 cli();
1704 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1705 sti();
1706 } else {
1707 status = -EPERM;
1708 }
1709
1710 break;
1711 case EWRK3_GET_CSR:
1712 tmp.addr[0] = inb(EWRK3_CSR);
1713 memcpy_tofs(ioc->data, tmp.addr, 1);
1714
1715 break;
1716 case EWRK3_SET_CSR:
1717 if (suser()) {
1718 memcpy_fromfs(tmp.addr, ioc->data, 1);
1719 outb(tmp.addr[0], EWRK3_CSR);
1720 } else {
1721 status = -EPERM;
1722 }
1723
1724 break;
1725 case EWRK3_GET_EEPROM:
1726 if (suser()) {
1727 for (i=0; i<(EEPROM_MAX>>1); i++) {
1728 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1729 }
1730 i = EEPROM_MAX;
1731 tmp.addr[i++] = inb(EWRK3_CMR);
1732 for (j=0;j<ETH_ALEN;j++) {
1733 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1734 }
1735 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1736 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1737 } else {
1738 status = -EPERM;
1739 }
1740
1741 break;
1742 case EWRK3_SET_EEPROM:
1743 if (suser()) {
1744 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1745 for (i=0; i<(EEPROM_MAX>>1); i++) {
1746 Write_EEPROM(tmp.val[i], iobase, i);
1747 }
1748 } else {
1749 status = -EPERM;
1750 }
1751
1752 break;
1753 case EWRK3_GET_CMR:
1754 tmp.addr[0] = inb(EWRK3_CMR);
1755 memcpy_tofs(ioc->data, tmp.addr, 1);
1756
1757 break;
1758 case EWRK3_SET_TX_CUT_THRU:
1759 if (suser()) {
1760 lp->txc = 1;
1761 } else {
1762 status = -EPERM;
1763 }
1764
1765 break;
1766 case EWRK3_CLR_TX_CUT_THRU:
1767 if (suser()) {
1768 lp->txc = 0;
1769 } else {
1770 status = -EPERM;
1771 }
1772
1773 break;
1774 default:
1775 status = -EOPNOTSUPP;
1776 }
1777
1778 return status;
1779 }
1780
1781 static char asc2hex(char value)
1782 {
1783 value -= 0x30;
1784 if (value >= 0) {
1785 if (value > 9) {
1786 value &= 0x1f;
1787 value -= 0x07;
1788 if ((value < 0x0a) || (value > 0x0f)) {
1789 value = -1;
1790 }
1791 }
1792 } else {
1793 value = -1;
1794 }
1795 return value;
1796 }
1797
1798 #ifdef MODULE
1799 char kernel_version[] = UTS_RELEASE;
1800 static struct device thisEthwrk = {
1801 " ",
1802 0, 0, 0, 0,
1803 0x300, 5,
1804 0, 0, 0, NULL, ewrk3_probe };
1805
1806 int
1807 init_module(void)
1808 {
1809 if (register_netdev(&thisEthwrk) != 0)
1810 return -EIO;
1811 return 0;
1812 }
1813
1814 void
1815 cleanup_module(void)
1816 {
1817 if (MOD_IN_USE) {
1818 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1819 } else {
1820 unregister_netdev(&thisEthwrk);
1821 }
1822 }
1823 #endif
1824
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