root/include/asm-alpha/dma.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. enable_dma
  2. disable_dma
  3. clear_dma_ff
  4. set_dma_mode
  5. set_dma_page
  6. set_dma_addr
  7. set_dma_count
  8. get_dma_residue

   1 /*
   2  * include/asm-alpha/dma.h
   3  *
   4  * This is essentially the same as the i386 DMA stuff, as
   5  * the AlphaPC uses normal EISA dma (but the DMA controller
   6  * is not on the EISA bus, but on the local VL82c106 bus).
   7  *
   8  * These DMA-functions don't know about EISA DMA yet..
   9  */
  10 
  11 /* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
  12  * linux/include/asm/dma.h: Defines for using and allocating dma channels.
  13  * Written by Hennus Bergman, 1992.
  14  * High DMA channel support & info by Hannu Savolainen
  15  * and John Boyd, Nov. 1992.
  16  */
  17 
  18 #ifndef _ASM_DMA_H
  19 #define _ASM_DMA_H
  20 
  21 #include <asm/io.h>             /* need byte IO */
  22 
  23 #define dma_outb        outb_local
  24 #define dma_inb         inb_local
  25 
  26 /*
  27  * NOTES about DMA transfers:
  28  *
  29  *  controller 1: channels 0-3, byte operations, ports 00-1F
  30  *  controller 2: channels 4-7, word operations, ports C0-DF
  31  *
  32  *  - ALL registers are 8 bits only, regardless of transfer size
  33  *  - channel 4 is not used - cascades 1 into 2.
  34  *  - channels 0-3 are byte - addresses/counts are for physical bytes
  35  *  - channels 5-7 are word - addresses/counts are for physical words
  36  *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  37  *  - transfer count loaded to registers is 1 less than actual count
  38  *  - controller 2 offsets are all even (2x offsets for controller 1)
  39  *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  40  *  - page registers for 0-3 use bit 0, represent 64K pages
  41  *
  42  * DMA transfers are limited to the lower 16MB of _physical_ memory.  
  43  * Note that addresses loaded into registers must be _physical_ addresses,
  44  * not logical addresses (which may differ if paging is active).
  45  *
  46  *  Address mapping for channels 0-3:
  47  *
  48  *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  49  *    |  ...  |   |  ... |   |  ... |
  50  *    |  ...  |   |  ... |   |  ... |
  51  *    |  ...  |   |  ... |   |  ... |
  52  *   P7  ...  P0  A7 ... A0  A7 ... A0   
  53  * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  54  *
  55  *  Address mapping for channels 5-7:
  56  *
  57  *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  58  *    |  ...  |   \   \   ... \  \  \  ... \  \
  59  *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  60  *    |  ...  |     \   \   ... \  \  \  ... \
  61  *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
  62  * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  63  *
  64  * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  65  * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  66  * the hardware level, so odd-byte transfers aren't possible).
  67  *
  68  * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  69  * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  70  * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
  71  *
  72  */
  73 
  74 #define MAX_DMA_CHANNELS        8
  75 
  76 /* 8237 DMA controllers */
  77 #define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
  78 #define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
  79 
  80 /* DMA controller registers */
  81 #define DMA1_CMD_REG            0x08    /* command register (w) */
  82 #define DMA1_STAT_REG           0x08    /* status register (r) */
  83 #define DMA1_REQ_REG            0x09    /* request register (w) */
  84 #define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
  85 #define DMA1_MODE_REG           0x0B    /* mode register (w) */
  86 #define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
  87 #define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
  88 #define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
  89 #define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
  90 #define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
  91 
  92 #define DMA2_CMD_REG            0xD0    /* command register (w) */
  93 #define DMA2_STAT_REG           0xD0    /* status register (r) */
  94 #define DMA2_REQ_REG            0xD2    /* request register (w) */
  95 #define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
  96 #define DMA2_MODE_REG           0xD6    /* mode register (w) */
  97 #define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
  98 #define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
  99 #define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 100 #define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 101 #define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 102 
 103 #define DMA_ADDR_0              0x00    /* DMA address registers */
 104 #define DMA_ADDR_1              0x02
 105 #define DMA_ADDR_2              0x04
 106 #define DMA_ADDR_3              0x06
 107 #define DMA_ADDR_4              0xC0
 108 #define DMA_ADDR_5              0xC4
 109 #define DMA_ADDR_6              0xC8
 110 #define DMA_ADDR_7              0xCC
 111 
 112 #define DMA_CNT_0               0x01    /* DMA count registers */
 113 #define DMA_CNT_1               0x03
 114 #define DMA_CNT_2               0x05
 115 #define DMA_CNT_3               0x07
 116 #define DMA_CNT_4               0xC2
 117 #define DMA_CNT_5               0xC6
 118 #define DMA_CNT_6               0xCA
 119 #define DMA_CNT_7               0xCE
 120 
 121 #define DMA_PAGE_0              0x87    /* DMA page registers */
 122 #define DMA_PAGE_1              0x83
 123 #define DMA_PAGE_2              0x81
 124 #define DMA_PAGE_3              0x82
 125 #define DMA_PAGE_5              0x8B
 126 #define DMA_PAGE_6              0x89
 127 #define DMA_PAGE_7              0x8A
 128 
 129 #define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 130 #define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 131 #define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 132 
 133 /* enable/disable a specific DMA channel */
 134 static __inline__ void enable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 135 {
 136         if (dmanr<=3)
 137                 dma_outb(dmanr,  DMA1_MASK_REG);
 138         else
 139                 dma_outb(dmanr & 3,  DMA2_MASK_REG);
 140 }
 141 
 142 static __inline__ void disable_dma(unsigned int dmanr)
     /* [previous][next][first][last][top][bottom][index][help] */
 143 {
 144         if (dmanr<=3)
 145                 dma_outb(dmanr | 4,  DMA1_MASK_REG);
 146         else
 147                 dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 148 }
 149 
 150 /* Clear the 'DMA Pointer Flip Flop'.
 151  * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 152  * Use this once to initialize the FF to a known state.
 153  * After that, keep track of it. :-)
 154  * --- In order to do that, the DMA routines below should ---
 155  * --- only be used while interrupts are disabled! ---
 156  */
 157 static __inline__ void clear_dma_ff(unsigned int dmanr)
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 158 {
 159         if (dmanr<=3)
 160                 dma_outb(0,  DMA1_CLEAR_FF_REG);
 161         else
 162                 dma_outb(0,  DMA2_CLEAR_FF_REG);
 163 }
 164 
 165 /* set mode (above) for a specific DMA channel */
 166 static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
     /* [previous][next][first][last][top][bottom][index][help] */
 167 {
 168         if (dmanr<=3)
 169                 dma_outb(mode | dmanr,  DMA1_MODE_REG);
 170         else
 171                 dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 172 }
 173 
 174 /* Set only the page register bits of the transfer address.
 175  * This is used for successive transfers when we know the contents of
 176  * the lower 16 bits of the DMA current address register, but a 64k boundary
 177  * may have been crossed.
 178  */
 179 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
     /* [previous][next][first][last][top][bottom][index][help] */
 180 {
 181         switch(dmanr) {
 182                 case 0:
 183                         dma_outb(pagenr, DMA_PAGE_0);
 184                         break;
 185                 case 1:
 186                         dma_outb(pagenr, DMA_PAGE_1);
 187                         break;
 188                 case 2:
 189                         dma_outb(pagenr, DMA_PAGE_2);
 190                         break;
 191                 case 3:
 192                         dma_outb(pagenr, DMA_PAGE_3);
 193                         break;
 194                 case 5:
 195                         dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 196                         break;
 197                 case 6:
 198                         dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 199                         break;
 200                 case 7:
 201                         dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 202                         break;
 203         }
 204 }
 205 
 206 
 207 /* Set transfer address & page bits for specific DMA channel.
 208  * Assumes dma flipflop is clear.
 209  */
 210 static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
     /* [previous][next][first][last][top][bottom][index][help] */
 211 {
 212         set_dma_page(dmanr, a>>16);
 213         if (dmanr <= 3)  {
 214             dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 215             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 216         }  else  {
 217             dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 218             dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 219         }
 220 }
 221 
 222 
 223 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
 224  * a specific DMA channel.
 225  * You must ensure the parameters are valid.
 226  * NOTE: from a manual: "the number of transfers is one more
 227  * than the initial word count"! This is taken into account.
 228  * Assumes dma flip-flop is clear.
 229  * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 230  */
 231 static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
     /* [previous][next][first][last][top][bottom][index][help] */
 232 {
 233         count--;
 234         if (dmanr <= 3)  {
 235             dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 236             dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 237         } else {
 238             dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 239             dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 240         }
 241 }
 242 
 243 
 244 /* Get DMA residue count. After a DMA transfer, this
 245  * should return zero. Reading this while a DMA transfer is
 246  * still in progress will return unpredictable results.
 247  * If called before the channel has been used, it may return 1.
 248  * Otherwise, it returns the number of _bytes_ left to transfer.
 249  *
 250  * Assumes DMA flip-flop is clear.
 251  */
 252 static __inline__ int get_dma_residue(unsigned int dmanr)
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 253 {
 254         unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 255                                          : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 256 
 257         /* using short to get 16-bit wrap around */
 258         unsigned short count;
 259 
 260         count = 1 + dma_inb(io_port);
 261         count += dma_inb(io_port) << 8;
 262         
 263         return (dmanr<=3)? count : (count<<1);
 264 }
 265 
 266 
 267 /* These are in kernel/dma.c: */
 268 extern int request_dma(unsigned int dmanr, char * device_id);   /* reserve a DMA channel */
 269 extern void free_dma(unsigned int dmanr);       /* release it again */
 270 
 271 
 272 #endif /* _ASM_DMA_H */

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