include/linux/pci.h

/* */
   1 /*
   2  * PCI defines and function prototypes
   3  * Copyright 1994, Drew Eckhardt
   4  *
   5  * For more information, please consult 
   6  * 
   7  * PCI BIOS Specification Revision
   8  * PCI Local Bus Specification
   9  * PCI System Design Guide
  10  *
  11  * PCI Special Interest Group
  12  * M/S HF3-15A
  13  * 5200 N.E. Elam Young Parkway
  14  * Hillsboro, Oregon 97124-6497
  15  * +1 (503) 696-2000 
  16  * +1 (800) 433-5177
  17  * 
  18  * Manuals are $25 each or $50 for all three, plus $7 shipping 
  19  * within the United States, $35 abroad.
  20  */
  21 
  22 #ifndef PCI_H
  23 #define PCI_H
  24 
  25 /* Configuration method #1 */
  26 #define PCI_CONFIG1_ADDRESS_REG  0xcf8
  27 #define PCI_CONFIG1_ENABLE 0x80000000
  28 #define PCI_CONFIG1_TUPPLE (bus, device, function, register)    \
  29         (PCI_CONFIG1_ENABLE | ((bus) << 16) & 0xff0000 |        \
  30         ((device) << 11) & 0xf800 | ((function) << 8) & 0x700 | \
  31         ((register) << 2) & 0xfc)
  32 #define PCI_CONFIG1_DATA_REG     0xcfc
  33 
  34 /* Configuration method #2, deprecated */
  35 #define PCI_CONFIG2_ENABLE_REG  0xcf8
  36 #define PCI_CONFIG2_ENABLE      0xf0
  37 #define PCI_CONFIG2_TUPPLE (function)                           \
  38         (PCI_CONFIG2_ENABLE | ((function) << 1) & 0xe)
  39 #define PCI_CONFIG2_FORWARD_REG 0xcfa
  40 
  41 /*
  42  * Under PCI, each device has 256 bytes of configuration address space,
  43  * of which the first 64 bytes is standardized as follows : 
  44  */
  45 
  46 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  47 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  48 #define PCI_COMMAND             0x04    /* 16 bits */
  49 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  50 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in I/O space */
  51 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  52 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  53 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  54 #define  PCI_COMMAND_VGA_PALETTE        0x20    /* Enable palette snooping */
  55 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  56 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  57 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  58 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  59 
  60 #define PCI_STATUS              0x06    /* 16 bits */
  61 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  62 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  63 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  64 #define  PCI_STATUS_DEVSEL_FAST 0x000   
  65 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  66 #define  PCI_STATUS_DEVESEL_SLOW 0x400
  67 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  68 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  69 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  70 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  71 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  72 
  73 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  74                                            revision */
  75 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  76 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  77 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  78 #define PCI_BIST                0x0f    /* 8 bits */
  79 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  80 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  81 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  82 
  83 /*
  84  * Base addresses specify locations in memory or I/O space.
  85  * Decoded size can be determined by writing a value of 
  86  * 0xffffffff to the register, and reading it back.  Only 
  87  * 1 bits are decoded.
  88  */
  89 
  90 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  91 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
  92 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
  93 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  94 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  95 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
  96 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
  97 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
  98 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  99 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 100 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 101 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
 102 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 103 #define  PCI_BASE_ADDRESS_MEM_MASK      ~7
 104 #define  PCI_BASE_ADDRESS_IO_MASK       ~3
 105 /* bit 1 is reserved if address_space = 1 */
 106 
 107 /* 0x28-0x2f are reserved */
 108 #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
 109 #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM,
 110                                            bits 31..11 are address,
 111                                            10..2 are reserved */
 112 /* 0x34-0x3b are reserved */
 113 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 114 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 115 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 116 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 117 
 118 #define PCI_CLASS_NOT_DEFINED           0x0000
 119 #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
 120 
 121 #define PCI_CLASS_STORAGE_SCSI          0x0100
 122 #define PCI_CLASS_STORAGE_IDE           0x0101
 123 #define PCI_CLASS_STORAGE_FLOPPY        0x0102
 124 #define PCI_CLASS_STORAGE_IPI           0x0103
 125 #define PCI_CLASS_STORAGE_OTHER         0x0180
 126 
 127 #define PCI_CLASS_NETWORK_ETHERNET      0x0200
 128 #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
 129 #define PCI_CLASS_NETWORK_FDDI          0x0202
 130 #define PCI_CLASS_NETWORK_OTHER         0x0280
 131 
 132 #define PCI_CLASS_DISPLAY_VGA           0x0300
 133 #define PCI_CLASS_DISPLAY_XGA           0x0301
 134 #define PCI_CLASS_DISPLAY_OTHER         0x0380
 135 
 136 #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
 137 #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
 138 #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
 139 
 140 #define PCI_CLASS_MEMORY_RAM            0x0500
 141 #define PCI_CLASS_MEMORY_FLASH          0x0501
 142 #define PCI_CLASS_MEMORY_OTHER          0x0580
 143 
 144 #define PCI_CLASS_BRIDGE_HOST           0x0600
 145 #define PCI_CLASS_BRIDGE_ISA            0x0601
 146 #define PCI_CLASS_BRIDGE_EISA           0x0602
 147 #define PCI_CLASS_BRIDGE_MC             0x0603
 148 #define PCI_CLASS_BRIDGE_PCI            0x0604
 149 #define PCI_CLASS_BRIDGE_PCMCIA         0x0605
 150 #define PCI_CLASS_BRIDGE_OTHER          0x0680
 151 
 152 #define PCI_CLASS_OTHERS                0xff
 153 
 154 struct pci_class_type {
 155         unsigned long class_id;
 156         char *class_name;
 157 };
 158 
 159 #define PCI_CLASS_NUM 27
 160 #define PCI_CLASS_TYPE    { \
 161         {PCI_CLASS_NOT_DEFINED,         "Old unidentified device"}, \
 162         {PCI_CLASS_NOT_DEFINED_VGA,     "Old VGA controller"}, \
 163         {PCI_CLASS_STORAGE_SCSI,        "SCSI bus controller"}, \
 164         {PCI_CLASS_STORAGE_IDE,         "IDE controller"}, \
 165         {PCI_CLASS_STORAGE_FLOPPY,      "Floppy controller"}, \
 166         {PCI_CLASS_STORAGE_IPI,         "IPI bus controller"}, \
 167         {PCI_CLASS_STORAGE_OTHER,       "Unknown mass storage controller"}, \
 168         {PCI_CLASS_NETWORK_ETHERNET,    "Ethernet controller"}, \
 169         {PCI_CLASS_NETWORK_TOKEN_RING,  "Token ring controller"}, \
 170         {PCI_CLASS_NETWORK_FDDI,        "FDDI controller"}, \
 171         {PCI_CLASS_NETWORK_OTHER,       "Unknown network controller"}, \
 172         {PCI_CLASS_DISPLAY_VGA,         "VGA display controller"}, \
 173         {PCI_CLASS_DISPLAY_XGA,         "XGA display controller"}, \
 174         {PCI_CLASS_DISPLAY_OTHER,       "Unknown display controller"}, \
 175         {PCI_CLASS_MULTIMEDIA_VIDEO,    "Video device"}, \
 176         {PCI_CLASS_MULTIMEDIA_AUDIO,    "Audio device"}, \
 177         {PCI_CLASS_MULTIMEDIA_OTHER,    "Unknown multimedia device"}, \
 178         {PCI_CLASS_MEMORY_RAM,          "RAM controller"}, \
 179         {PCI_CLASS_MEMORY_FLASH,        "FLASH controller"}, \
 180         {PCI_CLASS_MEMORY_OTHER,        "Unknown memory controller"}, \
 181         {PCI_CLASS_BRIDGE_HOST,         "Host bridge"}, \
 182         {PCI_CLASS_BRIDGE_ISA,          "ISA bridge"}, \
 183         {PCI_CLASS_BRIDGE_EISA,         "EISA bridge"}, \
 184         {PCI_CLASS_BRIDGE_MC,           "MC bridge"}, \
 185         {PCI_CLASS_BRIDGE_PCI,          "PCI to PCI bridge"}, \
 186         {PCI_CLASS_BRIDGE_PCMCIA,       "PCMCIA bridge"}, \
 187         {PCI_CLASS_BRIDGE_OTHER,        "Unknown bridge device"}, \
 188         {0,                             "Unknown type of PCI device"} \
 189 }
 190 
 191 #define PCI_VENDOR_ID_NCR               0x1000
 192 #define PCI_DEVICE_ID_NCR_53C810        0x0001
 193 #define PCI_DEVICE_ID_NCR_53C815        0x0004
 194 #define PCI_DEVICE_ID_NCR_53C820        0x0002
 195 #define PCI_DEVICE_ID_NCR_53C825        0x0003
 196 
 197 #define PCI_VENDOR_ID_ADAPTEC           0x9004
 198 #define PCI_DEVICE_ID_ADAPTEC_2940      0x7178
 199 
 200 #define PCI_VENDOR_ID_S3                0x5333
 201 #define PCI_DEVICE_ID_S3_864_1          0x88c0
 202 #define PCI_DEVICE_ID_S3_864_2          0x88c1
 203 #define PCI_DEVICE_ID_S3_928            0x88b0
 204 #define PCI_DEVICE_ID_S3_964            0x88d0
 205 #define PCI_DEVICE_ID_S3_811            0x8811
 206 
 207 #define PCI_VENDOR_ID_OPTI              0x1045
 208 #define PCI_DEVICE_ID_OPTI_82C822       0xc822
 209 #define PCI_DEVICE_ID_OPTI_82C621       0xc621
 210 
 211 #define PCI_VENDOR_ID_UMC               0x1060
 212 #define PCI_DEVICE_ID_UMC_UM8881F       0x8881
 213 #define PCI_DEVICE_ID_UMC_UM8886F       0x8886
 214 #define PCI_DEVICE_ID_UMC_UM8673F       0x0101
 215 
 216 #define PCI_VENDOR_ID_DEC               0x1011
 217 #define PCI_DEVICE_ID_DEC_TULIP         0x0002
 218 #define PCI_DEVICE_ID_DEC_TULIP_FAST    0x0009
 219 #define PCI_DEVICE_ID_DEC_FDDI          0x000F
 220 
 221 #define PCI_VENDOR_ID_MATROX            0x102B
 222 
 223 #define PCI_VENDOR_ID_INTEL             0x8086
 224 #define PCI_DEVICE_ID_INTEL_82378       0x0484
 225 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 226 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 227 #define PCI_DEVICE_ID_INTEL_82434       0x04a3
 228 
 229 #define PCI_VENDOR_ID_SMC               0x1042
 230 #define PCI_DEVICE_ID_SMC_37C665        0x1000
 231 
 232 #define PCI_VENDOR_ID_ATI               0x1002
 233 #define PCI_DEVICE_ID_ATI_M32           0x4158
 234 #define PCI_DEVICE_ID_ATI_M64           0x4758
 235 
 236 #define PCI_VENDOR_ID_WEITEK            0x100e
 237 #define PCI_DEVICE_ID_WEITEK_P9000      0x9001
 238 #define PCI_DEVICE_ID_WEITEK_P9100      0x9100
 239 
 240 #define PCI_VENDOR_ID_CIRRUS            0x1013
 241 #define PCI_DEVICE_ID_CIRRUS_5434       0x00A4
 242 
 243 #define PCI_VENDOR_ID_BUSLOGIC          0x104B
 244 #define PCI_DEVICE_ID_BUSLOGIC_946C     0x0140
 245 
 246 #define PCI_VENDOR_ID_N9                0x105D
 247 #define PCI_DEVICE_ID_N9_I128           0x2309
 248 
 249 #define PCI_VENDOR_ID_ALI               0x1025
 250 #define PCI_DEVICE_ID_ALI_M1435         0x1435
 251 
 252 #define PCI_VENDOR_ID_TSENG             0x100c
 253 #define PCI_DEVICE_ID_TSENG_W32P        0x3205
 254 
 255 #define PCI_VENDOR_ID_CMD               0x1095
 256 #define PCI_DEVICE_ID_CMD_640           0x0640
 257 
 258 struct pci_vendor_type {
 259         unsigned short vendor_id;
 260         char *vendor_name;
 261 };
 262 
 263 
 264 #define PCI_VENDOR_NUM 17
 265 #define PCI_VENDOR_TYPE { \
 266         {PCI_VENDOR_ID_NCR,             "NCR"}, \
 267         {PCI_VENDOR_ID_ADAPTEC,         "Adaptec"}, \
 268         {PCI_VENDOR_ID_S3,              "S3 Inc."}, \
 269         {PCI_VENDOR_ID_OPTI,            "OPTI"}, \
 270         {PCI_VENDOR_ID_UMC,             "UMC"}, \
 271         {PCI_VENDOR_ID_DEC,             "DEC"}, \
 272         {PCI_VENDOR_ID_MATROX,          "Matrox"}, \
 273         {PCI_VENDOR_ID_INTEL,           "Intel"}, \
 274         {PCI_VENDOR_ID_SMC,             "SMC"}, \
 275         {PCI_VENDOR_ID_ATI,             "ATI"}, \
 276         {PCI_VENDOR_ID_WEITEK,          "Weitek"}, \
 277         {PCI_VENDOR_ID_CIRRUS,          "Cirrus Logic"}, \
 278         {PCI_VENDOR_ID_BUSLOGIC,        "Bus Logic"}, \
 279         {PCI_VENDOR_ID_N9,              "Number #9"}, \
 280         {PCI_VENDOR_ID_ALI,             "ALI"}, \
 281         {PCI_VENDOR_ID_TSENG,           "Tseng'Lab"}, \
 282         {PCI_VENDOR_ID_CMD,             "CMD"}, \
 283         {0,                             ""} \
 284 }
 285 
 286 struct pci_device_type {
 287         unsigned short vendor_id;
 288         unsigned short device_id;
 289         char *device_name;
 290 };
 291 
 292 #define PCI_DEVICE_NUM 33
 293 #define PCI_DEVICE_TYPE { \
 294         {PCI_VENDOR_ID_NCR,     PCI_DEVICE_ID_NCR_53C810,       "53c810"}, \
 295         {PCI_VENDOR_ID_NCR,     PCI_DEVICE_ID_NCR_53C815,       "53c815"}, \
 296         {PCI_VENDOR_ID_NCR,     PCI_DEVICE_ID_NCR_53C820,       "53c820"}, \
 297         {PCI_VENDOR_ID_NCR,     PCI_DEVICE_ID_NCR_53C825,       "53c825"}, \
 298         {PCI_VENDOR_ID_ADAPTEC, PCI_DEVICE_ID_ADAPTEC_2940,     "2940"}, \
 299         {PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_864_1,         "Vision 864-P"}, \
 300         {PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_864_2,         "Vision 864-P"}, \
 301         {PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_928,           "Vision 928-P"}, \
 302         {PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_964,           "Vision 964-P"}, \
 303         {PCI_VENDOR_ID_S3,      PCI_DEVICE_ID_S3_811,           "Trio64"}, \
 304         {PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C822,      "82C822"}, \
 305         {PCI_VENDOR_ID_OPTI,    PCI_DEVICE_ID_OPTI_82C621,      "82C621"}, \
 306         {PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8881F,      "UM8881F"}, \
 307         {PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8886F,      "UM8886F"}, \
 308         {PCI_VENDOR_ID_UMC,     PCI_DEVICE_ID_UMC_UM8673F,      "UM8673F"}, \
 309         {PCI_VENDOR_ID_DEC,     PCI_DEVICE_ID_DEC_TULIP,        "DC21040"}, \
 310         {PCI_VENDOR_ID_DEC,     PCI_DEVICE_ID_DEC_TULIP_FAST,   "DC21040"}, \
 311         {PCI_VENDOR_ID_DEC,     PCI_DEVICE_ID_DEC_FDDI,         "DEFPA"}, \
 312         {PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82378,      "82378IB"}, \
 313         {PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82424,      "82424ZX"}, \
 314         {PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82375,      "82375EB"}, \
 315         {PCI_VENDOR_ID_INTEL,   PCI_DEVICE_ID_INTEL_82434,      "82434LX"}, \
 316         {PCI_VENDOR_ID_SMC,     PCI_DEVICE_ID_SMC_37C665,       "FDC 37C665"}, \
 317         {PCI_VENDOR_ID_ATI,     PCI_DEVICE_ID_ATI_M32,          "Mach 32"}, \
 318         {PCI_VENDOR_ID_ATI,     PCI_DEVICE_ID_ATI_M64,          "Mach 64"}, \
 319         {PCI_VENDOR_ID_WEITEK,  PCI_DEVICE_ID_WEITEK_P9000,     "P9000"}, \
 320         {PCI_VENDOR_ID_WEITEK,  PCI_DEVICE_ID_WEITEK_P9100,     "P9100"}, \
 321         {PCI_VENDOR_ID_CIRRUS,  PCI_DEVICE_ID_CIRRUS_5434,      "GD 5434"}, \
 322         {PCI_VENDOR_ID_BUSLOGIC,PCI_DEVICE_ID_BUSLOGIC_946C,    "946C"}, \
 323         {PCI_VENDOR_ID_N9,      PCI_DEVICE_ID_N9_I128,          "Imagine 128"}, \
 324         {PCI_VENDOR_ID_ALI,     PCI_DEVICE_ID_ALI_M1435,        "M1435"}, \
 325         {PCI_VENDOR_ID_TSENG,   PCI_DEVICE_ID_TSENG_W32P,       "ET4000W32P"}, \
 326         {PCI_VENDOR_ID_CMD,     PCI_DEVICE_ID_CMD_640,          "640A"}, \
 327         {0,0,"UNKNOWN DEVICE.PLEASE FIND OUT AND MAIL POTTER@CAO-VLSI.IBP.FR"} \
 328 }
 329 
 330 /* PCI BIOS */
 331 
 332 extern int pcibios_present (void);
 333 
 334 #define PCIBIOS_SUCCESSFUL              0x00
 335 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 336 #define PCIBIOS_BAD_VENDOR_ID           0x83
 337 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
 338 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
 339 
 340 /*
 341  * The PCIBIOS calls all bit-field the device_function variable such that 
 342  * the bit fielding matches that of the bl register used in the actual
 343  * calls.
 344  */
 345 
 346 extern int pcibios_find_class (unsigned long class_code, unsigned short index, 
 347     unsigned char *bus, unsigned char *device_fn);
 348 extern int pcibios_find_device (unsigned short vendor, unsigned short device_id, 
 349     unsigned short index, unsigned char *bus, unsigned char *device_fn);
 350 extern int pcibios_read_config_byte (unsigned char bus,
 351     unsigned char device_fn, unsigned char where, unsigned char *value);
 352 extern int pcibios_read_config_word (unsigned char bus,
 353     unsigned char device_fn, unsigned char where, unsigned short *value);
 354 extern int pcibios_read_config_dword (unsigned char bus,
 355     unsigned char device_fn, unsigned char where, unsigned long *value);
 356 extern char *pcibios_strerror (int error);
 357 extern int pcibios_write_config_byte (unsigned char bus,
 358     unsigned char device_fn, unsigned char where, unsigned char value);
 359 extern int pcibios_write_config_word (unsigned char bus,
 360     unsigned char device_fn, unsigned char where, unsigned short value);
 361 extern pcibios_write_config_dword (unsigned char bus,
 362     unsigned char device_fn, unsigned char where, unsigned long value);
 363 #endif /* ndef PCI_H */
/* */
root/include/linux/pci.h

INCLUDED FROM
