This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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128 static char *version = "ewrk3.c:v0.31 12/5/94 davies@wanton.lkg.dec.com\n";
129
130 #include <stdarg.h>
131 #include <linux/kernel.h>
132 #include <linux/sched.h>
133 #include <linux/string.h>
134 #include <linux/ptrace.h>
135 #include <linux/errno.h>
136 #include <linux/ioport.h>
137 #include <linux/malloc.h>
138 #include <linux/interrupt.h>
139 #include <asm/bitops.h>
140 #include <asm/io.h>
141 #include <asm/dma.h>
142 #include <asm/segment.h>
143
144 #include <linux/netdevice.h>
145 #include <linux/etherdevice.h>
146 #include <linux/skbuff.h>
147
148 #include <linux/time.h>
149 #include <linux/types.h>
150 #include <linux/unistd.h>
151
152 #ifdef MODULE
153 #include <linux/module.h>
154 #include <linux/version.h>
155 #endif
156
157 #include "ewrk3.h"
158
159 #ifdef EWRK3_DEBUG
160 static int ewrk3_debug = EWRK3_DEBUG;
161 #else
162 static int ewrk3_debug = 1;
163 #endif
164
165 #ifndef PROBE_LENGTH
166 #define PROBE_LENGTH 32
167 #endif
168
169 #ifndef PROBE_SEQUENCE
170 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
171 #endif
172
173 #ifndef EWRK3_SIGNATURE
174 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
175 #define EWRK3_NAME_LENGTH 8
176 #endif
177
178 #ifndef EWRK3_RAM_BASE_ADDRESSES
179 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
180 #endif
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196 #define EWRK3_IO_BASE 0x100
197 #define EWRK3_IOP_INC 0x20
198 #define EWRK3_IO_SEARCH 0x007dff7f
199 static long mem_chkd = EWRK3_IO_SEARCH;
200
201
202 #ifndef MAX_NUM_EWRK3S
203 #define MAX_NUM_EWRK3S 21
204 #endif
205
206 #ifndef EWRK3_EISA_IO_PORTS
207 #define EWRK3_EISA_IO_PORTS 0x0c00
208 #endif
209
210 #ifndef MAX_EISA_SLOTS
211 #define MAX_EISA_SLOTS 8
212 #define EISA_SLOT_INC 0x1000
213 #endif
214
215 #ifndef CRC_POLYNOMIAL
216 #define CRC_POLYNOMIAL 0x04c11db7
217 #endif
218
219
220
221
222 #define IO_ONLY 0x00
223 #define SHMEM_2K 0x800
224 #define SHMEM_32K 0x8000
225 #define SHMEM_64K 0x10000
226
227
228
229
230 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
231
232 #define ENABLE_IRQs \
233 icr |= irq_mask;\
234 outb(icr, EWRK3_ICR)
235
236 #define DISABLE_IRQs \
237 icr = inb(EWRK3_ICR);\
238 icr &= ~irq_mask;\
239 outb(icr, EWRK3_ICR)
240
241
242
243
244 #define START_EWRK3 \
245 csr = inb(EWRK3_CSR);\
246 csr &= ~(TXD|RXD);\
247 outb(csr, EWRK3_CSR)
248
249 #define STOP_EWRK3 \
250 csr = (TXD|RXD);\
251 outb(csr, EWRK3_CSR)
252
253
254
255
256 #define EWRK3_PKT_STAT_SZ 16
257 #define EWRK3_PKT_BIN_SZ 128
258
259
260 struct ewrk3_private {
261 long shmem_base;
262 long shmem_length;
263 struct enet_statistics stats;
264 struct {
265 unsigned long bins[EWRK3_PKT_STAT_SZ];
266 unsigned long unicast;
267 unsigned long multicast;
268 unsigned long broadcast;
269 unsigned long excessive_collisions;
270 unsigned long tx_underruns;
271 unsigned long excessive_underruns;
272 } pktStats;
273 short mPage;
274 unsigned char lemac;
275 unsigned char hard_strapped;
276 unsigned char lock;
277 unsigned char txc;
278 };
279
280
281
282
283 #define FORCE_2K_MODE \
284 shmem_length = SHMEM_2K;\
285 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
286
287
288
289
290 static int ewrk3_open(struct device *dev);
291 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
292 static void ewrk3_interrupt(int reg_ptr);
293 static int ewrk3_close(struct device *dev);
294 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
295 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
296 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
297
298
299
300
301 static int ewrk3_hw_init(struct device *dev, short iobase);
302 static void ewrk3_init(struct device *dev);
303 static int ewrk3_rx(struct device *dev);
304 static int ewrk3_tx(struct device *dev);
305
306 static void EthwrkSignature(char * name, char *eeprom_image);
307 static int DevicePresent(short iobase);
308 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
309
310 static int Read_EEPROM(short iobase, unsigned char eaddr);
311 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
312 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
313
314 #ifndef MODULE
315 static struct device *isa_probe(struct device *dev);
316 static struct device *eisa_probe(struct device *dev);
317 static struct device *alloc_device(struct device *dev, int iobase);
318
319 static int num_ewrk3s = 0, num_eth = 0;
320 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
321
322 #else
323 int init_module(void);
324 void cleanup_module(void);
325
326 #endif
327
328 static int autoprobed = 0;
329
330
331
332
333 #define INIT_EWRK3 {\
334 int i;\
335 outb(EEPROM_INIT, EWRK3_IOPR);\
336 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
337 }
338
339
340
341
342 int ewrk3_probe(struct device *dev)
343 {
344 int base_addr = dev->base_addr;
345 int status = -ENODEV;
346 #ifndef MODULE
347 struct device *eth0;
348 #endif
349
350 if (base_addr > 0x0ff) {
351 if (!autoprobed) {
352 if (!check_region(base_addr, EWRK3_IOP_INC)) {
353 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
354 if (DevicePresent(base_addr) == 0) {
355 request_region(base_addr, EWRK3_IOP_INC,"ewrk3");
356 status = ewrk3_hw_init(dev, base_addr);
357 } else {
358 printk("ewrk3_probe(): No device found\n");
359 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
360 }
361 }
362 } else {
363 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
364 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
365 }
366 } else {
367 status = ewrk3_hw_init(dev, base_addr);
368 }
369 } else if (base_addr > 0) {
370 status = -ENXIO;
371
372 #ifdef MODULE
373 } else {
374 printk("Autoprobing is not supported when loading a module based driver.\n");
375 status = -EIO;
376 #else
377 } else if (!autoprobed) {
378
379 eth0=isa_probe(dev);
380 eth0=eisa_probe(eth0);
381 if (dev->priv) status=0;
382 autoprobed = 1;
383 } else {
384 status = -ENXIO;
385 #endif
386
387 }
388
389 if (status) dev->base_addr = base_addr;
390
391 return status;
392 }
393
394 static int
395 ewrk3_hw_init(struct device *dev, short iobase)
396 {
397 struct ewrk3_private *lp;
398 int i, status=0;
399 unsigned long mem_start, shmem_length;
400 char name[EWRK3_NAME_LENGTH + 1];
401 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
402 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
403
404
405
406
407
408 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
409 INIT_EWRK3;
410
411 nicsr = inb(EWRK3_CSR);
412
413
414
415
416 DISABLE_IRQs;
417
418 if (nicsr == TXD|RXD) {
419
420
421
422
423 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
424 union {
425 short val;
426 char c[2];
427 } tmp;
428
429 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
430 eeprom_image[i] = tmp.c[0];
431 eeprom_image[i+1] = tmp.c[1];
432
433 chksum += eeprom_image[i] + eeprom_image[i+1];
434 }
435
436 if (chksum != 0) {
437 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
438 status = -ENXIO;
439 } else {
440
441
442
443 EthwrkSignature(name, eeprom_image);
444
445 if (*name != '\0') {
446 dev->base_addr = iobase;
447
448 if (iobase > 0x400) {
449 outb(eisa_cr, EISA_CR);
450 }
451
452 lemac = eeprom_image[EEPROM_CHIPVER];
453 cmr = inb(EWRK3_CMR);
454
455 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
456 ((lemac == LeMAC2) && !(cmr & HS))) {
457 printk("%s: %s at %#3x", dev->name, name, iobase);
458 hard_strapped = 1;
459 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
460
461 printk("%s: %s at %#3x (EISA slot %d)",
462 dev->name, name, iobase, ((iobase>>12)&0x0f));
463 } else {
464 printk("%s: %s at %#3x", dev->name, name, iobase);
465 }
466
467 if (!status) {
468 printk(", h/w address ");
469 if (lemac == LeMAC2) {
470 for (i = 0;i < ETH_ALEN - 1;i++) {
471 printk("%2.2x:", dev->dev_addr[i] =
472 eeprom_image[EEPROM_PADDR0 + i]);
473 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
474 }
475 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
476 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
477 } else {
478 DevicePresent(iobase);
479 for (i = 0; i < ETH_ALEN - 1; i++) {
480 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
481 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
482 }
483 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
484 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
485 }
486
487 if (aprom_crc(dev, eeprom_image, lemac)) {
488 printk(" which has an EEPROM CRC error.\n");
489 status = -ENXIO;
490 } else {
491 if (lemac == LeMAC2) {
492 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
493 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
494 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
495 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
496 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
497 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
498 }
499 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
500 outb(cmr, EWRK3_CMR);
501
502 cr = inb(EWRK3_CR);
503 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
504 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
505 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
506 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
507 outb(cr, EWRK3_CR);
508
509
510
511
512
513 mem_start = inb(EWRK3_MBR);
514 shmem_length = 0;
515 if (mem_start != 0) {
516 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
517 mem_start *= SHMEM_64K;
518 shmem_length = SHMEM_64K;
519 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
520 mem_start *= SHMEM_32K;
521 shmem_length = SHMEM_32K;
522 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
523 mem_start = mem_start * SHMEM_2K + 0x80000;
524 shmem_length = SHMEM_2K;
525 } else {
526 status = -ENXIO;
527 }
528 }
529
530
531
532
533
534
535
536 if (!status) {
537 if (hard_strapped) {
538 printk(" is hard strapped.\n");
539 } else if (mem_start) {
540 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
541 printk(" at 0x%.5lx", mem_start);
542 } else {
543 printk(" is in I/O only mode");
544 }
545
546
547 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
548 GFP_KERNEL);
549 lp = (struct ewrk3_private *)dev->priv;
550 memset(dev->priv, 0, sizeof(struct ewrk3_private));
551 lp->shmem_base = mem_start;
552 lp->shmem_length = shmem_length;
553 lp->lemac = lemac;
554 lp->hard_strapped = hard_strapped;
555
556 lp->mPage = 64;
557 if (cmr & DRAM) lp->mPage <<= 1 ;
558
559 if (!hard_strapped) {
560
561
562
563 icr |= IE;
564 outb(icr, EWRK3_ICR);
565
566
567 dev->dma = 0;
568
569
570
571 if (dev->irq < 2) {
572 #ifndef MODULE
573 unsigned char irqnum;
574
575 autoirq_setup(0);
576
577
578
579
580 icr |=TNEM;
581 outb(1,EWRK3_TDQ);
582 outb(icr, EWRK3_ICR);
583
584 irqnum = irq[((icr & IRQ_SEL) >> 4)];
585
586 dev->irq = autoirq_report(1);
587 if ((dev->irq) && (irqnum == dev->irq)) {
588 printk(" and uses IRQ%d.\n", dev->irq);
589 } else {
590 if (!dev->irq) {
591 printk(" and failed to detect IRQ line.\n");
592 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
593 printk(" and an illegal IRQ line detected.\n");
594 } else {
595 printk(", but incorrect IRQ line detected.\n");
596 }
597 status = -ENXIO;
598 }
599
600 DISABLE_IRQs;
601
602 #endif
603 } else {
604 printk(" and requires IRQ%d.\n", dev->irq);
605 }
606 }
607 } else {
608 status = -ENXIO;
609 }
610 }
611 }
612 } else {
613 status = -ENXIO;
614 }
615 }
616
617 if (!status) {
618 if (ewrk3_debug > 0) {
619 printk(version);
620 }
621
622
623 dev->open = &ewrk3_open;
624 dev->hard_start_xmit = &ewrk3_queue_pkt;
625 dev->stop = &ewrk3_close;
626 dev->get_stats = &ewrk3_get_stats;
627 #ifdef HAVE_MULTICAST
628 dev->set_multicast_list = &set_multicast_list;
629 #endif
630 dev->do_ioctl = &ewrk3_ioctl;
631
632 dev->mem_start = 0;
633
634
635 ether_setup(dev);
636 }
637 } else {
638 status = -ENXIO;
639 }
640
641 return status;
642 }
643
644
645 static int
646 ewrk3_open(struct device *dev)
647 {
648 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
649 int i, iobase = dev->base_addr;
650 int status = 0;
651 unsigned char icr, csr;
652
653
654
655
656 STOP_EWRK3;
657
658 if (!lp->hard_strapped) {
659 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
660 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
661 status = -EAGAIN;
662 } else {
663
664 irq2dev_map[dev->irq] = dev;
665
666
667
668
669 ewrk3_init(dev);
670
671 if (ewrk3_debug > 1){
672 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
673 printk("\tphysical address: ");
674 for (i=0;i<6;i++){
675 printk("%2.2x:",(short)dev->dev_addr[i]);
676 }
677 printk("\n");
678 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
679 if (lp->shmem_length == 0) {
680 printk("\tno shared memory, I/O only mode\n");
681 } else {
682 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
683 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
684 }
685 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
686 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
687 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
688 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
689 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
690 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
691 }
692
693 dev->tbusy = 0;
694 dev->start = 1;
695 dev->interrupt = UNMASK_INTERRUPTS;
696
697
698
699
700 icr = inb(EWRK3_ICR);
701 ENABLE_IRQs;
702
703 }
704 } else {
705 dev->start = 0;
706 dev->tbusy = 1;
707 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
708 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
709 }
710
711 #ifdef MODULE
712 MOD_INC_USE_COUNT;
713 #endif
714
715
716 return status;
717 }
718
719
720
721
722 static void
723 ewrk3_init(struct device *dev)
724 {
725 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
726 char csr, page;
727 short iobase = dev->base_addr;
728
729
730
731
732 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
733
734
735
736
737 while (inb(EWRK3_TQ));
738 while (inb(EWRK3_TDQ));
739 while (inb(EWRK3_RQ));
740 while (inb(EWRK3_FMQ));
741
742
743
744
745 for (page=1;page<lp->mPage;page++) {
746 outb(page, EWRK3_FMQ);
747 }
748
749 lp->lock = 0;
750
751 START_EWRK3;
752 }
753
754
755
756
757 static int
758 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
759 {
760 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
761 int iobase = dev->base_addr;
762 int status = 0;
763 unsigned char icr, csr;
764
765
766 if (dev->tbusy || lp->lock) {
767 int tickssofar = jiffies - dev->trans_start;
768 if (tickssofar < 10) {
769 status = -1;
770 } else if (!lp->hard_strapped) {
771 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
772 dev->name, inb(EWRK3_CSR));
773
774
775
776
777 DISABLE_IRQs;
778
779
780
781
782 STOP_EWRK3;
783
784 ewrk3_init(dev);
785
786
787
788
789 ENABLE_IRQs;
790
791 dev->tbusy=0;
792 dev->trans_start = jiffies;
793 }
794 } else if (skb == NULL) {
795 dev_tint(dev);
796 } else if (skb->len > 0) {
797
798
799
800
801
802 if (set_bit(0, (void*)&dev->tbusy) != 0)
803 printk("%s: Transmitter access conflict.\n", dev->name);
804
805 DISABLE_IRQs;
806
807
808
809
810 if (inb(EWRK3_FMQC) > 0) {
811 unsigned char *buf;
812 unsigned char page;
813
814 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
815 buf = NULL;
816
817
818
819
820 while (set_bit(0, (void *)&lp->lock) != 0);
821 if (lp->shmem_length == IO_ONLY) {
822 outb(page, EWRK3_IOPR);
823 } else if (lp->shmem_length == SHMEM_2K) {
824 buf = (char *) lp->shmem_base;
825 outb(page, EWRK3_MPR);
826 } else if (lp->shmem_length == SHMEM_32K) {
827 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
828 outb((page >> 4), EWRK3_MPR);
829 } else if (lp->shmem_length == SHMEM_64K) {
830 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
831 outb((page >> 5), EWRK3_MPR);
832 } else {
833 status = -1;
834 printk("%s: Oops - your private data area is hosed!\n",dev->name);
835 }
836
837 if (!status) {
838
839
840
841
842
843
844 if (lp->shmem_length == IO_ONLY) {
845 int i;
846 unsigned char *p = skb->data;
847
848 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
849 outb((char)(skb->len & 0xff), EWRK3_DATA);
850 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
851 outb((char)0x04, EWRK3_DATA);
852 for (i=0; i<skb->len; i++) {
853 outb(*p++, EWRK3_DATA);
854 }
855 outb(page, EWRK3_TQ);
856 } else {
857 *buf++ = (char)(QMODE | PAD | IFC);
858 *buf++ = (char)(skb->len & 0xff);
859 if (lp->txc) {
860 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
861 *buf++ = 0x04;
862 *(buf + skb->len) = 0x00;
863 memcpy(buf, skb->data, PRELOAD);
864 outb(page, EWRK3_TQ);
865 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
866 *(buf + skb->len) = 0xff;
867 } else {
868 *buf++ = (char)((skb->len >> 8) & 0xff);
869 *buf++ = 0x04;
870 memcpy(buf, skb->data, skb->len);
871 outb(page, EWRK3_TQ);
872 }
873 }
874
875 dev->trans_start = jiffies;
876
877 dev_kfree_skb (skb, FREE_WRITE);
878
879 } else {
880 outb(page, EWRK3_FMQ);
881 }
882 lp->lock = 0;
883 } else {
884 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
885 (unsigned char) page);
886 }
887 } else {
888 printk("ewrk3_queue_pkt(): No free resources...\n");
889 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
890 }
891
892
893 if (inb(EWRK3_FMQC) > 0) {
894 dev->tbusy = 0;
895 }
896
897 ENABLE_IRQs;
898 }
899
900 return status;
901 }
902
903
904
905
906 static void
907 ewrk3_interrupt(int reg_ptr)
908 {
909 int irq = -(((struct pt_regs *)reg_ptr)->orig_eax+2);
910 struct device *dev = (struct device *)(irq2dev_map[irq]);
911 struct ewrk3_private *lp;
912 int iobase;
913 unsigned char icr, cr, csr;
914
915 if (dev == NULL) {
916 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
917 } else {
918 lp = (struct ewrk3_private *)dev->priv;
919 iobase = dev->base_addr;
920
921 if (dev->interrupt)
922 printk("%s: Re-entering the interrupt handler.\n", dev->name);
923
924 dev->interrupt = MASK_INTERRUPTS;
925
926
927 csr = inb(EWRK3_CSR);
928
929
930
931
932 DISABLE_IRQs;
933
934 cr = inb(EWRK3_CR);
935 cr |= LED;
936 outb(cr, EWRK3_CR);
937
938 if (csr & RNE)
939 ewrk3_rx(dev);
940
941 if (csr & TNE)
942 ewrk3_tx(dev);
943
944
945
946
947
948
949
950 if (inb(EWRK3_FMQC)) {
951 irq_mask |= TXDM|RXDM;
952 csr &= ~(TXD|RXD);
953 outb(csr, EWRK3_CSR);
954 dev->tbusy = 0;
955 mark_bh(NET_BH);
956 } else {
957 irq_mask &= ~(TXDM|RXDM);
958 }
959
960
961 cr &= ~LED;
962 outb(cr, EWRK3_CR);
963
964 dev->interrupt = UNMASK_INTERRUPTS;
965
966 ENABLE_IRQs;
967 }
968
969 return;
970 }
971
972 static int
973 ewrk3_rx(struct device *dev)
974 {
975 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
976 int i, iobase = dev->base_addr;
977 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
978 int status = 0;
979
980 while (inb(EWRK3_RQC) && !status) {
981 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
982 buf = NULL;
983
984
985
986
987
988 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
989 if (lp->shmem_length == IO_ONLY) {
990 tmpPage = inb(EWRK3_IOPR);
991 } else {
992 tmpPage = inb(EWRK3_MPR);
993 }
994 }
995
996
997
998
999 if (lp->shmem_length == IO_ONLY) {
1000 outb(page, EWRK3_IOPR);
1001 } else if (lp->shmem_length == SHMEM_2K) {
1002 buf = (char *) lp->shmem_base;
1003 outb(page, EWRK3_MPR);
1004 } else if (lp->shmem_length == SHMEM_32K) {
1005 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1006 outb((page >> 4), EWRK3_MPR);
1007 } else if (lp->shmem_length == SHMEM_64K) {
1008 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1009 outb((page >> 5), EWRK3_MPR);
1010 } else {
1011 status = -1;
1012 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1013 }
1014
1015 if (!status) {
1016 char rx_status;
1017 int pkt_len;
1018
1019 if (lp->shmem_length == IO_ONLY) {
1020 rx_status = inb(EWRK3_DATA);
1021 pkt_len = inb(EWRK3_DATA);
1022 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1023 } else {
1024 rx_status = (char)(*buf++);
1025 pkt_len = (short)(*buf+((*(buf+1))<<8));
1026 buf+=3;
1027 }
1028
1029 if (!(rx_status & ROK)) {
1030 lp->stats.rx_errors++;
1031 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1032 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1033 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1034 } else {
1035 struct sk_buff *skb;
1036
1037 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1038 skb->len = pkt_len;
1039 skb->dev = dev;
1040
1041 if (lp->shmem_length == IO_ONLY) {
1042 unsigned char *p = skb->data;
1043
1044 *p = inb(EWRK3_DATA);
1045 for (i=0; i<skb->len; i++) {
1046 *p++ = inb(EWRK3_DATA);
1047 }
1048 } else {
1049 memcpy(skb->data, buf, pkt_len);
1050 }
1051
1052
1053
1054
1055
1056 netif_rx(skb);
1057
1058
1059
1060
1061 lp->stats.rx_packets++;
1062 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1063 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1064 lp->pktStats.bins[i]++;
1065 i = EWRK3_PKT_STAT_SZ;
1066 }
1067 }
1068 buf = skb->data;
1069 if (buf[0] & 0x01) {
1070 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1071 lp->pktStats.broadcast++;
1072 } else {
1073 lp->pktStats.multicast++;
1074 }
1075 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1076 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1077 lp->pktStats.unicast++;
1078 }
1079
1080 lp->pktStats.bins[0]++;
1081 if (lp->pktStats.bins[0] == 0) {
1082 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1083 }
1084 } else {
1085 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1086 lp->stats.rx_dropped++;
1087 break;
1088 }
1089 }
1090 }
1091
1092
1093
1094 outb(page, EWRK3_FMQ);
1095
1096 if (tmpLock) {
1097 if (lp->shmem_length == IO_ONLY) {
1098 outb(tmpPage, EWRK3_IOPR);
1099 } else {
1100 outb(tmpPage, EWRK3_MPR);
1101 }
1102 }
1103 lp->lock = 0;
1104 } else {
1105 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1106 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1107 }
1108 }
1109 return status;
1110 }
1111
1112
1113
1114
1115 static int
1116 ewrk3_tx(struct device *dev)
1117 {
1118 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1119 int iobase = dev->base_addr;
1120 unsigned char tx_status;
1121
1122 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1123 if (tx_status & VSTS) {
1124 if (tx_status & MAC_TXE) {
1125 lp->stats.tx_errors++;
1126 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1127 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1128 if (tx_status & MAC_CTU) {
1129 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1130 lp->pktStats.tx_underruns++;
1131 } else {
1132 lp->pktStats.excessive_underruns++;
1133 }
1134 } else if (tx_status & MAC_COLL) {
1135 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1136 lp->stats.collisions++;
1137 } else {
1138 lp->pktStats.excessive_collisions++;
1139 }
1140 }
1141 } else {
1142 lp->stats.tx_packets++;
1143 }
1144 }
1145 }
1146
1147 return 0;
1148 }
1149
1150 static int
1151 ewrk3_close(struct device *dev)
1152 {
1153 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1154 int iobase = dev->base_addr;
1155 unsigned char icr, csr;
1156
1157 dev->start = 0;
1158 dev->tbusy = 1;
1159
1160 if (ewrk3_debug > 1) {
1161 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1162 dev->name, inb(EWRK3_CSR));
1163 }
1164
1165
1166
1167
1168 DISABLE_IRQs;
1169
1170 STOP_EWRK3;
1171
1172
1173
1174
1175
1176
1177
1178 while (inb(EWRK3_TQ));
1179 while (inb(EWRK3_TDQ));
1180 while (inb(EWRK3_RQ));
1181
1182 if (!lp->hard_strapped) {
1183 free_irq(dev->irq);
1184
1185 irq2dev_map[dev->irq] = 0;
1186 }
1187
1188 #ifdef MODULE
1189 MOD_DEC_USE_COUNT;
1190 #endif
1191
1192 return 0;
1193 }
1194
1195 static struct enet_statistics *
1196 ewrk3_get_stats(struct device *dev)
1197 {
1198 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1199
1200
1201
1202 return &lp->stats;
1203 }
1204
1205
1206
1207
1208
1209
1210
1211
1212 static void
1213 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1214 {
1215 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1216 int iobase = dev->base_addr;
1217 char *multicast_table;
1218 unsigned char csr;
1219
1220 csr = inb(EWRK3_CSR);
1221
1222 if (lp->shmem_length == IO_ONLY) {
1223 multicast_table = (char *) PAGE0_HTE;
1224 } else {
1225 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1226 }
1227
1228 if (num_addrs >= 0) {
1229 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1230 csr &= ~PME;
1231 csr |= MCE;
1232 outb(csr, EWRK3_CSR);
1233 } else {
1234 csr |= PME;
1235 csr &= ~MCE;
1236 outb(csr, EWRK3_CSR);
1237 }
1238 }
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1249 {
1250 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1251 int iobase = dev->base_addr;
1252 char j, ctrl, bit, octet;
1253 short *p = (short *) multicast_table;
1254 unsigned short hashcode;
1255 int i;
1256 long int crc, poly = (long int) CRC_POLYNOMIAL;
1257
1258 while (set_bit(0, (void *)&lp->lock) != 0);
1259
1260 if (lp->shmem_length == IO_ONLY) {
1261 outb(0, EWRK3_IOPR);
1262 outw((short)((long)multicast_table), EWRK3_PIR1);
1263 } else {
1264 outb(0, EWRK3_MPR);
1265 }
1266
1267 if (num_addrs == HASH_TABLE_LEN) {
1268 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1269 if (lp->shmem_length == IO_ONLY) {
1270 outb(0xff, EWRK3_DATA);
1271 } else {
1272 *p++ = 0xffff;
1273 i++;
1274 }
1275 }
1276 } else if (num_addrs == 0) {
1277 if (lp->shmem_length == IO_ONLY) {
1278 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1279 outb(0x00, EWRK3_DATA);
1280 }
1281 } else {
1282 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1283 }
1284 } else {
1285 for (i=0;i<num_addrs;i++) {
1286 if (((char) *(addrs+ETH_ALEN*i) & 0x01) == 1) {
1287 crc = (long int) 0xffffffff;
1288 for (octet=0;octet<ETH_ALEN;octet++) {
1289 for(j=0;j<8;j++) {
1290 bit = (((char)* (addrs+ETH_ALEN*i+octet)) >> j) & 0x01;
1291 ctrl = ((crc < 0) ? 1 : 0);
1292 crc <<= 1;
1293 if (bit ^ ctrl) {
1294 crc ^= poly;
1295 }
1296 }
1297 }
1298 hashcode = ((crc >>= 23) & 0x01);
1299 for (j=0;j<8;j++) {
1300 hashcode <<= 1;
1301 crc >>= 1;
1302 hashcode |= (crc & 0x01);
1303 }
1304
1305 octet = hashcode >> 3;
1306
1307 if (lp->shmem_length == IO_ONLY) {
1308 unsigned char tmp;
1309
1310 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1311 tmp = inb(EWRK3_DATA);
1312 tmp |= (1 << (hashcode & 0x07));
1313 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1314 outb(tmp, EWRK3_DATA);
1315 } else {
1316 multicast_table[octet] |= (1 << (hashcode & 0x07));
1317 }
1318 }
1319 }
1320 }
1321
1322 lp->lock = 0;
1323
1324 return;
1325 }
1326
1327 #ifndef MODULE
1328
1329
1330
1331 static struct device *isa_probe(struct device *dev)
1332 {
1333 int i, iobase, status;
1334 unsigned long int tmp = mem_chkd;
1335
1336 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1337 i < 24;
1338 iobase += EWRK3_IOP_INC, i++) {
1339 if (tmp & 0x01) {
1340
1341 if (!check_region(iobase, EWRK3_IOP_INC)) {
1342 if (DevicePresent(iobase) == 0) {
1343
1344
1345
1346
1347 request_region(iobase, EWRK3_IOP_INC,"ewrk3");
1348 if (num_ewrk3s > 0) {
1349 dev = alloc_device(dev, iobase);
1350 } else {
1351 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1352 num_ewrk3s++;
1353 }
1354 }
1355 num_eth++;
1356 } else {
1357 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1358 }
1359 } else {
1360 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1361 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1362 }
1363 }
1364 tmp >>= 1;
1365 }
1366
1367 return dev;
1368 }
1369
1370
1371
1372
1373
1374 static struct device *eisa_probe(struct device *dev)
1375 {
1376 int i, iobase = EWRK3_EISA_IO_PORTS;
1377 int status;
1378
1379 iobase+=EISA_SLOT_INC;
1380 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1381
1382
1383 if (!check_region(iobase, EWRK3_IOP_INC)) {
1384 if (DevicePresent(iobase) == 0) {
1385
1386
1387
1388
1389 mem_chkd |= (0x01 << (i + 24));
1390 request_region(iobase, EWRK3_IOP_INC,"ewrk3");
1391 if (num_ewrk3s > 0) {
1392 dev = alloc_device(dev, iobase);
1393 } else {
1394 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1395 num_ewrk3s++;
1396 }
1397 }
1398 num_eth++;
1399 }
1400 }
1401 }
1402 return dev;
1403 }
1404
1405
1406
1407
1408
1409 static struct device *alloc_device(struct device *dev, int iobase)
1410 {
1411
1412
1413
1414 while (dev->next != NULL) {
1415 if (dev->next->base_addr == 0xffe0) break;
1416 dev = dev->next;
1417 num_eth++;
1418 }
1419
1420
1421
1422
1423
1424 if (dev->next == NULL) {
1425 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1426 GFP_KERNEL);
1427 if (dev->next == NULL) {
1428 printk("eth%d: Device not initialised, insufficient memory\n",
1429 num_eth);
1430 }
1431 }
1432
1433
1434
1435
1436
1437
1438 if ((dev->next != NULL) &&
1439 (num_eth > 0) && (num_eth < 9999)) {
1440 dev = dev->next;
1441 dev->name = (char *)(dev + sizeof(struct device));
1442 sprintf(dev->name,"eth%d", num_eth);
1443 dev->base_addr = iobase;
1444 dev->next = NULL;
1445 dev->init = &ewrk3_probe;
1446 num_ewrk3s++;
1447 }
1448
1449 return dev;
1450 }
1451 #endif
1452
1453
1454
1455
1456 static int Read_EEPROM(short iobase, unsigned char eaddr)
1457 {
1458 int i;
1459
1460 outb((eaddr & 0x3f), EWRK3_PIR1);
1461 outb(EEPROM_RD, EWRK3_IOPR);
1462 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1463
1464 return inw(EWRK3_EPROM1);
1465 }
1466
1467
1468
1469
1470 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1471 {
1472 int i;
1473
1474 outb(EEPROM_WR_EN, EWRK3_IOPR);
1475 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1476 outw(data, EWRK3_EPROM1);
1477 outb((eaddr & 0x3f), EWRK3_PIR1);
1478 outb(EEPROM_WR, EWRK3_IOPR);
1479 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1480 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1481 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1482
1483 return 0;
1484 }
1485
1486
1487
1488
1489 static void EthwrkSignature(char *name, char *eeprom_image)
1490 {
1491 unsigned long i,j,k;
1492 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1493
1494 strcpy(name, "");
1495 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1496 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1497 if (signatures[i][k] == eeprom_image[j]) {
1498 k++;
1499 } else {
1500 k=0;
1501 }
1502 }
1503 if (k == strlen(signatures[i])) {
1504 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1505 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1506 name[EWRK3_NAME_LENGTH] = '\0';
1507 }
1508 }
1509 }
1510
1511 return;
1512 }
1513
1514
1515
1516
1517
1518
1519 static int DevicePresent(short iobase)
1520 {
1521 static short fp=1,sigLength=0;
1522 static char devSig[] = PROBE_SEQUENCE;
1523 char data;
1524 int i, j, status = 0;
1525 static char asc2hex(char value);
1526
1527
1528
1529
1530 if (fp) {
1531 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1532 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1533 devSig[i]<<=4;
1534 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1535 devSig[j]=devSig[i]+devSig[i+1];
1536 } else {
1537 status= -1;
1538 }
1539 } else {
1540 status= -1;
1541 }
1542 }
1543 sigLength=j;
1544 fp = 0;
1545 }
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555 if (!status) {
1556 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1557 data = inb(EWRK3_APROM);
1558 if (devSig[j] == data) {
1559 j++;
1560 } else {
1561 j=0;
1562 }
1563 }
1564
1565 if (j!=sigLength) {
1566 status = -ENODEV;
1567 }
1568 }
1569
1570 return status;
1571 }
1572
1573 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1574 {
1575 long k;
1576 unsigned short j,chksum;
1577 unsigned char crc, lfsr, sd, status = 0;
1578 int iobase = dev->base_addr;
1579
1580 if (chipType == LeMAC2) {
1581 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1582 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1583 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1584 crc = (crc >> 1) + lfsr;
1585 }
1586 }
1587 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1588 } else {
1589 for (k=0,j=0;j<3;j++) {
1590 k <<= 1 ;
1591 if (k > 0xffff) k-=0xffff;
1592 k += inw(EWRK3_PAR0 + (j<<1));
1593 if (k > 0xffff) k-=0xffff;
1594 }
1595 if (k == 0xffff) k=0;
1596 chksum = inb(EWRK3_APROM);
1597 chksum |= (inb(EWRK3_APROM)<<8);
1598 if (k != chksum) status = -1;
1599 }
1600
1601 return status;
1602 }
1603
1604
1605
1606
1607
1608 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1609 {
1610 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1611 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1612 int i, j, iobase = dev->base_addr, status = 0;
1613 unsigned char csr;
1614 union {
1615 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1616 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1617 } tmp;
1618
1619 switch(ioc->cmd) {
1620 case EWRK3_GET_HWADDR:
1621 for (i=0; i<ETH_ALEN; i++) {
1622 tmp.addr[i] = dev->dev_addr[i];
1623 }
1624 ioc->len = ETH_ALEN;
1625 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1626
1627 break;
1628 case EWRK3_SET_HWADDR:
1629 if (suser()) {
1630 csr = inb(EWRK3_CSR);
1631 csr |= (TXD|RXD);
1632 outb(csr, EWRK3_CSR);
1633
1634 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1635 for (i=0; i<ETH_ALEN; i++) {
1636 dev->dev_addr[i] = tmp.addr[i];
1637 outb(tmp.addr[i], EWRK3_PAR0 + i);
1638 }
1639
1640 csr &= ~(TXD|RXD);
1641 outb(csr, EWRK3_CSR);
1642 } else {
1643 status = -EPERM;
1644 }
1645
1646 break;
1647 case EWRK3_SET_PROM:
1648 if (suser()) {
1649 csr = inb(EWRK3_CSR);
1650 csr |= PME;
1651 csr &= ~MCE;
1652 outb(csr, EWRK3_CSR);
1653 } else {
1654 status = -EPERM;
1655 }
1656
1657 break;
1658 case EWRK3_CLR_PROM:
1659 if (suser()) {
1660 csr = inb(EWRK3_CSR);
1661 csr &= ~PME;
1662 outb(csr, EWRK3_CSR);
1663 } else {
1664 status = -EPERM;
1665 }
1666
1667 break;
1668 case EWRK3_SAY_BOO:
1669 printk("%s: Boo!\n", dev->name);
1670
1671 break;
1672 case EWRK3_GET_MCA:
1673 while (set_bit(0, (void *)&lp->lock) != 0);
1674 if (lp->shmem_length == IO_ONLY) {
1675 outb(0, EWRK3_IOPR);
1676 outw(PAGE0_HTE, EWRK3_PIR1);
1677 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1678 tmp.addr[i] = inb(EWRK3_DATA);
1679 }
1680 } else {
1681 outb(0, EWRK3_MPR);
1682 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1683 }
1684 ioc->len = (HASH_TABLE_LEN >> 3);
1685 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1686 lp->lock = 0;
1687
1688 break;
1689 case EWRK3_SET_MCA:
1690 if (suser()) {
1691 if (ioc->len != HASH_TABLE_LEN) {
1692 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1693 }
1694 set_multicast_list(dev, ioc->len, tmp.addr);
1695 } else {
1696 status = -EPERM;
1697 }
1698
1699 break;
1700 case EWRK3_CLR_MCA:
1701 if (suser()) {
1702 set_multicast_list(dev, 0, NULL);
1703 } else {
1704 status = -EPERM;
1705 }
1706
1707 break;
1708 case EWRK3_MCA_EN:
1709 if (suser()) {
1710 csr = inb(EWRK3_CSR);
1711 csr |= MCE;
1712 csr &= ~PME;
1713 outb(csr, EWRK3_CSR);
1714 } else {
1715 status = -EPERM;
1716 }
1717
1718 break;
1719 case EWRK3_GET_STATS:
1720 cli();
1721 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1722 ioc->len = EWRK3_PKT_STAT_SZ;
1723 sti();
1724
1725 break;
1726 case EWRK3_CLR_STATS:
1727 if (suser()) {
1728 cli();
1729 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1730 sti();
1731 } else {
1732 status = -EPERM;
1733 }
1734
1735 break;
1736 case EWRK3_GET_CSR:
1737 tmp.addr[0] = inb(EWRK3_CSR);
1738 memcpy_tofs(ioc->data, tmp.addr, 1);
1739
1740 break;
1741 case EWRK3_SET_CSR:
1742 if (suser()) {
1743 memcpy_fromfs(tmp.addr, ioc->data, 1);
1744 outb(tmp.addr[0], EWRK3_CSR);
1745 } else {
1746 status = -EPERM;
1747 }
1748
1749 break;
1750 case EWRK3_GET_EEPROM:
1751 if (suser()) {
1752 for (i=0; i<(EEPROM_MAX>>1); i++) {
1753 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1754 }
1755 i = EEPROM_MAX;
1756 tmp.addr[i++] = inb(EWRK3_CMR);
1757 for (j=0;j<ETH_ALEN;j++) {
1758 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1759 }
1760 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1761 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1762 } else {
1763 status = -EPERM;
1764 }
1765
1766 break;
1767 case EWRK3_SET_EEPROM:
1768 if (suser()) {
1769 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1770 for (i=0; i<(EEPROM_MAX>>1); i++) {
1771 Write_EEPROM(tmp.val[i], iobase, i);
1772 }
1773 } else {
1774 status = -EPERM;
1775 }
1776
1777 break;
1778 case EWRK3_GET_CMR:
1779 tmp.addr[0] = inb(EWRK3_CMR);
1780 memcpy_tofs(ioc->data, tmp.addr, 1);
1781
1782 break;
1783 case EWRK3_SET_TX_CUT_THRU:
1784 if (suser()) {
1785 lp->txc = 1;
1786 } else {
1787 status = -EPERM;
1788 }
1789
1790 break;
1791 case EWRK3_CLR_TX_CUT_THRU:
1792 if (suser()) {
1793 lp->txc = 0;
1794 } else {
1795 status = -EPERM;
1796 }
1797
1798 break;
1799 default:
1800 status = -EOPNOTSUPP;
1801 }
1802
1803 return status;
1804 }
1805
1806 static char asc2hex(char value)
1807 {
1808 value -= 0x30;
1809 if (value >= 0) {
1810 if (value > 9) {
1811 value &= 0x1f;
1812 value -= 0x07;
1813 if ((value < 0x0a) || (value > 0x0f)) {
1814 value = -1;
1815 }
1816 }
1817 } else {
1818 value = -1;
1819 }
1820 return value;
1821 }
1822
1823 #ifdef MODULE
1824 char kernel_version[] = UTS_RELEASE;
1825 static struct device thisEthwrk = {
1826 " ",
1827 0, 0, 0, 0,
1828 0x300, 5,
1829 0, 0, 0, NULL, ewrk3_probe };
1830
1831
1832 int io=0x300;
1833 int irq=5;
1834
1835 int
1836 init_module(void)
1837 {
1838 thisEthwrk.base_addr=io;
1839 thisEthwrk.irq=irq;
1840 if (register_netdev(&thisEthwrk) != 0)
1841 return -EIO;
1842 return 0;
1843 }
1844
1845 void
1846 cleanup_module(void)
1847 {
1848 if (MOD_IN_USE) {
1849 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1850 } else {
1851 unregister_netdev(&thisEthwrk);
1852 }
1853 }
1854 #endif
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866