This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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128 static char *version = "ewrk3.c:v0.31 12/5/94 davies@wanton.lkg.dec.com\n";
129
130 #include <stdarg.h>
131 #include <linux/kernel.h>
132 #include <linux/sched.h>
133 #include <linux/string.h>
134 #include <linux/ptrace.h>
135 #include <linux/errno.h>
136 #include <linux/ioport.h>
137 #include <linux/malloc.h>
138 #include <linux/interrupt.h>
139 #include <asm/bitops.h>
140 #include <asm/io.h>
141 #include <asm/dma.h>
142 #include <asm/segment.h>
143
144 #include <linux/netdevice.h>
145 #include <linux/etherdevice.h>
146 #include <linux/skbuff.h>
147
148 #include <linux/time.h>
149 #include <linux/types.h>
150 #include <linux/unistd.h>
151
152 #ifdef MODULE
153 #include <linux/module.h>
154 #include <linux/version.h>
155 #endif
156
157 #include "ewrk3.h"
158
159 #ifdef EWRK3_DEBUG
160 static int ewrk3_debug = EWRK3_DEBUG;
161 #else
162 static int ewrk3_debug = 1;
163 #endif
164
165 #ifndef PROBE_LENGTH
166 #define PROBE_LENGTH 32
167 #endif
168
169 #ifndef PROBE_SEQUENCE
170 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
171 #endif
172
173 #ifndef EWRK3_SIGNATURE
174 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
175 #define EWRK3_NAME_LENGTH 8
176 #endif
177
178 #ifndef EWRK3_RAM_BASE_ADDRESSES
179 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
180 #endif
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196 #define EWRK3_IO_BASE 0x100
197 #define EWRK3_IOP_INC 0x20
198 #define EWRK3_IO_SEARCH 0x007dff7f
199 static long mem_chkd = EWRK3_IO_SEARCH;
200
201
202 #ifndef MAX_NUM_EWRK3S
203 #define MAX_NUM_EWRK3S 21
204 #endif
205
206 #ifndef EWRK3_EISA_IO_PORTS
207 #define EWRK3_EISA_IO_PORTS 0x0c00
208 #endif
209
210 #ifndef MAX_EISA_SLOTS
211 #define MAX_EISA_SLOTS 8
212 #define EISA_SLOT_INC 0x1000
213 #endif
214
215 #ifndef CRC_POLYNOMIAL
216 #define CRC_POLYNOMIAL 0x04c11db7
217 #endif
218
219
220
221
222 #define IO_ONLY 0x00
223 #define SHMEM_2K 0x800
224 #define SHMEM_32K 0x8000
225 #define SHMEM_64K 0x10000
226
227
228
229
230 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
231
232 #define ENABLE_IRQs \
233 icr |= irq_mask;\
234 outb(icr, EWRK3_ICR)
235
236 #define DISABLE_IRQs \
237 icr = inb(EWRK3_ICR);\
238 icr &= ~irq_mask;\
239 outb(icr, EWRK3_ICR)
240
241
242
243
244 #define START_EWRK3 \
245 csr = inb(EWRK3_CSR);\
246 csr &= ~(TXD|RXD);\
247 outb(csr, EWRK3_CSR)
248
249 #define STOP_EWRK3 \
250 csr = (TXD|RXD);\
251 outb(csr, EWRK3_CSR)
252
253
254
255
256 #define EWRK3_PKT_STAT_SZ 16
257 #define EWRK3_PKT_BIN_SZ 128
258
259
260 struct ewrk3_private {
261 long shmem_base;
262 long shmem_length;
263 struct enet_statistics stats;
264 struct {
265 unsigned long bins[EWRK3_PKT_STAT_SZ];
266 unsigned long unicast;
267 unsigned long multicast;
268 unsigned long broadcast;
269 unsigned long excessive_collisions;
270 unsigned long tx_underruns;
271 unsigned long excessive_underruns;
272 } pktStats;
273 short mPage;
274 unsigned char lemac;
275 unsigned char hard_strapped;
276 unsigned char lock;
277 unsigned char txc;
278 };
279
280
281
282
283 #define FORCE_2K_MODE \
284 shmem_length = SHMEM_2K;\
285 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
286
287
288
289
290 static int ewrk3_open(struct device *dev);
291 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
292 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
293 static int ewrk3_close(struct device *dev);
294 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
295 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
296 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
297
298
299
300
301 static int ewrk3_hw_init(struct device *dev, short iobase);
302 static void ewrk3_init(struct device *dev);
303 static int ewrk3_rx(struct device *dev);
304 static int ewrk3_tx(struct device *dev);
305
306 static void EthwrkSignature(char * name, char *eeprom_image);
307 static int DevicePresent(short iobase);
308 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
309
310 static int Read_EEPROM(short iobase, unsigned char eaddr);
311 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
312 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
313
314 #ifndef MODULE
315 static struct device *isa_probe(struct device *dev);
316 static struct device *eisa_probe(struct device *dev);
317 static struct device *alloc_device(struct device *dev, int iobase);
318
319 static int num_ewrk3s = 0, num_eth = 0;
320 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
321
322 #else
323 int init_module(void);
324 void cleanup_module(void);
325
326 #endif
327
328 static int autoprobed = 0;
329
330
331
332
333 #define INIT_EWRK3 {\
334 int i;\
335 outb(EEPROM_INIT, EWRK3_IOPR);\
336 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
337 }
338
339
340
341
342 int ewrk3_probe(struct device *dev)
343 {
344 int base_addr = dev->base_addr;
345 int status = -ENODEV;
346 #ifndef MODULE
347 struct device *eth0;
348 #endif
349
350 if (base_addr > 0x0ff) {
351 if (!autoprobed) {
352 if (!check_region(base_addr, EWRK3_IOP_INC)) {
353 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
354 if (DevicePresent(base_addr) == 0) {
355 request_region(base_addr, EWRK3_IOP_INC,"ewrk3");
356 status = ewrk3_hw_init(dev, base_addr);
357 } else {
358 printk("ewrk3_probe(): No device found\n");
359 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
360 }
361 }
362 } else {
363 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
364 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
365 }
366 } else {
367 status = ewrk3_hw_init(dev, base_addr);
368 }
369 } else if (base_addr > 0) {
370 status = -ENXIO;
371
372 #ifdef MODULE
373 } else {
374 printk("Autoprobing is not supported when loading a module based driver.\n");
375 status = -EIO;
376 #else
377 } else if (!autoprobed) {
378
379 eth0=isa_probe(dev);
380 eth0=eisa_probe(eth0);
381 if (dev->priv) status=0;
382 autoprobed = 1;
383 } else {
384 status = -ENXIO;
385 #endif
386
387 }
388
389 if (status) dev->base_addr = base_addr;
390
391 return status;
392 }
393
394 static int
395 ewrk3_hw_init(struct device *dev, short iobase)
396 {
397 struct ewrk3_private *lp;
398 int i, status=0;
399 unsigned long mem_start, shmem_length;
400 char name[EWRK3_NAME_LENGTH + 1];
401 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
402 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
403
404
405
406
407
408 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
409 INIT_EWRK3;
410
411 nicsr = inb(EWRK3_CSR);
412
413
414
415
416 DISABLE_IRQs;
417
418 if (nicsr == TXD|RXD) {
419
420
421
422
423 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
424 union {
425 short val;
426 char c[2];
427 } tmp;
428
429 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
430 eeprom_image[i] = tmp.c[0];
431 eeprom_image[i+1] = tmp.c[1];
432
433 chksum += eeprom_image[i] + eeprom_image[i+1];
434 }
435
436 if (chksum != 0) {
437 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
438 status = -ENXIO;
439 } else {
440
441
442
443 EthwrkSignature(name, eeprom_image);
444
445 if (*name != '\0') {
446 dev->base_addr = iobase;
447
448 if (iobase > 0x400) {
449 outb(eisa_cr, EISA_CR);
450 }
451
452 lemac = eeprom_image[EEPROM_CHIPVER];
453 cmr = inb(EWRK3_CMR);
454
455 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
456 ((lemac == LeMAC2) && !(cmr & HS))) {
457 printk("%s: %s at %#3x", dev->name, name, iobase);
458 hard_strapped = 1;
459 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
460
461 printk("%s: %s at %#3x (EISA slot %d)",
462 dev->name, name, iobase, ((iobase>>12)&0x0f));
463 } else {
464 printk("%s: %s at %#3x", dev->name, name, iobase);
465 }
466
467 if (!status) {
468 printk(", h/w address ");
469 if (lemac == LeMAC2) {
470 for (i = 0;i < ETH_ALEN - 1;i++) {
471 printk("%2.2x:", dev->dev_addr[i] =
472 eeprom_image[EEPROM_PADDR0 + i]);
473 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
474 }
475 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
476 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
477 } else {
478 DevicePresent(iobase);
479 for (i = 0; i < ETH_ALEN - 1; i++) {
480 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
481 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
482 }
483 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
484 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
485 }
486
487 if (aprom_crc(dev, eeprom_image, lemac)) {
488 printk(" which has an EEPROM CRC error.\n");
489 status = -ENXIO;
490 } else {
491 if (lemac == LeMAC2) {
492 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
493 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
494 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
495 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
496 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
497 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
498 }
499 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
500 outb(cmr, EWRK3_CMR);
501
502 cr = inb(EWRK3_CR);
503 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
504 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
505 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
506 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
507 outb(cr, EWRK3_CR);
508
509
510
511
512
513 mem_start = inb(EWRK3_MBR);
514 shmem_length = 0;
515 if (mem_start != 0) {
516 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
517 mem_start *= SHMEM_64K;
518 shmem_length = SHMEM_64K;
519 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
520 mem_start *= SHMEM_32K;
521 shmem_length = SHMEM_32K;
522 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
523 mem_start = mem_start * SHMEM_2K + 0x80000;
524 shmem_length = SHMEM_2K;
525 } else {
526 status = -ENXIO;
527 }
528 }
529
530
531
532
533
534
535
536 if (!status) {
537 if (hard_strapped) {
538 printk(" is hard strapped.\n");
539 } else if (mem_start) {
540 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
541 printk(" at 0x%.5lx", mem_start);
542 } else {
543 printk(" is in I/O only mode");
544 }
545
546
547 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
548 GFP_KERNEL);
549 lp = (struct ewrk3_private *)dev->priv;
550 memset(dev->priv, 0, sizeof(struct ewrk3_private));
551 lp->shmem_base = mem_start;
552 lp->shmem_length = shmem_length;
553 lp->lemac = lemac;
554 lp->hard_strapped = hard_strapped;
555
556 lp->mPage = 64;
557 if (cmr & DRAM) lp->mPage <<= 1 ;
558
559 if (!hard_strapped) {
560
561
562
563 icr |= IE;
564 outb(icr, EWRK3_ICR);
565
566
567 dev->dma = 0;
568
569
570
571 if (dev->irq < 2) {
572 #ifndef MODULE
573 unsigned char irqnum;
574
575 autoirq_setup(0);
576
577
578
579
580 icr |=TNEM;
581 outb(1,EWRK3_TDQ);
582 outb(icr, EWRK3_ICR);
583
584 irqnum = irq[((icr & IRQ_SEL) >> 4)];
585
586 dev->irq = autoirq_report(1);
587 if ((dev->irq) && (irqnum == dev->irq)) {
588 printk(" and uses IRQ%d.\n", dev->irq);
589 } else {
590 if (!dev->irq) {
591 printk(" and failed to detect IRQ line.\n");
592 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
593 printk(" and an illegal IRQ line detected.\n");
594 } else {
595 printk(", but incorrect IRQ line detected.\n");
596 }
597 status = -ENXIO;
598 }
599
600 DISABLE_IRQs;
601
602 #endif
603 } else {
604 printk(" and requires IRQ%d.\n", dev->irq);
605 }
606 }
607 } else {
608 status = -ENXIO;
609 }
610 }
611 }
612 } else {
613 status = -ENXIO;
614 }
615 }
616
617 if (!status) {
618 if (ewrk3_debug > 0) {
619 printk(version);
620 }
621
622
623 dev->open = &ewrk3_open;
624 dev->hard_start_xmit = &ewrk3_queue_pkt;
625 dev->stop = &ewrk3_close;
626 dev->get_stats = &ewrk3_get_stats;
627 #ifdef HAVE_MULTICAST
628 dev->set_multicast_list = &set_multicast_list;
629 #endif
630 dev->do_ioctl = &ewrk3_ioctl;
631
632 dev->mem_start = 0;
633
634
635 ether_setup(dev);
636 }
637 } else {
638 status = -ENXIO;
639 }
640
641 return status;
642 }
643
644
645 static int
646 ewrk3_open(struct device *dev)
647 {
648 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
649 int i, iobase = dev->base_addr;
650 int status = 0;
651 unsigned char icr, csr;
652
653
654
655
656 STOP_EWRK3;
657
658 if (!lp->hard_strapped) {
659 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
660 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
661 status = -EAGAIN;
662 } else {
663
664 irq2dev_map[dev->irq] = dev;
665
666
667
668
669 ewrk3_init(dev);
670
671 if (ewrk3_debug > 1){
672 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
673 printk("\tphysical address: ");
674 for (i=0;i<6;i++){
675 printk("%2.2x:",(short)dev->dev_addr[i]);
676 }
677 printk("\n");
678 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
679 if (lp->shmem_length == 0) {
680 printk("\tno shared memory, I/O only mode\n");
681 } else {
682 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
683 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
684 }
685 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
686 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
687 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
688 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
689 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
690 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
691 }
692
693 dev->tbusy = 0;
694 dev->start = 1;
695 dev->interrupt = UNMASK_INTERRUPTS;
696
697
698
699
700 icr = inb(EWRK3_ICR);
701 ENABLE_IRQs;
702
703 }
704 } else {
705 dev->start = 0;
706 dev->tbusy = 1;
707 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
708 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
709 }
710
711 #ifdef MODULE
712 MOD_INC_USE_COUNT;
713 #endif
714
715
716 return status;
717 }
718
719
720
721
722 static void
723 ewrk3_init(struct device *dev)
724 {
725 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
726 char csr, page;
727 short iobase = dev->base_addr;
728
729
730
731
732 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
733
734
735
736
737 while (inb(EWRK3_TQ));
738 while (inb(EWRK3_TDQ));
739 while (inb(EWRK3_RQ));
740 while (inb(EWRK3_FMQ));
741
742
743
744
745 for (page=1;page<lp->mPage;page++) {
746 outb(page, EWRK3_FMQ);
747 }
748
749 lp->lock = 0;
750
751 START_EWRK3;
752 }
753
754
755
756
757 static int
758 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
759 {
760 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
761 int iobase = dev->base_addr;
762 int status = 0;
763 unsigned char icr, csr;
764
765
766 if (dev->tbusy || lp->lock) {
767 int tickssofar = jiffies - dev->trans_start;
768 if (tickssofar < 10) {
769 status = -1;
770 } else if (!lp->hard_strapped) {
771 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
772 dev->name, inb(EWRK3_CSR));
773
774
775
776
777 DISABLE_IRQs;
778
779
780
781
782 STOP_EWRK3;
783
784 ewrk3_init(dev);
785
786
787
788
789 ENABLE_IRQs;
790
791 dev->tbusy=0;
792 dev->trans_start = jiffies;
793 }
794 } else if (skb == NULL) {
795 dev_tint(dev);
796 } else if (skb->len > 0) {
797
798
799
800
801
802 if (set_bit(0, (void*)&dev->tbusy) != 0)
803 printk("%s: Transmitter access conflict.\n", dev->name);
804
805 DISABLE_IRQs;
806
807
808
809
810 if (inb(EWRK3_FMQC) > 0) {
811 unsigned char *buf;
812 unsigned char page;
813
814 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
815 buf = NULL;
816
817
818
819
820 while (set_bit(0, (void *)&lp->lock) != 0);
821 if (lp->shmem_length == IO_ONLY) {
822 outb(page, EWRK3_IOPR);
823 } else if (lp->shmem_length == SHMEM_2K) {
824 buf = (char *) lp->shmem_base;
825 outb(page, EWRK3_MPR);
826 } else if (lp->shmem_length == SHMEM_32K) {
827 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
828 outb((page >> 4), EWRK3_MPR);
829 } else if (lp->shmem_length == SHMEM_64K) {
830 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
831 outb((page >> 5), EWRK3_MPR);
832 } else {
833 status = -1;
834 printk("%s: Oops - your private data area is hosed!\n",dev->name);
835 }
836
837 if (!status) {
838
839
840
841
842
843
844 if (lp->shmem_length == IO_ONLY) {
845 int i;
846 unsigned char *p = skb->data;
847
848 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
849 outb((char)(skb->len & 0xff), EWRK3_DATA);
850 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
851 outb((char)0x04, EWRK3_DATA);
852 for (i=0; i<skb->len; i++) {
853 outb(*p++, EWRK3_DATA);
854 }
855 outb(page, EWRK3_TQ);
856 } else {
857 *buf++ = (char)(QMODE | PAD | IFC);
858 *buf++ = (char)(skb->len & 0xff);
859 if (lp->txc) {
860 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
861 *buf++ = 0x04;
862 *(buf + skb->len) = 0x00;
863 memcpy(buf, skb->data, PRELOAD);
864 outb(page, EWRK3_TQ);
865 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
866 *(buf + skb->len) = 0xff;
867 } else {
868 *buf++ = (char)((skb->len >> 8) & 0xff);
869 *buf++ = 0x04;
870 memcpy(buf, skb->data, skb->len);
871 outb(page, EWRK3_TQ);
872 }
873 }
874
875 dev->trans_start = jiffies;
876
877 dev_kfree_skb (skb, FREE_WRITE);
878
879 } else {
880 outb(page, EWRK3_FMQ);
881 }
882 lp->lock = 0;
883 } else {
884 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
885 (unsigned char) page);
886 }
887 } else {
888 printk("ewrk3_queue_pkt(): No free resources...\n");
889 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
890 }
891
892
893 if (inb(EWRK3_FMQC) > 0) {
894 dev->tbusy = 0;
895 }
896
897 ENABLE_IRQs;
898 }
899
900 return status;
901 }
902
903
904
905
906 static void
907 ewrk3_interrupt(int irq, struct pt_regs * regs)
908 {
909 struct device *dev = (struct device *)(irq2dev_map[irq]);
910 struct ewrk3_private *lp;
911 int iobase;
912 unsigned char icr, cr, csr;
913
914 if (dev == NULL) {
915 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
916 } else {
917 lp = (struct ewrk3_private *)dev->priv;
918 iobase = dev->base_addr;
919
920 if (dev->interrupt)
921 printk("%s: Re-entering the interrupt handler.\n", dev->name);
922
923 dev->interrupt = MASK_INTERRUPTS;
924
925
926 csr = inb(EWRK3_CSR);
927
928
929
930
931 DISABLE_IRQs;
932
933 cr = inb(EWRK3_CR);
934 cr |= LED;
935 outb(cr, EWRK3_CR);
936
937 if (csr & RNE)
938 ewrk3_rx(dev);
939
940 if (csr & TNE)
941 ewrk3_tx(dev);
942
943
944
945
946
947
948
949 if (inb(EWRK3_FMQC)) {
950 irq_mask |= TXDM|RXDM;
951 csr &= ~(TXD|RXD);
952 outb(csr, EWRK3_CSR);
953 dev->tbusy = 0;
954 mark_bh(NET_BH);
955 } else {
956 irq_mask &= ~(TXDM|RXDM);
957 }
958
959
960 cr &= ~LED;
961 outb(cr, EWRK3_CR);
962
963 dev->interrupt = UNMASK_INTERRUPTS;
964
965 ENABLE_IRQs;
966 }
967
968 return;
969 }
970
971 static int
972 ewrk3_rx(struct device *dev)
973 {
974 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
975 int i, iobase = dev->base_addr;
976 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
977 int status = 0;
978
979 while (inb(EWRK3_RQC) && !status) {
980 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
981 buf = NULL;
982
983
984
985
986
987 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
988 if (lp->shmem_length == IO_ONLY) {
989 tmpPage = inb(EWRK3_IOPR);
990 } else {
991 tmpPage = inb(EWRK3_MPR);
992 }
993 }
994
995
996
997
998 if (lp->shmem_length == IO_ONLY) {
999 outb(page, EWRK3_IOPR);
1000 } else if (lp->shmem_length == SHMEM_2K) {
1001 buf = (char *) lp->shmem_base;
1002 outb(page, EWRK3_MPR);
1003 } else if (lp->shmem_length == SHMEM_32K) {
1004 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1005 outb((page >> 4), EWRK3_MPR);
1006 } else if (lp->shmem_length == SHMEM_64K) {
1007 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1008 outb((page >> 5), EWRK3_MPR);
1009 } else {
1010 status = -1;
1011 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1012 }
1013
1014 if (!status) {
1015 char rx_status;
1016 int pkt_len;
1017
1018 if (lp->shmem_length == IO_ONLY) {
1019 rx_status = inb(EWRK3_DATA);
1020 pkt_len = inb(EWRK3_DATA);
1021 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1022 } else {
1023 rx_status = (char)(*buf++);
1024 pkt_len = (short)(*buf+((*(buf+1))<<8));
1025 buf+=3;
1026 }
1027
1028 if (!(rx_status & ROK)) {
1029 lp->stats.rx_errors++;
1030 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1031 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1032 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1033 } else {
1034 struct sk_buff *skb;
1035
1036 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1037 skb->len = pkt_len;
1038 skb->dev = dev;
1039
1040 if (lp->shmem_length == IO_ONLY) {
1041 unsigned char *p = skb->data;
1042
1043 *p = inb(EWRK3_DATA);
1044 for (i=0; i<skb->len; i++) {
1045 *p++ = inb(EWRK3_DATA);
1046 }
1047 } else {
1048 memcpy(skb->data, buf, pkt_len);
1049 }
1050
1051
1052
1053
1054
1055 netif_rx(skb);
1056
1057
1058
1059
1060 lp->stats.rx_packets++;
1061 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1062 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1063 lp->pktStats.bins[i]++;
1064 i = EWRK3_PKT_STAT_SZ;
1065 }
1066 }
1067 buf = skb->data;
1068 if (buf[0] & 0x01) {
1069 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1070 lp->pktStats.broadcast++;
1071 } else {
1072 lp->pktStats.multicast++;
1073 }
1074 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1075 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1076 lp->pktStats.unicast++;
1077 }
1078
1079 lp->pktStats.bins[0]++;
1080 if (lp->pktStats.bins[0] == 0) {
1081 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1082 }
1083 } else {
1084 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1085 lp->stats.rx_dropped++;
1086 break;
1087 }
1088 }
1089 }
1090
1091
1092
1093 outb(page, EWRK3_FMQ);
1094
1095 if (tmpLock) {
1096 if (lp->shmem_length == IO_ONLY) {
1097 outb(tmpPage, EWRK3_IOPR);
1098 } else {
1099 outb(tmpPage, EWRK3_MPR);
1100 }
1101 }
1102 lp->lock = 0;
1103 } else {
1104 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1105 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1106 }
1107 }
1108 return status;
1109 }
1110
1111
1112
1113
1114 static int
1115 ewrk3_tx(struct device *dev)
1116 {
1117 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1118 int iobase = dev->base_addr;
1119 unsigned char tx_status;
1120
1121 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1122 if (tx_status & VSTS) {
1123 if (tx_status & MAC_TXE) {
1124 lp->stats.tx_errors++;
1125 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1126 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1127 if (tx_status & MAC_CTU) {
1128 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1129 lp->pktStats.tx_underruns++;
1130 } else {
1131 lp->pktStats.excessive_underruns++;
1132 }
1133 } else if (tx_status & MAC_COLL) {
1134 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1135 lp->stats.collisions++;
1136 } else {
1137 lp->pktStats.excessive_collisions++;
1138 }
1139 }
1140 } else {
1141 lp->stats.tx_packets++;
1142 }
1143 }
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int
1150 ewrk3_close(struct device *dev)
1151 {
1152 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1153 int iobase = dev->base_addr;
1154 unsigned char icr, csr;
1155
1156 dev->start = 0;
1157 dev->tbusy = 1;
1158
1159 if (ewrk3_debug > 1) {
1160 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1161 dev->name, inb(EWRK3_CSR));
1162 }
1163
1164
1165
1166
1167 DISABLE_IRQs;
1168
1169 STOP_EWRK3;
1170
1171
1172
1173
1174
1175
1176
1177 while (inb(EWRK3_TQ));
1178 while (inb(EWRK3_TDQ));
1179 while (inb(EWRK3_RQ));
1180
1181 if (!lp->hard_strapped) {
1182 free_irq(dev->irq);
1183
1184 irq2dev_map[dev->irq] = 0;
1185 }
1186
1187 #ifdef MODULE
1188 MOD_DEC_USE_COUNT;
1189 #endif
1190
1191 return 0;
1192 }
1193
1194 static struct enet_statistics *
1195 ewrk3_get_stats(struct device *dev)
1196 {
1197 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1198
1199
1200
1201 return &lp->stats;
1202 }
1203
1204
1205
1206
1207
1208
1209
1210
1211 static void
1212 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1213 {
1214 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1215 int iobase = dev->base_addr;
1216 char *multicast_table;
1217 unsigned char csr;
1218
1219 csr = inb(EWRK3_CSR);
1220
1221 if (lp->shmem_length == IO_ONLY) {
1222 multicast_table = (char *) PAGE0_HTE;
1223 } else {
1224 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1225 }
1226
1227 if (num_addrs >= 0) {
1228 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1229 csr &= ~PME;
1230 csr |= MCE;
1231 outb(csr, EWRK3_CSR);
1232 } else {
1233 csr |= PME;
1234 csr &= ~MCE;
1235 outb(csr, EWRK3_CSR);
1236 }
1237 }
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1248 {
1249 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1250 int iobase = dev->base_addr;
1251 char j, ctrl, bit, octet;
1252 short *p = (short *) multicast_table;
1253 unsigned short hashcode;
1254 int i;
1255 long int crc, poly = (long int) CRC_POLYNOMIAL;
1256
1257 while (set_bit(0, (void *)&lp->lock) != 0);
1258
1259 if (lp->shmem_length == IO_ONLY) {
1260 outb(0, EWRK3_IOPR);
1261 outw((short)((long)multicast_table), EWRK3_PIR1);
1262 } else {
1263 outb(0, EWRK3_MPR);
1264 }
1265
1266 if (num_addrs == HASH_TABLE_LEN) {
1267 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1268 if (lp->shmem_length == IO_ONLY) {
1269 outb(0xff, EWRK3_DATA);
1270 } else {
1271 *p++ = 0xffff;
1272 i++;
1273 }
1274 }
1275 } else if (num_addrs == 0) {
1276 if (lp->shmem_length == IO_ONLY) {
1277 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1278 outb(0x00, EWRK3_DATA);
1279 }
1280 } else {
1281 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1282 }
1283 } else {
1284 for (i=0;i<num_addrs;i++) {
1285 if (((char) *(addrs+ETH_ALEN*i) & 0x01) == 1) {
1286 crc = (long int) 0xffffffff;
1287 for (octet=0;octet<ETH_ALEN;octet++) {
1288 for(j=0;j<8;j++) {
1289 bit = (((char)* (addrs+ETH_ALEN*i+octet)) >> j) & 0x01;
1290 ctrl = ((crc < 0) ? 1 : 0);
1291 crc <<= 1;
1292 if (bit ^ ctrl) {
1293 crc ^= poly;
1294 }
1295 }
1296 }
1297 hashcode = ((crc >>= 23) & 0x01);
1298 for (j=0;j<8;j++) {
1299 hashcode <<= 1;
1300 crc >>= 1;
1301 hashcode |= (crc & 0x01);
1302 }
1303
1304 octet = hashcode >> 3;
1305
1306 if (lp->shmem_length == IO_ONLY) {
1307 unsigned char tmp;
1308
1309 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1310 tmp = inb(EWRK3_DATA);
1311 tmp |= (1 << (hashcode & 0x07));
1312 outw((short)((long)multicast_table) + octet, EWRK3_PIR1);
1313 outb(tmp, EWRK3_DATA);
1314 } else {
1315 multicast_table[octet] |= (1 << (hashcode & 0x07));
1316 }
1317 }
1318 }
1319 }
1320
1321 lp->lock = 0;
1322
1323 return;
1324 }
1325
1326 #ifndef MODULE
1327
1328
1329
1330 static struct device *isa_probe(struct device *dev)
1331 {
1332 int i, iobase, status;
1333 unsigned long int tmp = mem_chkd;
1334
1335 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1336 i < 24;
1337 iobase += EWRK3_IOP_INC, i++) {
1338 if (tmp & 0x01) {
1339
1340 if (!check_region(iobase, EWRK3_IOP_INC)) {
1341 if (DevicePresent(iobase) == 0) {
1342
1343
1344
1345
1346 request_region(iobase, EWRK3_IOP_INC,"ewrk3");
1347 if (num_ewrk3s > 0) {
1348 dev = alloc_device(dev, iobase);
1349 } else {
1350 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1351 num_ewrk3s++;
1352 }
1353 }
1354 num_eth++;
1355 } else {
1356 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1357 }
1358 } else {
1359 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1360 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1361 }
1362 }
1363 tmp >>= 1;
1364 }
1365
1366 return dev;
1367 }
1368
1369
1370
1371
1372
1373 static struct device *eisa_probe(struct device *dev)
1374 {
1375 int i, iobase = EWRK3_EISA_IO_PORTS;
1376 int status;
1377
1378 iobase+=EISA_SLOT_INC;
1379 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1380
1381
1382 if (!check_region(iobase, EWRK3_IOP_INC)) {
1383 if (DevicePresent(iobase) == 0) {
1384
1385
1386
1387
1388 mem_chkd |= (0x01 << (i + 24));
1389 request_region(iobase, EWRK3_IOP_INC,"ewrk3");
1390 if (num_ewrk3s > 0) {
1391 dev = alloc_device(dev, iobase);
1392 } else {
1393 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1394 num_ewrk3s++;
1395 }
1396 }
1397 num_eth++;
1398 }
1399 }
1400 }
1401 return dev;
1402 }
1403
1404
1405
1406
1407
1408 static struct device *alloc_device(struct device *dev, int iobase)
1409 {
1410
1411
1412
1413 while (dev->next != NULL) {
1414 if (dev->next->base_addr == 0xffe0) break;
1415 dev = dev->next;
1416 num_eth++;
1417 }
1418
1419
1420
1421
1422
1423 if (dev->next == NULL) {
1424 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1425 GFP_KERNEL);
1426 if (dev->next == NULL) {
1427 printk("eth%d: Device not initialised, insufficient memory\n",
1428 num_eth);
1429 }
1430 }
1431
1432
1433
1434
1435
1436
1437 if ((dev->next != NULL) &&
1438 (num_eth > 0) && (num_eth < 9999)) {
1439 dev = dev->next;
1440 dev->name = (char *)(dev + sizeof(struct device));
1441 sprintf(dev->name,"eth%d", num_eth);
1442 dev->base_addr = iobase;
1443 dev->next = NULL;
1444 dev->init = &ewrk3_probe;
1445 num_ewrk3s++;
1446 }
1447
1448 return dev;
1449 }
1450 #endif
1451
1452
1453
1454
1455 static int Read_EEPROM(short iobase, unsigned char eaddr)
1456 {
1457 int i;
1458
1459 outb((eaddr & 0x3f), EWRK3_PIR1);
1460 outb(EEPROM_RD, EWRK3_IOPR);
1461 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1462
1463 return inw(EWRK3_EPROM1);
1464 }
1465
1466
1467
1468
1469 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1470 {
1471 int i;
1472
1473 outb(EEPROM_WR_EN, EWRK3_IOPR);
1474 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1475 outw(data, EWRK3_EPROM1);
1476 outb((eaddr & 0x3f), EWRK3_PIR1);
1477 outb(EEPROM_WR, EWRK3_IOPR);
1478 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1479 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1480 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1481
1482 return 0;
1483 }
1484
1485
1486
1487
1488 static void EthwrkSignature(char *name, char *eeprom_image)
1489 {
1490 unsigned long i,j,k;
1491 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1492
1493 strcpy(name, "");
1494 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1495 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1496 if (signatures[i][k] == eeprom_image[j]) {
1497 k++;
1498 } else {
1499 k=0;
1500 }
1501 }
1502 if (k == strlen(signatures[i])) {
1503 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1504 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1505 name[EWRK3_NAME_LENGTH] = '\0';
1506 }
1507 }
1508 }
1509
1510 return;
1511 }
1512
1513
1514
1515
1516
1517
1518 static int DevicePresent(short iobase)
1519 {
1520 static short fp=1,sigLength=0;
1521 static char devSig[] = PROBE_SEQUENCE;
1522 char data;
1523 int i, j, status = 0;
1524 static char asc2hex(char value);
1525
1526
1527
1528
1529 if (fp) {
1530 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1531 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1532 devSig[i]<<=4;
1533 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1534 devSig[j]=devSig[i]+devSig[i+1];
1535 } else {
1536 status= -1;
1537 }
1538 } else {
1539 status= -1;
1540 }
1541 }
1542 sigLength=j;
1543 fp = 0;
1544 }
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554 if (!status) {
1555 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1556 data = inb(EWRK3_APROM);
1557 if (devSig[j] == data) {
1558 j++;
1559 } else {
1560 j=0;
1561 }
1562 }
1563
1564 if (j!=sigLength) {
1565 status = -ENODEV;
1566 }
1567 }
1568
1569 return status;
1570 }
1571
1572 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1573 {
1574 long k;
1575 unsigned short j,chksum;
1576 unsigned char crc, lfsr, sd, status = 0;
1577 int iobase = dev->base_addr;
1578
1579 if (chipType == LeMAC2) {
1580 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1581 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1582 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1583 crc = (crc >> 1) + lfsr;
1584 }
1585 }
1586 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1587 } else {
1588 for (k=0,j=0;j<3;j++) {
1589 k <<= 1 ;
1590 if (k > 0xffff) k-=0xffff;
1591 k += inw(EWRK3_PAR0 + (j<<1));
1592 if (k > 0xffff) k-=0xffff;
1593 }
1594 if (k == 0xffff) k=0;
1595 chksum = inb(EWRK3_APROM);
1596 chksum |= (inb(EWRK3_APROM)<<8);
1597 if (k != chksum) status = -1;
1598 }
1599
1600 return status;
1601 }
1602
1603
1604
1605
1606
1607 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1608 {
1609 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1610 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1611 int i, j, iobase = dev->base_addr, status = 0;
1612 unsigned char csr;
1613 union {
1614 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1615 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1616 } tmp;
1617
1618 switch(ioc->cmd) {
1619 case EWRK3_GET_HWADDR:
1620 for (i=0; i<ETH_ALEN; i++) {
1621 tmp.addr[i] = dev->dev_addr[i];
1622 }
1623 ioc->len = ETH_ALEN;
1624 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1625
1626 break;
1627 case EWRK3_SET_HWADDR:
1628 if (suser()) {
1629 csr = inb(EWRK3_CSR);
1630 csr |= (TXD|RXD);
1631 outb(csr, EWRK3_CSR);
1632
1633 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1634 for (i=0; i<ETH_ALEN; i++) {
1635 dev->dev_addr[i] = tmp.addr[i];
1636 outb(tmp.addr[i], EWRK3_PAR0 + i);
1637 }
1638
1639 csr &= ~(TXD|RXD);
1640 outb(csr, EWRK3_CSR);
1641 } else {
1642 status = -EPERM;
1643 }
1644
1645 break;
1646 case EWRK3_SET_PROM:
1647 if (suser()) {
1648 csr = inb(EWRK3_CSR);
1649 csr |= PME;
1650 csr &= ~MCE;
1651 outb(csr, EWRK3_CSR);
1652 } else {
1653 status = -EPERM;
1654 }
1655
1656 break;
1657 case EWRK3_CLR_PROM:
1658 if (suser()) {
1659 csr = inb(EWRK3_CSR);
1660 csr &= ~PME;
1661 outb(csr, EWRK3_CSR);
1662 } else {
1663 status = -EPERM;
1664 }
1665
1666 break;
1667 case EWRK3_SAY_BOO:
1668 printk("%s: Boo!\n", dev->name);
1669
1670 break;
1671 case EWRK3_GET_MCA:
1672 while (set_bit(0, (void *)&lp->lock) != 0);
1673 if (lp->shmem_length == IO_ONLY) {
1674 outb(0, EWRK3_IOPR);
1675 outw(PAGE0_HTE, EWRK3_PIR1);
1676 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1677 tmp.addr[i] = inb(EWRK3_DATA);
1678 }
1679 } else {
1680 outb(0, EWRK3_MPR);
1681 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1682 }
1683 ioc->len = (HASH_TABLE_LEN >> 3);
1684 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1685 lp->lock = 0;
1686
1687 break;
1688 case EWRK3_SET_MCA:
1689 if (suser()) {
1690 if (ioc->len != HASH_TABLE_LEN) {
1691 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1692 }
1693 set_multicast_list(dev, ioc->len, tmp.addr);
1694 } else {
1695 status = -EPERM;
1696 }
1697
1698 break;
1699 case EWRK3_CLR_MCA:
1700 if (suser()) {
1701 set_multicast_list(dev, 0, NULL);
1702 } else {
1703 status = -EPERM;
1704 }
1705
1706 break;
1707 case EWRK3_MCA_EN:
1708 if (suser()) {
1709 csr = inb(EWRK3_CSR);
1710 csr |= MCE;
1711 csr &= ~PME;
1712 outb(csr, EWRK3_CSR);
1713 } else {
1714 status = -EPERM;
1715 }
1716
1717 break;
1718 case EWRK3_GET_STATS:
1719 cli();
1720 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1721 ioc->len = EWRK3_PKT_STAT_SZ;
1722 sti();
1723
1724 break;
1725 case EWRK3_CLR_STATS:
1726 if (suser()) {
1727 cli();
1728 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1729 sti();
1730 } else {
1731 status = -EPERM;
1732 }
1733
1734 break;
1735 case EWRK3_GET_CSR:
1736 tmp.addr[0] = inb(EWRK3_CSR);
1737 memcpy_tofs(ioc->data, tmp.addr, 1);
1738
1739 break;
1740 case EWRK3_SET_CSR:
1741 if (suser()) {
1742 memcpy_fromfs(tmp.addr, ioc->data, 1);
1743 outb(tmp.addr[0], EWRK3_CSR);
1744 } else {
1745 status = -EPERM;
1746 }
1747
1748 break;
1749 case EWRK3_GET_EEPROM:
1750 if (suser()) {
1751 for (i=0; i<(EEPROM_MAX>>1); i++) {
1752 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1753 }
1754 i = EEPROM_MAX;
1755 tmp.addr[i++] = inb(EWRK3_CMR);
1756 for (j=0;j<ETH_ALEN;j++) {
1757 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1758 }
1759 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1760 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1761 } else {
1762 status = -EPERM;
1763 }
1764
1765 break;
1766 case EWRK3_SET_EEPROM:
1767 if (suser()) {
1768 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1769 for (i=0; i<(EEPROM_MAX>>1); i++) {
1770 Write_EEPROM(tmp.val[i], iobase, i);
1771 }
1772 } else {
1773 status = -EPERM;
1774 }
1775
1776 break;
1777 case EWRK3_GET_CMR:
1778 tmp.addr[0] = inb(EWRK3_CMR);
1779 memcpy_tofs(ioc->data, tmp.addr, 1);
1780
1781 break;
1782 case EWRK3_SET_TX_CUT_THRU:
1783 if (suser()) {
1784 lp->txc = 1;
1785 } else {
1786 status = -EPERM;
1787 }
1788
1789 break;
1790 case EWRK3_CLR_TX_CUT_THRU:
1791 if (suser()) {
1792 lp->txc = 0;
1793 } else {
1794 status = -EPERM;
1795 }
1796
1797 break;
1798 default:
1799 status = -EOPNOTSUPP;
1800 }
1801
1802 return status;
1803 }
1804
1805 static char asc2hex(char value)
1806 {
1807 value -= 0x30;
1808 if (value >= 0) {
1809 if (value > 9) {
1810 value &= 0x1f;
1811 value -= 0x07;
1812 if ((value < 0x0a) || (value > 0x0f)) {
1813 value = -1;
1814 }
1815 }
1816 } else {
1817 value = -1;
1818 }
1819 return value;
1820 }
1821
1822 #ifdef MODULE
1823 char kernel_version[] = UTS_RELEASE;
1824 static struct device thisEthwrk = {
1825 " ",
1826 0, 0, 0, 0,
1827 0x300, 5,
1828 0, 0, 0, NULL, ewrk3_probe };
1829
1830
1831 int io=0x300;
1832 int irq=5;
1833
1834 int
1835 init_module(void)
1836 {
1837 thisEthwrk.base_addr=io;
1838 thisEthwrk.irq=irq;
1839 if (register_netdev(&thisEthwrk) != 0)
1840 return -EIO;
1841 return 0;
1842 }
1843
1844 void
1845 cleanup_module(void)
1846 {
1847 if (MOD_IN_USE) {
1848 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1849 } else {
1850 unregister_netdev(&thisEthwrk);
1851 }
1852 }
1853 #endif
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865