include/linux/pci.h

/* */
   1 /*
   2  * PCI defines and function prototypes
   3  * Copyright 1994, Drew Eckhardt
   4  *
   5  * For more information, please consult 
   6  * 
   7  * PCI BIOS Specification Revision
   8  * PCI Local Bus Specification
   9  * PCI System Design Guide
  10  *
  11  * PCI Special Interest Group
  12  * M/S HF3-15A
  13  * 5200 N.E. Elam Young Parkway
  14  * Hillsboro, Oregon 97124-6497
  15  * +1 (503) 696-2000 
  16  * +1 (800) 433-5177
  17  * 
  18  * Manuals are $25 each or $50 for all three, plus $7 shipping 
  19  * within the United States, $35 abroad.
  20  */
  21 
  22 #ifndef PCI_H
  23 #define PCI_H
  24 
  25 /* Configuration method #1 */
  26 #define PCI_CONFIG1_ADDRESS_REG  0xcf8
  27 #define PCI_CONFIG1_ENABLE 0x80000000
  28 #define PCI_CONFIG1_TUPPLE(bus, device, function, register)     \
  29         (PCI_CONFIG1_ENABLE | ((bus) << 16) & 0xff0000 |        \
  30         ((device) << 11) & 0xf800 | ((function) << 8) & 0x700 | \
  31         ((register) << 2) & 0xfc)
  32 #define PCI_CONFIG1_DATA_REG     0xcfc
  33 
  34 /* Configuration method #2, deprecated */
  35 #define PCI_CONFIG2_ENABLE_REG  0xcf8
  36 #define PCI_CONFIG2_ENABLE      0xf0
  37 #define PCI_CONFIG2_TUPPLE(function)                            \
  38         (PCI_CONFIG2_ENABLE | ((function) << 1) & 0xe)
  39 #define PCI_CONFIG2_FORWARD_REG 0xcfa
  40 
  41 /*
  42  * Under PCI, each device has 256 bytes of configuration address space,
  43  * of which the first 64 bytes is standardized as follows : 
  44  */
  45 
  46 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  47 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  48 #define PCI_COMMAND             0x04    /* 16 bits */
  49 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  50 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in I/O space */
  51 #define  PCI_COMMAND_MASTER     0x4     /* Enable bus mastering */
  52 #define  PCI_COMMAND_SPECIAL    0x8     /* Enable response to special cycles */
  53 #define  PCI_COMMAND_INVALIDATE 0x10    /* Use memory write and invalidate */
  54 #define  PCI_COMMAND_VGA_PALETTE        0x20    /* Enable palette snooping */
  55 #define  PCI_COMMAND_PARITY     0x40    /* Enable parity checking */
  56 #define  PCI_COMMAND_WAIT       0x80    /* Enable address/data stepping */
  57 #define  PCI_COMMAND_SERR       0x100   /* Enable SERR */
  58 #define  PCI_COMMAND_FAST_BACK  0x200   /* Enable back-to-back writes */
  59 
  60 #define PCI_STATUS              0x06    /* 16 bits */
  61 #define  PCI_STATUS_FAST_BACK   0x80    /* Accept fast-back to back */
  62 #define  PCI_STATUS_PARITY      0x100   /* Detected parity error */
  63 #define  PCI_STATUS_DEVSEL_MASK 0x600   /* DEVSEL timing */
  64 #define  PCI_STATUS_DEVSEL_FAST 0x000   
  65 #define  PCI_STATUS_DEVSEL_MEDIUM 0x200
  66 #define  PCI_STATUS_DEVESEL_SLOW 0x400
  67 #define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  68 #define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  69 #define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  70 #define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  71 #define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  72 
  73 #define PCI_CLASS_REVISION      0x08    /* High 24 bits are class, low 8
  74                                            revision */
  75 #define PCI_REVISION_ID         0x08    /* Revision ID */
  76 #define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
  77 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  78 
  79 #define PCI_CACHE_LINE_SIZE     0x0c    /* 8 bits */
  80 #define PCI_LATENCY_TIMER       0x0d    /* 8 bits */
  81 #define PCI_HEADER_TYPE         0x0e    /* 8 bits */
  82 #define PCI_BIST                0x0f    /* 8 bits */
  83 #define PCI_BIST_CODE_MASK      0x0f    /* Return result */
  84 #define PCI_BIST_START          0x40    /* 1 to start BIST, 2 secs or less */
  85 #define PCI_BIST_CAPABLE        0x80    /* 1 if BIST capable */
  86 
  87 /*
  88  * Base addresses specify locations in memory or I/O space.
  89  * Decoded size can be determined by writing a value of 
  90  * 0xffffffff to the register, and reading it back.  Only 
  91  * 1 bits are decoded.
  92  */
  93 
  94 #define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
  95 #define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
  96 #define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
  97 #define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
  98 #define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
  99 #define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
 100 #define  PCI_BASE_ADDRESS_SPACE 0x01    /* 0 = memory, 1 = I/O */
 101 #define  PCI_BASE_ADDRESS_SPACE_IO 0x01
 102 #define  PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
 103 #define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
 104 #define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
 105 #define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M */
 106 #define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
 107 #define  PCI_BASE_ADDRESS_MEM_MASK      ~7
 108 #define  PCI_BASE_ADDRESS_IO_MASK       ~3
 109 /* bit 1 is reserved if address_space = 1 */
 110 
 111 /* 0x28-0x2f are reserved */
 112 #define PCI_ROM_ADDRESS         0x30    /* 32 bits */
 113 #define  PCI_ROM_ADDRESS_ENABLE 0x01    /* Write 1 to enable ROM,
 114                                            bits 31..11 are address,
 115                                            10..2 are reserved */
 116 /* 0x34-0x3b are reserved */
 117 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
 118 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
 119 #define PCI_MIN_GNT             0x3e    /* 8 bits */
 120 #define PCI_MAX_LAT             0x3f    /* 8 bits */
 121 
 122 #define PCI_CLASS_NOT_DEFINED           0x0000
 123 #define PCI_CLASS_NOT_DEFINED_VGA       0x0001
 124 
 125 #define PCI_CLASS_STORAGE_SCSI          0x0100
 126 #define PCI_CLASS_STORAGE_IDE           0x0101
 127 #define PCI_CLASS_STORAGE_FLOPPY        0x0102
 128 #define PCI_CLASS_STORAGE_IPI           0x0103
 129 #define PCI_CLASS_STORAGE_OTHER         0x0180
 130 
 131 #define PCI_CLASS_NETWORK_ETHERNET      0x0200
 132 #define PCI_CLASS_NETWORK_TOKEN_RING    0x0201
 133 #define PCI_CLASS_NETWORK_FDDI          0x0202
 134 #define PCI_CLASS_NETWORK_OTHER         0x0280
 135 
 136 #define PCI_CLASS_DISPLAY_VGA           0x0300
 137 #define PCI_CLASS_DISPLAY_XGA           0x0301
 138 #define PCI_CLASS_DISPLAY_OTHER         0x0380
 139 
 140 #define PCI_CLASS_MULTIMEDIA_VIDEO      0x0400
 141 #define PCI_CLASS_MULTIMEDIA_AUDIO      0x0401
 142 #define PCI_CLASS_MULTIMEDIA_OTHER      0x0480
 143 
 144 #define PCI_CLASS_MEMORY_RAM            0x0500
 145 #define PCI_CLASS_MEMORY_FLASH          0x0501
 146 #define PCI_CLASS_MEMORY_OTHER          0x0580
 147 
 148 #define PCI_CLASS_BRIDGE_HOST           0x0600
 149 #define PCI_CLASS_BRIDGE_ISA            0x0601
 150 #define PCI_CLASS_BRIDGE_EISA           0x0602
 151 #define PCI_CLASS_BRIDGE_MC             0x0603
 152 #define PCI_CLASS_BRIDGE_PCI            0x0604
 153 #define PCI_CLASS_BRIDGE_PCMCIA         0x0605
 154 #define PCI_CLASS_BRIDGE_OTHER          0x0680
 155 
 156 #define PCI_CLASS_OTHERS                0xff
 157 
 158 struct pci_class_type {
 159         unsigned long class_id;
 160         char *class_name;
 161 };
 162 
 163 #define PCI_CLASS_NUM 28
 164 #define PCI_CLASS_TYPE    { \
 165         {PCI_CLASS_NOT_DEFINED,         "Old unidentified device"}, \
 166         {PCI_CLASS_NOT_DEFINED_VGA,     "Old VGA controller"}, \
 167         {PCI_CLASS_STORAGE_SCSI,        "SCSI bus controller"}, \
 168         {PCI_CLASS_STORAGE_IDE,         "IDE controller"}, \
 169         {PCI_CLASS_STORAGE_FLOPPY,      "Floppy controller"}, \
 170         {PCI_CLASS_STORAGE_IPI,         "IPI bus controller"}, \
 171         {PCI_CLASS_STORAGE_OTHER,       "Unknown mass storage controller"}, \
 172         {PCI_CLASS_NETWORK_ETHERNET,    "Ethernet controller"}, \
 173         {PCI_CLASS_NETWORK_TOKEN_RING,  "Token ring controller"}, \
 174         {PCI_CLASS_NETWORK_FDDI,        "FDDI controller"}, \
 175         {PCI_CLASS_NETWORK_OTHER,       "Unknown network controller"}, \
 176         {PCI_CLASS_DISPLAY_VGA,         "VGA display controller"}, \
 177         {PCI_CLASS_DISPLAY_XGA,         "XGA display controller"}, \
 178         {PCI_CLASS_DISPLAY_OTHER,       "Unknown display controller"}, \
 179         {PCI_CLASS_MULTIMEDIA_VIDEO,    "Video device"}, \
 180         {PCI_CLASS_MULTIMEDIA_AUDIO,    "Audio device"}, \
 181         {PCI_CLASS_MULTIMEDIA_OTHER,    "Unknown multimedia device"}, \
 182         {PCI_CLASS_MEMORY_RAM,          "RAM controller"}, \
 183         {PCI_CLASS_MEMORY_FLASH,        "FLASH controller"}, \
 184         {PCI_CLASS_MEMORY_OTHER,        "Unknown memory controller"}, \
 185         {PCI_CLASS_BRIDGE_HOST,         "Host bridge"}, \
 186         {PCI_CLASS_BRIDGE_ISA,          "ISA bridge"}, \
 187         {PCI_CLASS_BRIDGE_EISA,         "EISA bridge"}, \
 188         {PCI_CLASS_BRIDGE_MC,           "MC bridge"}, \
 189         {PCI_CLASS_BRIDGE_PCI,          "PCI to PCI bridge"}, \
 190         {PCI_CLASS_BRIDGE_PCMCIA,       "PCMCIA bridge"}, \
 191         {PCI_CLASS_BRIDGE_OTHER,        "Unknown bridge device"}, \
 192         {0,                             "Unknown type of PCI device"} \
 193 }
 194 
 195 #define PCI_VENDOR_ID_NCR               0x1000
 196 #define PCI_DEVICE_ID_NCR_53C810        0x0001
 197 #define PCI_DEVICE_ID_NCR_53C815        0x0004
 198 #define PCI_DEVICE_ID_NCR_53C820        0x0002
 199 #define PCI_DEVICE_ID_NCR_53C825        0x0003
 200 
 201 #define PCI_VENDOR_ID_ADAPTEC           0x9004
 202 #define PCI_DEVICE_ID_ADAPTEC_2940      0x7178
 203 
 204 #define PCI_VENDOR_ID_DPT               0x1044   
 205 #define PCI_DEVICE_ID_DPT               0xa400  
 206 
 207 #define PCI_VENDOR_ID_S3                0x5333
 208 #define PCI_DEVICE_ID_S3_864_1          0x88c0
 209 #define PCI_DEVICE_ID_S3_864_2          0x88c1
 210 #define PCI_DEVICE_ID_S3_928            0x88b0
 211 #define PCI_DEVICE_ID_S3_964_1          0x88d0
 212 #define PCI_DEVICE_ID_S3_964_2          0x88d1
 213 #define PCI_DEVICE_ID_S3_811            0x8811
 214 
 215 #define PCI_VENDOR_ID_OPTI              0x1045
 216 #define PCI_DEVICE_ID_OPTI_82C822       0xc822
 217 #define PCI_DEVICE_ID_OPTI_82C621       0xc621
 218 
 219 #define PCI_VENDOR_ID_UMC               0x1060
 220 #define PCI_DEVICE_ID_UMC_UM8881F       0x8881
 221 #define PCI_DEVICE_ID_UMC_UM8891A       0x0891
 222 #define PCI_DEVICE_ID_UMC_UM8886F       0x8886
 223 #define PCI_DEVICE_ID_UMC_UM8673F       0x0101
 224 
 225 #define PCI_VENDOR_ID_DEC               0x1011
 226 #define PCI_DEVICE_ID_DEC_TULIP         0x0002
 227 #define PCI_DEVICE_ID_DEC_TULIP_FAST    0x0009
 228 #define PCI_DEVICE_ID_DEC_FDDI          0x000F
 229 
 230 #define PCI_VENDOR_ID_MATROX            0x102B
 231 
 232 #define PCI_VENDOR_ID_INTEL             0x8086
 233 #define PCI_DEVICE_ID_INTEL_82378       0x0484
 234 #define PCI_DEVICE_ID_INTEL_82424       0x0483
 235 #define PCI_DEVICE_ID_INTEL_82375       0x0482
 236 #define PCI_DEVICE_ID_INTEL_82434       0x04a3
 237 #define PCI_DEVICE_ID_INTEL_82430       0x0486
 238 
 239 #define PCI_VENDOR_ID_SMC               0x1042
 240 #define PCI_DEVICE_ID_SMC_37C665        0x1000
 241 
 242 #define PCI_VENDOR_ID_ATI               0x1002
 243 #define PCI_DEVICE_ID_ATI_M32           0x4158
 244 #define PCI_DEVICE_ID_ATI_M64           0x4758
 245 
 246 #define PCI_VENDOR_ID_WEITEK            0x100e
 247 #define PCI_DEVICE_ID_WEITEK_P9000      0x9001
 248 #define PCI_DEVICE_ID_WEITEK_P9100      0x9100
 249 
 250 #define PCI_VENDOR_ID_CIRRUS            0x1013
 251 #define PCI_DEVICE_ID_CIRRUS_5434_4     0x00A4
 252 #define PCI_DEVICE_ID_CIRRUS_5434_8     0x00A8
 253 #define PCI_DEVICE_ID_CIRRUS_6729       0x1100
 254 
 255 #define PCI_VENDOR_ID_BUSLOGIC          0x104B
 256 #define PCI_DEVICE_ID_BUSLOGIC_946C     0x0140
 257 
 258 #define PCI_VENDOR_ID_N9                0x105D
 259 #define PCI_DEVICE_ID_N9_I128           0x2309
 260 
 261 #define PCI_VENDOR_ID_AI                0x1025
 262 #define PCI_DEVICE_ID_AI_M1435          0x1435
 263 
 264 #define PCI_VENDOR_ID_AL                0x10b9
 265 #define PCI_DEVICE_ID_AL_M1449          0x4449
 266 #define PCI_DEVICE_ID_AL_M1451          0x1451
 267 
 268 #define PCI_VENDOR_ID_TSENG             0x100c
 269 #define PCI_DEVICE_ID_TSENG_W32P_2      0x3202
 270 #define PCI_DEVICE_ID_TSENG_W32P_b      0x3205
 271 #define PCI_DEVICE_ID_TSENG_W32P_a      0x3207
 272 
 273 #define PCI_VENDOR_ID_CMD               0x1095
 274 #define PCI_DEVICE_ID_CMD_640           0x0640
 275 
 276 #define PCI_VENDOR_ID_VISION            0x1098
 277 #define PCI_DEVICE_ID_VISION_QD8500     0x0001
 278 
 279 #define PCI_VENDOR_ID_AMD               0x1022
 280 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
 281 
 282 #define PCI_VENDOR_ID_VLSI              0x1004
 283 #define PCI_DEVICE_ID_VLSI_82C593       0x0006
 284 
 285 #define PCI_VENDOR_ID_ADL               0x1005
 286 #define PCI_DEVICE_ID_ADL_2301          0x2301
 287 
 288 #define PCI_VENDOR_ID_SYMPHONY          0x1c1c
 289 #define PCI_DEVICE_ID_SYMPHONY_101      0x0001
 290 
 291 #define PCI_VENDOR_ID_TRIDENT           0x1023
 292 #define PCI_DEVICE_ID_TRIDENT_9420      0x9420
 293 
 294 #define PCI_VENDOR_ID_CONTAQ            0x1023
 295 #define PCI_DEVICE_ID_CONTAQ_82C599     0x0600
 296 
 297 #define PCI_VENDOR_ID_NS                0x100b
 298 
 299 struct pci_vendor_type {
 300         unsigned short vendor_id;
 301         char *vendor_name;
 302 };
 303 
 304 
 305 #define PCI_VENDOR_NUM 27
 306 #define PCI_VENDOR_TYPE { \
 307         {PCI_VENDOR_ID_NCR,             "NCR"}, \
 308         {PCI_VENDOR_ID_ADAPTEC,         "Adaptec"}, \
 309         {PCI_VENDOR_ID_DPT,             "DPT"}, \
 310         {PCI_VENDOR_ID_S3,              "S3 Inc."}, \
 311         {PCI_VENDOR_ID_OPTI,            "OPTI"}, \
 312         {PCI_VENDOR_ID_UMC,             "UMC"}, \
 313         {PCI_VENDOR_ID_DEC,             "DEC"}, \
 314         {PCI_VENDOR_ID_MATROX,          "Matrox"}, \
 315         {PCI_VENDOR_ID_INTEL,           "Intel"}, \
 316         {PCI_VENDOR_ID_SMC,             "SMC"}, \
 317         {PCI_VENDOR_ID_ATI,             "ATI"}, \
 318         {PCI_VENDOR_ID_WEITEK,          "Weitek"}, \
 319         {PCI_VENDOR_ID_CIRRUS,          "Cirrus Logic"}, \
 320         {PCI_VENDOR_ID_BUSLOGIC,        "Bus Logic"}, \
 321         {PCI_VENDOR_ID_N9,              "Number Nine"}, \
 322         {PCI_VENDOR_ID_AI,              "Acer Incorporated"}, \
 323         {PCI_VENDOR_ID_AL,              "Acer Labs"}, \
 324         {PCI_VENDOR_ID_TSENG,           "Tseng'Lab"}, \
 325         {PCI_VENDOR_ID_CMD,             "CMD"}, \
 326         {PCI_VENDOR_ID_VISION,          "Vision"}, \
 327         {PCI_VENDOR_ID_AMD,             "AMD"}, \
 328         {PCI_VENDOR_ID_VLSI,            "VLSI"}, \
 329         {PCI_VENDOR_ID_ADL,             "Advance Logic"}, \
 330         {PCI_VENDOR_ID_SYMPHONY,        "Symphony"}, \
 331         {PCI_VENDOR_ID_TRIDENT,         "Trident"}, \
 332         {PCI_VENDOR_ID_CONTAQ,          "Contaq"}, \
 333         {PCI_VENDOR_ID_NS,              "NS"} \
 334 }
 335 
 336 
 337 /* Optimisation pointer is a offset of an item into the array           */
 338 /* BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI     */
 339 /* bridge, or that we don't know for the moment how to configure it.    */
 340 /* I'm trying to do my best so that the kernel stays small.             */
 341 /* Different chipset can have same optimisation structure. i486 and     */
 342 /* pentium chipsets from the same manufacturer usually have the same    */
 343 /* structure                                                            */
 344 
 345 struct pci_device_type {
 346         unsigned char bridge_id;
 347         unsigned short vendor_id;
 348         unsigned short device_id;
 349         char *device_name;
 350 };
 351 
 352 #define PCI_DEVICE_NUM 50
 353 #define PCI_DEVICE_TYPE { \
 354         {0xff,  PCI_VENDOR_ID_NCR,      PCI_DEVICE_ID_NCR_53C810,       "53c810"}, \
 355         {0xff,  PCI_VENDOR_ID_NCR,      PCI_DEVICE_ID_NCR_53C815,       "53c815"}, \
 356         {0xff,  PCI_VENDOR_ID_NCR,      PCI_DEVICE_ID_NCR_53C820,       "53c820"}, \
 357         {0xff,  PCI_VENDOR_ID_NCR,      PCI_DEVICE_ID_NCR_53C825,       "53c825"}, \
 358         {0xff,  PCI_VENDOR_ID_ADAPTEC,  PCI_DEVICE_ID_ADAPTEC_2940,     "2940"}, \
 359         {0xff,  PCI_VENDOR_ID_DPT,      PCI_DEVICE_ID_DPT,              "SmartCache/Raid"}, \
 360         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_864_1,         "Vision 864-P"}, \
 361         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_864_2,         "Vision 864-P"}, \
 362         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_928,           "Vision 928-P"}, \
 363         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_964_1,         "Vision 964-P"}, \
 364         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_964_2,         "Vision 964-P"}, \
 365         {0xff,  PCI_VENDOR_ID_S3,       PCI_DEVICE_ID_S3_811,           "Trio32/Trio64"}, \
 366         {0x02,  PCI_VENDOR_ID_OPTI,     PCI_DEVICE_ID_OPTI_82C822,      "82C822"}, \
 367         {0xff,  PCI_VENDOR_ID_OPTI,     PCI_DEVICE_ID_OPTI_82C621,      "82C621"}, \
 368         {0xff,  PCI_VENDOR_ID_UMC,      PCI_DEVICE_ID_UMC_UM8881F,      "UM8881F"}, \
 369         {0x01,  PCI_VENDOR_ID_UMC,      PCI_DEVICE_ID_UMC_UM8891A,      "UM8891A"}, \
 370         {0xff,  PCI_VENDOR_ID_UMC,      PCI_DEVICE_ID_UMC_UM8886F,      "UM8886F"}, \
 371         {0xff,  PCI_VENDOR_ID_UMC,      PCI_DEVICE_ID_UMC_UM8673F,      "UM8673F"}, \
 372         {0xff,  PCI_VENDOR_ID_DEC,      PCI_DEVICE_ID_DEC_TULIP,        "DC21040"}, \
 373         {0xff,  PCI_VENDOR_ID_DEC,      PCI_DEVICE_ID_DEC_TULIP_FAST,   "DC21040"}, \
 374         {0xff,  PCI_VENDOR_ID_DEC,      PCI_DEVICE_ID_DEC_FDDI,         "DEFPA"}, \
 375         {0xff,  PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82378,      "82378IB"}, \
 376         {0x00,  PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82424,      "82424ZX Saturn"}, \
 377         {0xff,  PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82375,      "82375EB"}, \
 378         {0x00,  PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82434,      "82434LX Mercury/Neptune"}, \
 379         {0xff,  PCI_VENDOR_ID_INTEL,    PCI_DEVICE_ID_INTEL_82430,      "82430ZX Aries"}, \
 380         {0xff,  PCI_VENDOR_ID_SMC,      PCI_DEVICE_ID_SMC_37C665,       "FDC 37C665"}, \
 381         {0xff,  PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_M32,          "Mach 32"}, \
 382         {0xff,  PCI_VENDOR_ID_ATI,      PCI_DEVICE_ID_ATI_M64,          "Mach 64"}, \
 383         {0xff,  PCI_VENDOR_ID_WEITEK,   PCI_DEVICE_ID_WEITEK_P9000,     "P9000"}, \
 384         {0xff,  PCI_VENDOR_ID_WEITEK,   PCI_DEVICE_ID_WEITEK_P9100,     "P9100"}, \
 385         {0xff,  PCI_VENDOR_ID_CIRRUS,   PCI_DEVICE_ID_CIRRUS_5434_4,    "GD 5434"}, \
 386         {0xff,  PCI_VENDOR_ID_CIRRUS,   PCI_DEVICE_ID_CIRRUS_5434_8,    "GD 5434"}, \
 387         {0xff,  PCI_VENDOR_ID_CIRRUS,   PCI_DEVICE_ID_CIRRUS_6729,      "CL 6729"}, \
 388         {0xff,  PCI_VENDOR_ID_BUSLOGIC,PCI_DEVICE_ID_BUSLOGIC_946C,     "946C"}, \
 389         {0xff,  PCI_VENDOR_ID_N9,       PCI_DEVICE_ID_N9_I128,          "Imagine 128"}, \
 390         {0xff,  PCI_VENDOR_ID_AI,       PCI_DEVICE_ID_AI_M1435,         "M1435"}, \
 391         {0xff,  PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1449,         "M1449"}, \
 392         {0xff,  PCI_VENDOR_ID_AL,       PCI_DEVICE_ID_AL_M1451,         "M1451"}, \
 393         {0xff,  PCI_VENDOR_ID_TSENG,    PCI_DEVICE_ID_TSENG_W32P_2,     "ET4000W32P"}, \
 394         {0xff,  PCI_VENDOR_ID_TSENG,    PCI_DEVICE_ID_TSENG_W32P_b,     "ET4000W32P rev B"}, \
 395         {0xff,  PCI_VENDOR_ID_TSENG,    PCI_DEVICE_ID_TSENG_W32P_a,     "ET4000W32P rev A"}, \
 396         {0xff,  PCI_VENDOR_ID_CMD,      PCI_DEVICE_ID_CMD_640,          "640A"}, \
 397         {0xff,  PCI_VENDOR_ID_VISION,   PCI_DEVICE_ID_VISION_QD8500,    "QD-8500PCI"}, \
 398         {0xff,  PCI_VENDOR_ID_AMD,      PCI_DEVICE_ID_AMD_LANCE,        "79C970"}, \
 399         {0xff,  PCI_VENDOR_ID_VLSI,     PCI_DEVICE_ID_VLSI_82C593,      "82C593-FC1"}, \
 400         {0xff,  PCI_VENDOR_ID_ADL,      PCI_DEVICE_ID_ADL_2301,         "2301"}, \
 401         {0xff,  PCI_VENDOR_ID_SYMPHONY, PCI_DEVICE_ID_SYMPHONY_101,     "82C101"}, \
 402         {0xff,  PCI_VENDOR_ID_TRIDENT,  PCI_DEVICE_ID_TRIDENT_9420,     "TG 9420"}, \
 403         {0xff,  PCI_VENDOR_ID_CONTAQ,   PCI_DEVICE_ID_CONTAQ_82C599,    "82C599"} \
 404 }
 405 
 406 /* An item of this structure has the following meaning  */
 407 /* For each optimisation, the register address, the mask        */
 408 /* and value to write to turn it on.                    */
 409 /* There are 5 optimizations for the moment :           */
 410 /* Cache L2 write back best than write through          */
 411 /* Posted Write for CPU to PCI enable                   */
 412 /* Posted Write for CPU to MEMORY enable                */
 413 /* Posted Write for PCI to MEMORY enable                */
 414 /* PCI Burst enable                                     */
 415 
 416 /* Half of the bios I've meet don't allow you to turn   */
 417 /* that on, and you can gain more than 15% on graphic   */
 418 /* accesses using those optimisations...                */
 419 
 420 struct optimisation_type {
 421         char    *type;
 422         char    *off;
 423         char    *on;
 424 };
 425 
 426 #define OPTIMISATION_NUM 5
 427 #define OPTIMISATION_TYPE { \
 428         {"Cache L2","write trough","write back"}, \
 429         {"CPU-PCI posted write","off","on"}, \
 430         {"CPU-Memory posted write","off","on"}, \
 431         {"PCI-Memory posted write","off","on"}, \
 432         {"PCI burst","off","on"} \
 433 }
 434 
 435 struct bridge_mapping_type {
 436         unsigned char   address;
 437         unsigned char   mask;
 438         unsigned char   value;
 439 };
 440 
 441 /* Intel Neptune/Mercury/Saturn */
 442 /*      If the Internal cache is Write back,    */
 443 /*      the L2 cache must be write through !    */
 444 /*      I've to check out how to control that   */
 445 /*      for the moment, we won't touch the cache*/
 446 /* UMC 8891A Pentium chipset                    */
 447 /*      Why did you think UMC was cheaper ??    */
 448 /* OPTI 82C822                                  */
 449 /*      This is a dummy entry for my tests.     */
 450 /*      I have this chipset and no docs....     */   
 451 
 452 /* I'm gathering docs. If you can help......    */
 453 
 454 #define BRIDGE_MAPPING_NUM 3
 455 #define BRIDGE_MAPPING_TYPE { \
 456         {0x0    ,0x02   ,0x02   }, \
 457         {0x53   ,0x02   ,0x02   }, \
 458         {0x53   ,0x01   ,0x01   }, \
 459         {0x54   ,0x01   ,0x01   }, \
 460         {0x54   ,0x02   ,0x02   }, \
 461 \
 462         {0x50   ,0x10   ,0x00   }, \
 463         {0x51   ,0x40   ,0x40   }, \
 464         {0x0    ,0x0    ,0x0    }, \
 465         {0x0    ,0x0    ,0x0    }, \
 466         {0x0    ,0x0    ,0x0    }, \
 467 \
 468         {0x0    ,0x1    ,0x1    }, \
 469         {0x0    ,0x2    ,0x0    }, \
 470         {0x0    ,0x0    ,0x0    }, \
 471         {0x0    ,0x0    ,0x0    }, \
 472         {0x0    ,0x0    ,0x0    }  \
 473 }
 474 
 475 
 476 /* PCI BIOS */
 477 
 478 extern int pcibios_present (void);
 479 
 480 #define PCIBIOS_SUCCESSFUL              0x00
 481 #define PCIBIOS_FUNC_NOT_SUPPORTED      0x81
 482 #define PCIBIOS_BAD_VENDOR_ID           0x83
 483 #define PCIBIOS_DEVICE_NOT_FOUND        0x86
 484 #define PCIBIOS_BAD_REGISTER_NUMBER     0x87
 485 
 486 /*
 487  * The PCIBIOS calls all bit-field the device_function variable such that 
 488  * the bit fielding matches that of the bl register used in the actual
 489  * calls.
 490  */
 491 
 492 extern int pcibios_find_class (unsigned long class_code, unsigned short index, 
 493     unsigned char *bus, unsigned char *device_fn);
 494 extern int pcibios_find_device (unsigned short vendor, unsigned short device_id, 
 495     unsigned short index, unsigned char *bus, unsigned char *device_fn);
 496 extern int pcibios_read_config_byte (unsigned char bus,
 497     unsigned char device_fn, unsigned char where, unsigned char *value);
 498 extern int pcibios_read_config_word (unsigned char bus,
 499     unsigned char device_fn, unsigned char where, unsigned short *value);
 500 extern int pcibios_read_config_dword (unsigned char bus,
 501     unsigned char device_fn, unsigned char where, unsigned long *value);
 502 extern char *pcibios_strerror (int error);
 503 extern int pcibios_write_config_byte (unsigned char bus,
 504     unsigned char device_fn, unsigned char where, unsigned char value);
 505 extern int pcibios_write_config_word (unsigned char bus,
 506     unsigned char device_fn, unsigned char where, unsigned short value);
 507 extern pcibios_write_config_dword (unsigned char bus,
 508     unsigned char device_fn, unsigned char where, unsigned long value);
 509 #endif /* ndef PCI_H */
/* */
root/include/linux/pci.h

INCLUDED FROM
