root/include/asm-sparc/system.h

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INCLUDED FROM


DEFINITIONS

This source file includes following definitions.
  1. xchg_u32
  2. xchg_ptr

   1 #ifndef __SPARC_SYSTEM_H
   2 #define __SPARC_SYSTEM_H
   3 
   4 /*
   5  * System defines.. Note that this is included both from .c and .S
   6  * files, so it does only defines, not any C code.
   7  */
   8 
   9 /*
  10  * I wish the boot time image was as beautiful as the Alpha's
  11  * but no such luck. The icky PROM loads us at 0x0, and jumps
  12  * to magic address 0x4000 to start thing going. This means that
  13  * I can stick the pcb and user/kernel stacks in the area from
  14  * 0x0-0x4000 and be reasonably sure that this is sane.
  15  *
  16  * Sorry, I can't impress people with cool looking 64-bit values
  17  * yet. ;-)
  18  */
  19 
  20 #include <asm/openprom.h>
  21 
  22 #define INIT_PCB        0x00011fe0
  23 #define INIT_STACK      0x00013fe0
  24 #define START_ADDR      0x00004000
  25 #define START_SIZE      (32*1024)
  26 #define EMPTY_PGT       0x00001000
  27 #define EMPTY_PGE       0x00001000
  28 #define ZERO_PGE        0x00001000
  29 
  30 #ifndef __ASSEMBLY__
  31 
  32 extern void wrent(void *, unsigned long);
  33 extern void wrkgp(unsigned long);
  34 extern struct linux_romvec *romvec;
  35 
  36 #define halt() { romvec->pv_halt(); }
  37 #define move_to_user_mode() halt()
  38 #define switch_to(x) halt()
  39 
  40 #ifndef stbar  /* store barrier Sparc insn to synchronize stores in PSO */
  41 #define stbar() __asm__ __volatile__("stbar": : :"memory")
  42 #endif
  43 
  44 /* Changing the PIL on the sparc is a bit hairy. I'll figure out some
  45  * more optimized way of doing this soon. This is bletcherous code.
  46  */
  47 
  48 #define swpipl(__new_ipl) \
  49 ({ unsigned long __old_ipl, psr; \
  50 __asm__ __volatile__( \
  51         "rd %%psr, %0\n\t" : "=&r" (__old_ipl)); \
  52 __asm__ __volatile__( \
  53         "and %1, 15, %0\n\t" \
  54         "sll %0, 8, %0\n\t" \
  55         "or  %0, %2, %0\n\t" \
  56         "wr  %0, 0x0, %%psr\n\t" \
  57         : "=&r" (psr) \
  58         : "r" (__new_ipl), "r" (__old_ipl)); \
  59 __old_ipl = ((__old_ipl>>8)&15); \
  60 __old_ipl; })
  61 
  62 #define cli()                   swpipl(15)  /* 15 = no int's except nmi's */
  63 #define sti()                   swpipl(0)   /* same as alpha */
  64 #define save_flags(flags)       do { flags = swpipl(15); } while (0)
  65 #define restore_flags(flags)    swpipl(flags)
  66 
  67 #define iret() __asm__ __volatile__ ("jmp %%l1\n\t" \
  68                                      "rett %%l2\n\t": : :"memory")
  69 
  70 #define _set_gate(gate_addr,type,dpl,addr) \
  71 __asm__ __volatile__ ("nop\n\t")
  72 
  73 #define set_intr_gate(n,addr) \
  74         _set_gate(&idt[n],14,0,addr)
  75 
  76 #define set_trap_gate(n,addr) \
  77         _set_gate(&idt[n],15,0,addr)
  78 
  79 #define set_system_gate(n,addr) \
  80         _set_gate(&idt[n],15,3,addr)
  81 
  82 #define set_call_gate(a,addr) \
  83         _set_gate(a,12,3,addr)
  84 
  85 
  86 /* Must this be atomic? */
  87 
  88 extern inline void *xchg_u32(int * m, unsigned long val)
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  89 {
  90         unsigned long dummy;
  91 
  92         __asm__ __volatile__(
  93                 "ld [%1],%2\n\t"
  94                 "st %0, [%1]\n\t"
  95                 "or %%g0, %2, %0"
  96                 : "=r" (val), "=r" (m), "=r" (dummy)
  97                 : "0" (val));
  98         return (void *)val;
  99 }
 100 
 101 
 102 /* pointers are 32 bits on the sparc (at least the v8, and they'll work
 103  * on the V9 none the less). I don't need the xchg_u64 routine for now.
 104  */
 105 
 106 extern inline void *xchg_ptr(void *m, void *val)
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 107 {
 108         return (void *) xchg_u32((int *) m, (unsigned long) val);
 109 }
 110 
 111 
 112 
 113 #endif /* __ASSEMBLY__ */
 114 
 115 #endif

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