root/drivers/scsi/53c7,8xx.h

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   1 /*
   2  * NCR 53c{7,8}0x0 driver, header file
   3  *
   4  * Sponsored by
   5  *      iX Multiuser Multitasking Magazine
   6  *      Hannover, Germany
   7  *      hm@ix.de        
   8  *
   9  * Copyright 1993, Drew Eckhardt
  10  *      Visionary Computing 
  11  *      (Unix and Linux consulting and custom programming)
  12  *      drew@Colorado.EDU
  13  *      +1 (303) 786-7975
  14  *
  15  * TolerANT and SCSI SCRIPTS are registered trademarks of NCR Corporation.
  16  * 
  17  * PRE-ALPHA
  18  *
  19  * For more information, please consult 
  20  *
  21  * NCR 53C700/53C700-66
  22  * SCSI I/O Processor
  23  * Data Manual
  24  *
  25  * NCR 53C810
  26  * PCI-SCSI I/O Processor 
  27  * Data Manual
  28  *
  29  * NCR Microelectronics
  30  * 1635 Aeroplaza Drive
  31  * Colorado Springs, CO 80916
  32  * +1 (719) 578-3400
  33  *
  34  * Toll free literature number
  35  * +1 (800) 334-5454
  36  *
  37  */
  38 
  39 #ifndef NCR53c7x0_H
  40 #define NCR53c7x0_H
  41 
  42 
  43 /* 
  44  * Prevent name space pollution in hosts.c, and only provide the 
  45  * define we need to get the NCR53c7x0 driver into the host template
  46  * array.
  47  */
  48 
  49 #ifdef HOSTS_C 
  50 #include <linux/scsicam.h>
  51 extern int NCR53c7xx_abort(Scsi_Cmnd *);
  52 extern int NCR53c7xx_detect(Scsi_Host_Template *tpnt);
  53 extern int NCR53c7xx_queue_command(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  54 extern int NCR53c7xx_reset(Scsi_Cmnd *);
  55 
  56 #define NCR53c7xx {NULL, NULL, "NCR53c{7,8}xx (rel 3)", NCR53c7xx_detect,       \
  57         NULL, NULL,                                             \
  58         NULL, NCR53c7xx_queue_command, NCR53c7xx_abort, NCR53c7xx_reset,\
  59         NULL, scsicam_bios_param,                                       \
  60         /* can queue */ 1, /* id */ 7, 255 /* old SG_ALL */,            \
  61         /* cmd per lun */ 1 , 0, 0, DISABLE_CLUSTERING}
  62 #else
  63 /* Register addresses, ordered numerically */
  64 
  65 
  66 /* SCSI control 0 rw, default = 0xc0 */ 
  67 #define SCNTL0_REG              0x00    
  68 #define SCNTL0_ARB1             0x80    /* 0 0 = simple arbitration */
  69 #define SCNTL0_ARB2             0x40    /* 1 1 = full arbitration */
  70 #define SCNTL0_STRT             0x20    /* Start Sequence */
  71 #define SCNTL0_WATN             0x10    /* Select with ATN */
  72 #define SCNTL0_EPC              0x08    /* Enable parity checking */
  73 /* Bit 2 is reserved on 800 series chips */
  74 #define SCNTL0_EPG_700          0x04    /* Enable parity generation */
  75 #define SCNTL0_AAP              0x02    /*  ATN/ on parity error */
  76 #define SCNTL0_TRG              0x01    /* Target mode */
  77 
  78 /* SCSI control 1 rw, default = 0x00 */
  79 
  80 #define SCNTL1_REG              0x01    
  81 #define SCNTL1_EXC              0x80    /* Extra Clock Cycle of Data setup */
  82 #define SCNTL1_ADB              0x40    /*  contents of SODL on bus */
  83 #define SCNTL1_ESR_700          0x20    /* Enable SIOP response to selection 
  84                                            and reselection */
  85 #define SCNTL1_DHP_800          0x20    /* Disable halt on parity error or ATN
  86                                            target mode only */
  87 #define SCNTL1_CON              0x10    /* Connected */
  88 #define SCNTL1_RST              0x08    /*  SCSI RST/ */
  89 #define SCNTL1_AESP             0x04    /* Force bad parity */
  90 #define SCNTL1_SND_700          0x02    /* Start SCSI send */
  91 #define SCNTL1_IARB_800         0x02    /* Immediate Arbitration, start
  92                                            arbitration immediately after
  93                                            busfree is detected */
  94 #define SCNTL1_RCV_700          0x01    /* Start SCSI receive */
  95 #define SCNTL1_SST_800          0x01    /* Start SCSI transfer */
  96 
  97 /* SCSI control 2 rw, */
  98 
  99 #define SCNTL2_REG_800          0x02    
 100 #define SCNTL2_800_SDU          0x80    /* SCSI disconnect unexpected */
 101 
 102 /* SCSI control 3 rw */
 103 
 104 #define SCNTL3_REG_800          0x03    
 105 #define SCNTL3_800_SCF_SHIFT    4
 106 #define SCNTL3_800_SCF_MASK     0x70
 107 #define SCNTL3_800_SCF2         0x40    /* Synchronous divisor */
 108 #define SCNTL3_800_SCF1         0x20    /* 0x00 = SCLK/3 */
 109 #define SCNTL3_800_SCF0         0x10    /* 0x10 = SCLK/1 */
 110                                         /* 0x20 = SCLK/1.5 
 111                                            0x30 = SCLK/2 
 112                                            0x40 = SCLK/3 */
 113             
 114 #define SCNTL3_800_CCF_SHIFT    0
 115 #define SCNTL3_800_CCF_MASK     0x07
 116 #define SCNTL3_800_CCF2         0x04    /* 0x00 50.01 to 66 */
 117 #define SCNTL3_800_CCF1         0x02    /* 0x01 16.67 to 25 */
 118 #define SCNTL3_800_CCF0         0x01    /* 0x02 25.01 - 37.5 
 119                                            0x03 37.51 - 50 
 120                                            0x04 50.01 - 66 */
 121 
 122 /*  
 123  * SCSI destination ID rw - the appropriate bit is set for the selected
 124  * target ID.  This is written by the SCSI SCRIPTS processor.
 125  * default = 0x00
 126  */
 127 #define SDID_REG_700            0x02    
 128 #define SDID_REG_800            0x06
 129 
 130 #define GP_REG_800              0x07    /* General purpose IO */
 131 #define GP_800_IO1              0x02
 132 #define GP_800_IO2              0x01
 133 
 134 
 135 /* SCSI interrupt enable rw, default = 0x00 */
 136 #define SIEN_REG_700            0x03    
 137 #define SIEN0_REG_800           0x40
 138 #define SIEN_MA                 0x80    /* Phase mismatch (ini) or ATN (tgt) */
 139 #define SIEN_FC                 0x40    /* Function complete */
 140 #define SIEN_700_STO            0x20    /* Selection or reselection timeout */
 141 #define SIEN_800_SEL            0x20    /* Selected */
 142 #define SIEN_700_SEL            0x10    /* Selected or reselected */
 143 #define SIEN_800_RESEL          0x10    /* Reselected */
 144 #define SIEN_SGE                0x08    /* SCSI gross error */
 145 #define SIEN_UDC                0x04    /* Unexpected disconnect */
 146 #define SIEN_RST                0x02    /* SCSI RST/ received */
 147 #define SIEN_PAR                0x01    /* Parity error */
 148 
 149 /* 
 150  * SCSI chip ID rw
 151  * NCR53c700 : 
 152  *      When arbitrating, the highest bit is used, when reselection or selection
 153  *      occurs, the chip responds to all IDs for which a bit is set.
 154  *      default = 0x00 
 155  * NCR53c810 : 
 156  *      Uses bit mapping
 157  */
 158 #define SCID_REG                0x04    
 159 /* Bit 7 is reserved on 800 series chips */
 160 #define SCID_800_RRE            0x40    /* Enable response to reselection */
 161 #define SCID_800_SRE            0x20    /* Enable response to selection */
 162 /* Bits four and three are reserved on 800 series chips */
 163 #define SCID_800_ENC_MASK       0x07    /* Encoded SCSI ID */
 164 
 165 /* SCSI transfer rw, default = 0x00 */
 166 #define SXFER_REG               0x05
 167 #define SXFER_DHP               0x80    /* Disable halt on parity */
 168 
 169 #define SXFER_TP2               0x40    /* Transfer period msb */
 170 #define SXFER_TP1               0x20
 171 #define SXFER_TP0               0x10    /* lsb */
 172 #define SXFER_TP_MASK           0x70
 173 #define SXFER_TP_SHIFT          4
 174 #define SXFER_TP_4              0x00    /* Divisors */
 175 #define SXFER_TP_5              0x10
 176 #define SXFER_TP_6              0x20
 177 #define SXFER_TP_7              0x30
 178 #define SXFER_TP_8              0x40
 179 #define SXFER_TP_9              0x50
 180 #define SXFER_TP_10             0x60
 181 #define SXFER_TP_11             0x70
 182 
 183 #define SXFER_MO3               0x08    /* Max offset msb */
 184 #define SXFER_MO2               0x04
 185 #define SXFER_MO1               0x02
 186 #define SXFER_MO0               0x01    /* lsb */
 187 #define SXFER_MO_MASK           0x0f
 188 #define SXFER_MO_SHIFT          0
 189 
 190 /* 
 191  * SCSI output data latch rw
 192  * The contents of this register are driven onto the SCSI bus when 
 193  * the Assert Data Bus bit of the SCNTL1 register is set and 
 194  * the CD, IO, and MSG bits of the SOCL register match the SCSI phase
 195  */
 196 #define SODL_REG_700            0x06    
 197 #define SODL_REG_800            0x54
 198 
 199 
 200 /* 
 201  * SCSI output control latch rw, default = 0 
 202  * Note that when the chip is being manually programmed as an initiator,
 203  * the MSG, CD, and IO bits must be set correctly for the phase the target
 204  * is driving the bus in.  Otherwise no data transfer will occur due to 
 205  * phase mismatch.
 206  */
 207 
 208 #define SBCL_REG                0x0b
 209 #define SBCL_REQ                0x80    /*  REQ */
 210 #define SBCL_ACK                0x40    /*  ACK */
 211 #define SBCL_BSY                0x20    /*  BSY */
 212 #define SBCL_SEL                0x10    /*  SEL */
 213 #define SBCL_ATN                0x08    /*  ATN */
 214 #define SBCL_MSG                0x04    /*  MSG */
 215 #define SBCL_CD                 0x02    /*  C/D */
 216 #define SBCL_IO                 0x01    /*  I/O */
 217 #define SBCL_PHASE_CMDOUT       SBCL_CD
 218 #define SBCL_PHASE_DATAIN       SBCL_IO
 219 #define SBCL_PHASE_DATAOUT      0
 220 #define SBCL_PHASE_MSGIN        (SBCL_CD|SBCL_IO|SBCL_MSG)
 221 #define SBCL_PHASE_MSGOUT       (SBCL_CD|SBCL_MSG)
 222 #define SBCL_PHASE_STATIN       (SBCL_CD|SBCL_IO)
 223 #define SBCL_PHASE_MASK         (SBCL_CD|SBCL_IO|SBCL_MSG)
 224 
 225 /* 
 226  * SCSI first byte received latch ro 
 227  * This register contains the first byte received during a block MOVE 
 228  * SCSI SCRIPTS instruction, including
 229  * 
 230  * Initiator mode       Target mode
 231  * Message in           Command
 232  * Status               Message out
 233  * Data in              Data out
 234  *
 235  * It also contains the selecting or reselecting device's ID and our 
 236  * ID.
 237  *
 238  * Note that this is the register the various IF conditionals can 
 239  * operate on.
 240  */
 241 #define SFBR_REG                0x08    
 242 
 243 /* 
 244  * SCSI input data latch ro
 245  * In initiator mode, data is latched into this register on the rising
 246  * edge of REQ/. In target mode, data is latched on the rising edge of 
 247  * ACK/
 248  */
 249 #define SIDL_REG_700            0x09
 250 #define SIDL_REG_800            0x50
 251 
 252 /* 
 253  * SCSI bus data lines ro 
 254  * This register reflects the instantaneous status of the SCSI data 
 255  * lines.  Note that SCNTL0 must be set to disable parity checking, 
 256  * otherwise reading this register will latch new parity.
 257  */
 258 #define SBDL_REG_700            0x0a
 259 #define SBDL_REG_800            0x58
 260 
 261 #define SSID_REG_800            0x0a
 262 #define SSID_800_VAL            0x80    /* Exactly two bits asserted at sel */
 263 #define SSID_800_ENCID_MASK     0x07    /* Device which performed operation */
 264 
 265 
 266 /* 
 267  * SCSI bus control lines rw, 
 268  * instantaneous readout of control lines 
 269  */
 270 #define SOCL_REG                0x0b    
 271 #define SOCL_REQ                0x80    /*  REQ ro */
 272 #define SOCL_ACK                0x40    /*  ACK ro */
 273 #define SOCL_BSY                0x20    /*  BSY ro */
 274 #define SOCL_SEL                0x10    /*  SEL ro */
 275 #define SOCL_ATN                0x08    /*  ATN ro */
 276 #define SOCL_MSG                0x04    /*  MSG ro */
 277 #define SOCL_CD                 0x02    /*  C/D ro */
 278 #define SOCL_IO                 0x01    /*  I/O ro */
 279 /* 
 280  * Synchronous SCSI Clock Control bits 
 281  * 0 - set by DCNTL 
 282  * 1 - SCLK / 1.0
 283  * 2 - SCLK / 1.5
 284  * 3 - SCLK / 2.0 
 285  */
 286 #define SBCL_SSCF1              0x02    /* wo, -66 only */
 287 #define SBCL_SSCF0              0x01    /* wo, -66 only */
 288 #define SBCL_SSCF_MASK          0x03
 289 
 290 /* 
 291  * XXX note : when reading the DSTAT and STAT registers to clear interrupts,
 292  * insure that 10 clocks elapse between the two  
 293  */
 294 /* DMA status ro */
 295 #define DSTAT_REG               0x0c    
 296 #define DSTAT_DFE               0x80    /* DMA FIFO empty */
 297 #define DSTAT_800_MDPE          0x40    /* Master Data Parity Error */
 298 #define DSTAT_800_BF            0x20    /* Bus Fault */
 299 #define DSTAT_ABRT              0x10    /* Aborted - set on error */
 300 #define DSTAT_SSI               0x08    /* SCRIPTS single step interrupt */
 301 #define DSTAT_SIR               0x04    /* SCRIPTS interrupt received - 
 302                                            set when INT instruction is 
 303                                            executed */
 304 #define DSTAT_WTD               0x02    /* Watchdog timeout detected */
 305 #define DSTAT_OPC               0x01    /* Illegal instruction */
 306 #define DSTAT_800_IID           0x01    /* Same thing, different name */
 307 
 308 
 309 #define SSTAT0_REG              0x0d    /* SCSI status 0 ro */
 310 #define SIST0_REG_800           0x42    
 311 #define SSTAT0_MA               0x80    /* ini : phase mismatch,
 312                                          * tgt : ATN/ asserted 
 313                                          */
 314 #define SSTAT0_CMP              0x40    /* function complete */
 315 #define SSTAT0_700_STO          0x20    /* Selection or reselection timeout */
 316 #define SIST0_800_SEL           0x20    /* Selected */
 317 #define SSTAT0_700_SEL          0x10    /* Selected or reselected */
 318 #define SIST0_800_RSL           0x10    /* Reselected */
 319 #define SSTAT0_SGE              0x08    /* SCSI gross error */
 320 #define SSTAT0_UDC              0x04    /* Unexpected disconnect */
 321 #define SSTAT0_RST              0x02    /* SCSI RST/ received */
 322 #define SSTAT0_PAR              0x01    /* Parity error */
 323 
 324 #define SSTAT1_REG              0x0e    /* SCSI status 1 ro */
 325 #define SSTAT1_ILF              0x80    /* SIDL full */
 326 #define SSTAT1_ORF              0x40    /* SODR full */
 327 #define SSTAT1_OLF              0x20    /* SODL full */
 328 #define SSTAT1_AIP              0x10    /* Arbitration in progress */
 329 #define SSTAT1_LOA              0x08    /* Lost arbitration */
 330 #define SSTAT1_WOA              0x04    /* Won arbitration */
 331 #define SSTAT1_RST              0x02    /* Instant readout of RST/ */
 332 #define SSTAT1_SDP              0x01    /* Instant readout of SDP/ */
 333 
 334 #define SSTAT2_REG              0x0f    /* SCSI status 2 ro */
 335 #define SSTAT2_FF3              0x80    /* number of bytes in synchronous */
 336 #define SSTAT2_FF2              0x40    /* data FIFO */
 337 #define SSTAT2_FF1              0x20    
 338 #define SSTAT2_FF0              0x10
 339 #define SSTAT2_FF_MASK          0xf0
 340 
 341 /* 
 342  * Latched signals, latched on the leading edge of REQ/ for initiators,
 343  * ACK/ for targets.
 344  */
 345 #define SSTAT2_SDP              0x08    /* SDP */
 346 #define SSTAT2_MSG              0x04    /* MSG */
 347 #define SSTAT2_CD               0x02    /* C/D */
 348 #define SSTAT2_IO               0x01    /* I/O */
 349 
 350 
 351 /* NCR53c700-66 only */
 352 #define SCRATCHA_REG_00         0x10    /* through  0x13 Scratch A rw */
 353 /* NCR53c710 and higher */
 354 #define DSA_REG                 0x10    /* DATA structure address */
 355 
 356 #define CTEST0_REG_700          0x14    /* Chip test 0 ro */
 357 #define CTEST0_REG_800          0x18    /* Chip test 0 rw, general purpose */
 358 /* 0x80 - 0x04 are reserved */
 359 #define CTEST0_700_RTRG         0x02    /* Real target mode */
 360 #define CTEST0_700_DDIR         0x01    /* Data direction, 1 = 
 361                                          * SCSI bus to host, 0  =
 362                                          * host to SCSI.
 363                                          */
 364 
 365 #define CTEST1_REG_700          0x15    /* Chip test 1 ro */
 366 #define CTEST1_REG_800          0x19    /* Chip test 1 ro */
 367 #define CTEST1_FMT3             0x80    /* Identify which byte lanes are empty */
 368 #define CTEST1_FMT2             0x40    /* in the DMA FIFO */
 369 #define CTEST1_FMT1             0x20
 370 #define CTEST1_FMT0             0x10
 371 
 372 #define CTEST1_FFL3             0x08    /* Identify which bytes lanes are full */
 373 #define CTEST1_FFL2             0x04    /* in the DMA FIFO */
 374 #define CTEST1_FFL1             0x02
 375 #define CTEST1_FFL0             0x01
 376 
 377 #define CTEST2_REG_700          0x16    /* Chip test 2 ro */
 378 #define CTEST2_REG_800          0x1a    /* Chip test 2 ro */
 379 
 380 #define CTEST2_800_DDIR         0x80    /* 1 = SCSI->host */
 381 #define CTEST2_800_SIGP         0x40    /* A copy of SIGP in ISTAT.
 382                                            Reading this register clears */
 383 #define CTEST2_800_CIO          0x20    /* Configured as IO */.
 384 #define CTEST2_800_CM           0x10    /* Configured as memory */
 385 
 386 /* 0x80 - 0x40 are reserved on 700 series chips */
 387 #define CTEST2_700_SOFF         0x20    /* SCSI Offset Compare,
 388                                          * As an initiator, this bit is 
 389                                          * one when the synchronous offset
 390                                          * is zero, as a target this bit 
 391                                          * is one when the synchronous 
 392                                          * offset is at the maximum
 393                                          * defined in SXFER
 394                                          */
 395 #define CTEST2_700_SFP          0x10    /* SCSI FIFO parity bit,
 396                                          * reading CTEST3 unloads a byte
 397                                          * from the FIFO and sets this
 398                                          */
 399 #define CTEST2_700_DFP          0x08    /* DMA FIFO parity bit,
 400                                          * reading CTEST6 unloads a byte
 401                                          * from the FIFO and sets this
 402                                          */
 403 #define CTEST2_TEOP             0x04    /* SCSI true end of process,
 404                                          * indicates a totally finished
 405                                          * transfer
 406                                          */
 407 #define CTEST2_DREQ             0x02    /* Data request signal */
 408 /* 0x01 is reserved on 700 series chips */
 409 #define CTEST2_800_DACK         0x01    
 410 
 411 /* 
 412  * Chip test 3 ro 
 413  * Unloads the bottom byte of the eight deep SCSI synchronous FIFO,
 414  * check SSTAT2 FIFO full bits to determine size.  Note that a GROSS
 415  * error results if a read is attempted on this register.  Also note 
 416  * that 16 and 32 bit reads of this register will cause corruption.
 417  */
 418 #define CTEST3_REG_700          0x17    
 419 /*  Chip test 3 rw */
 420 #define CTEST3_REG_800          0x1b
 421 #define CTEST3_800_V3           0x80    /* Chip revision */
 422 #define CTEST3_800_V2           0x40
 423 #define CTEST3_800_V1           0x20
 424 #define CTEST3_800_V0           0x10
 425 #define CTEST3_800_FLF          0x08    /* Flush DMA FIFO */
 426 #define CTEST3_800_CLF          0x04    /* Clear DMA FIFO */
 427 #define CTEST3_800_FM           0x02    /* Fetch mode pin */
 428 /* bit 0 is reserved on 800 series chips */
 429 
 430 #define CTEST4_REG_700          0x18    /* Chip test 4 rw */
 431 #define CTEST4_REG_800          0x21    /* Chip test 4 rw */
 432 /* 0x80 is reserved on 700 series chips */
 433 #define CTEST4_800_BDIS         0x80    /* Burst mode disable */
 434 #define CTEST4_ZMOD             0x40    /* High impedance mode */
 435 #define CTEST4_SZM              0x20    /* SCSI bus high impedance */
 436 #define CTEST4_700_SLBE         0x10    /* SCSI loopback enabled */
 437 #define CTEST4_800_SRTM         0x10    /* Shadow Register Test Mode */
 438 #define CTEST4_700_SFWR         0x08    /* SCSI FIFO write enable, 
 439                                          * redirects writes from SODL
 440                                          * to the SCSI FIFO.
 441                                          */
 442 #define CTEST4_800_MPEE         0x08    /* Enable parity checking
 443                                            during master cycles on PCI
 444                                            bus */
 445 
 446 /* 
 447  * These bits send the contents of the CTEST6 register to the appropriate
 448  * byte lane of the 32 bit DMA FIFO.  Normal operation is zero, otherwise 
 449  * the high bit means the low two bits select the byte lane.
 450  */
 451 #define CTEST4_FBL2             0x04    
 452 #define CTEST4_FBL1             0x02
 453 #define CTEST4_FBL0             0x01    
 454 #define CTEST4_FBL_MASK         0x07
 455 #define CTEST4_FBL_0            0x04    /* Select DMA FIFO byte lane 0 */
 456 #define CTEST4_FBL_1            0x05    /* Select DMA FIFO byte lane 1 */
 457 #define CTEST4_FBL_2            0x06    /* Select DMA FIFO byte lane 2 */
 458 #define CTEST4_FBL_3            0x07    /* Select DMA FIFO byte lane 3 */
 459 #define CTEST4_800_SAVE         (CTEST4_800_BDIS)
 460 
 461 
 462 #define CTEST5_REG_700          0x19    /* Chip test 5 rw */
 463 #define CTEST5_REG_800          0x22    /* Chip test 5 rw */
 464 /* 
 465  * Clock Address Incrementor.  When set, it increments the 
 466  * DNAD register to the next bus size boundary.  It automatically 
 467  * resets itself when the operation is complete.
 468  */
 469 #define CTEST5_ADCK             0x80
 470 /*
 471  * Clock Byte Counter.  When set, it decrements the DBC register to
 472  * the next bus size boundary.
 473  */
 474 #define CTEST5_BBCK             0x40
 475 /*
 476  * Reset SCSI Offset.  Setting this bit to 1 clears the current offset
 477  * pointer in the SCSI synchronous offset counter (SSTAT).  This bit
 478  * is set to 1 if a SCSI Gross Error Condition occurs.  The offset should
 479  * be cleared when a synchronous transfer fails.  When written, it is 
 480  * automatically cleared after the SCSI synchronous offset counter is 
 481  * reset.
 482  */
 483 /* Bit 5 is reserved on 800 series chips */
 484 #define CTEST5_700_ROFF         0x20
 485 /* 
 486  * Master Control for Set or Reset pulses. When 1, causes the low 
 487  * four bits of register to set when set, 0 causes the low bits to
 488  * clear when set.
 489  */
 490 #define CTEST5_MASR             0x10    
 491 #define CTEST5_DDIR             0x08    /* DMA direction */
 492 /*
 493  * Bits 2-0 are reserved on 800 series chips
 494  */
 495 #define CTEST5_700_EOP          0x04    /* End of process */
 496 #define CTEST5_700_DREQ         0x02    /* Data request */
 497 #define CTEST5_700_DACK         0x01    /* Data acknowledge */
 498 
 499 /* 
 500  * Chip test 6 rw - writing to this register writes to the byte 
 501  * lane in the DMA FIFO as determined by the FBL bits in the CTEST4
 502  * register.
 503  */
 504 #define CTEST6_REG_700          0x1a
 505 #define CTEST6_REG_800          0x23
 506 
 507 #define CTEST7_REG              0x1b    /* Chip test 7 rw */
 508 /* 0x80 - 0x40 are reserved on NCR53c700 and NCR53c700-66 chips */
 509 #define CTEST7_10_CDIS          0x80    /* Cache burst disable */
 510 #define CTEST7_10_SC1           0x40    /* Snoop control bits */
 511 #define CTEST7_10_SC0           0x20    
 512 #define CTEST7_10_SC_MASK       0x60
 513 /* 0x20 is reserved on the NCR53c700 */
 514 #define CTEST7_0060_FM          0x20    /* Fetch mode */
 515 #define CTEST7_STD              0x10    /* Selection timeout disable */
 516 #define CTEST7_DFP              0x08    /* DMA FIFO parity bit for CTEST6 */
 517 #define CTEST7_EVP              0x04    /* 1 = host bus even parity, 0 = odd */
 518 #define CTEST7_10_TT1           0x02    /* Transfer type */
 519 #define CTEST7_00_DC            0x02    /* Set to drive DC low during instruction 
 520                                            fetch */
 521 #define CTEST7_DIFF             0x01    /* Differential mode */
 522 
 523 #define CTEST7_SAVE ( CTEST7_EVP | CTEST7_DIFF )
 524 
 525 
 526 #define TEMP_REG                0x1c    /* through 0x1f Temporary stack rw */
 527 
 528 #define DFIFO_REG               0x20    /* DMA FIFO rw */
 529 /* 
 530  * 0x80 is reserved on the NCR53c710, the CLF and FLF bits have been
 531  * moved into the CTEST8 register.
 532  */
 533 #define DFIFO_00_FLF            0x80    /* Flush DMA FIFO to memory */
 534 #define DFIFO_00_CLF            0x40    /* Clear DMA and SCSI FIFOs */
 535 #define DFIFO_BO6               0x40
 536 #define DFIFO_BO5               0x20
 537 #define DFIFO_BO4               0x10
 538 #define DFIFO_BO3               0x08
 539 #define DFIFO_BO2               0x04 
 540 #define DFIFO_BO1               0x02
 541 #define DFIFO_BO0               0x01
 542 #define DFIFO_10_BO_MASK        0x7f    /* 7 bit counter */
 543 #define DFIFO_00_BO_MASK        0x3f    /* 6 bit counter */
 544 
 545 /* 
 546  * Interrupt status rw 
 547  * Note that this is the only register which can be read while SCSI
 548  * SCRIPTS are being executed.
 549  */
 550 #define ISTAT_REG_700           0x21
 551 #define ISTAT_REG_800           0x14
 552 #define ISTAT_ABRT              0x80    /* Software abort, write 
 553                                          *1 to abort, wait for interrupt. */
 554 /* 0x40 and 0x20 are reserved on NCR53c700 and NCR53c700-66 chips */
 555 #define ISTAT_10_SRST           0x40    /* software reset */
 556 #define ISTAT_10_SIGP           0x20    /* signal script */
 557 /* 0x10 is reserved on NCR53c700 series chips */
 558 #define ISTAT_800_SEM           0x10    /* semaphore */
 559 #define ISTAT_CON               0x08    /* 1 when connected */
 560 #define ISTAT_800_INTF          0x04    /* Interrupt on the fly */
 561 #define ISTAT_700_PRE           0x04    /* Pointer register empty.
 562                                          * Set to 1 when DSPS and DSP
 563                                          * registers are empty in pipeline
 564                                          * mode, always set otherwise.
 565                                          */
 566 #define ISTAT_SIP               0x02    /* SCSI interrupt pending from
 567                                          * SCSI portion of SIOP see
 568                                          * SSTAT0
 569                                          */
 570 #define ISTAT_DIP               0x01    /* DMA interrupt pending 
 571                                          * see DSTAT
 572                                          */
 573 
 574 /* NCR53c700-66 and NCR53c710 only */
 575 #define CTEST8_REG              0x22    /* Chip test 8 rw */
 576 #define CTEST8_0066_EAS         0x80    /* Enable alternate SCSI clock,
 577                                          * ie read from SCLK/ rather than CLK/
 578                                          */
 579 #define CTEST8_0066_EFM         0x40    /* Enable fetch and master outputs */
 580 #define CTEST8_0066_GRP         0x20    /* Generate Receive Parity for 
 581                                          * pass through.  This insures that 
 582                                          * bad parity won't reach the host 
 583                                          * bus.
 584                                          */
 585 #define CTEST8_0066_TE          0x10    /* TolerANT enable.  Enable 
 586                                          * active negation, should only
 587                                          * be used for slow SCSI 
 588                                          * non-differential.
 589                                          */
 590 #define CTEST8_0066_HSC         0x08    /* Halt SCSI clock */
 591 #define CTEST8_0066_SRA         0x04    /* Shorten REQ/ACK filtering,
 592                                          * must be set for fast SCSI-II
 593                                          * speeds.
 594                                          */
 595 #define CTEST8_0066_DAS         0x02    /* Disable automatic target/initiator
 596                                          * switching.
 597                                          */
 598 #define CTEST8_0066_LDE         0x01    /* Last disconnect enable.
 599                                          * The status of pending 
 600                                          * disconnect is maintained by
 601                                          * the core, eliminating
 602                                          * the possibility of missing a 
 603                                          * selection or reselection
 604                                          * while waiting to fetch a 
 605                                          * WAIT DISCONNECT opcode.
 606                                          */
 607 
 608 #define CTEST8_10_V3            0x80    /* Chip revision */
 609 #define CTEST8_10_V2            0x40
 610 #define CTEST8_10_V1            0x20    
 611 #define CTEST8_10_V0            0x10
 612 #define CTEST8_10_V_MASK        0xf0    
 613 #define CTEST8_10_FLF           0x08    /* Flush FIFOs */
 614 #define CTEST8_10_CLF           0x04    /* Clear FIFOs */
 615 #define CTEST8_10_FM            0x02    /* Fetch pin mode */
 616 #define CTEST8_10_SM            0x01    /* Snoop pin mode */
 617 
 618 
 619 /* 
 620  * The CTEST9 register may be used to differentiate between a
 621  * NCR53c700 and a NCR53c710.  
 622  *
 623  * Write 0xff to this register.
 624  * Read it.
 625  * If the contents are 0xff, it is a NCR53c700
 626  * If the contents are 0x00, it is a NCR53c700-66 first revision
 627  * If the contents are some other value, it is some other NCR53c700-66
 628  */
 629 #define CTEST9_REG_00           0x23    /* Chip test 9 ro */
 630 #define LCRC_REG_10             0x23    
 631 
 632 /*
 633  * 0x24 through 0x27 are the DMA byte counter register.  Instructions
 634  * write their high 8 bits into the DCMD register, the low 24 bits into
 635  * the DBC register.
 636  *
 637  * Function is dependent on the command type being executed.
 638  */
 639 
 640  
 641 #define DBC_REG                 0x24
 642 /* 
 643  * For Block Move Instructions, DBC is a 24 bit quantity representing 
 644  *     the number of bytes to transfer.
 645  * For Transfer Control Instructions, DBC is bit fielded as follows : 
 646  */
 647 /* Bits 20 - 23 should be clear */
 648 #define DBC_TCI_TRUE            (1 << 19)       /* Jump when true */
 649 #define DBC_TCI_COMPARE_DATA    (1 << 18)       /* Compare data */
 650 #define DBC_TCI_COMPARE_PHASE   (1 << 17)       /* Compare phase with DCMD field */
 651 #define DBC_TCI_WAIT_FOR_VALID  (1 << 16)       /* Wait for REQ */
 652 /* Bits 8 - 15 are reserved on some implementations ? */
 653 #define DBC_TCI_MASK_MASK       0xff00          /* Mask for data compare */
 654 #define DBC_TCI_MASK_SHIFT      8
 655 #define DBC_TCI_DATA_MASK       0xff            /* Data to be compared */ 
 656 #define DBC_TCI_DATA_SHIFT      0
 657 
 658 #define DBC_RWRI_IMMEDIATE_MASK 0xff00          /* Immediate data */
 659 #define DBC_RWRI_IMMEDIATE_SHIFT 8              /* Amount to shift */
 660 #define DBC_RWRI_ADDRESS_MASK   0x3f0000        /* Register address */
 661 #define DBC_RWRI_ADDRESS_SHIFT  16
 662 
 663 
 664 /*
 665  * DMA command r/w
 666  */
 667 #define DCMD_REG                0x27    
 668 #define DCMD_TYPE_MASK          0xc0    /* Masks off type */
 669 #define DCMD_TYPE_BMI           0x00    /* Indicates a Block Move instruction */
 670 #define DCMD_BMI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 671 #define DCMD_BMI_CD             0x02    /* the phase for the block MOVE      */
 672 #define DCMD_BMI_MSG            0x04    /* instruction                       */
 673 
 674 #define DCMD_BMI_OP_MASK        0x18    /* mask for opcode */
 675 #define DCMD_BMI_OP_MOVE_T      0x00    /* MOVE */
 676 #define DCMD_BMI_OP_MOVE_I      0x08    /* MOVE Initiator */
 677 
 678 #define DCMD_BMI_INDIRECT       0x20    /*  Indirect addressing */
 679 
 680 #define DCMD_TYPE_TCI           0x80    /* Indicates a Transfer Control 
 681                                            instruction */
 682 #define DCMD_TCI_IO             0x01    /* I/O, CD, and MSG bits selecting   */
 683 #define DCMD_TCI_CD             0x02    /* the phase for the block MOVE      */
 684 #define DCMD_TCI_MSG            0x04    /* instruction                       */
 685 #define DCMD_TCI_OP_MASK        0x38    /* mask for opcode */
 686 #define DCMD_TCI_OP_JUMP        0x00    /* JUMP */
 687 #define DCMD_TCI_OP_CALL        0x08    /* CALL */
 688 #define DCMD_TCI_OP_RETURN      0x10    /* RETURN */
 689 #define DCMD_TCI_OP_INT         0x18    /* INT */
 690 
 691 #define DCMD_TYPE_RWRI          0x40    /* Indicates I/O or register Read/Write
 692                                            instruction */
 693 #define DCMD_RWRI_OPC_MASK      0x38    /* Opcode mask */
 694 #define DCMD_RWRI_OPC_WRITE     0x28    /* Write SFBR to register */
 695 #define DCMD_RWRI_OPC_READ      0x30    /* Read register to SFBR */
 696 #define DCMD_RWRI_OPC_MODIFY    0x38    /* Modify in place */
 697 
 698 #define DCMD_RWRI_OP_MASK       0x07
 699 #define DCMD_RWRI_OP_MOVE       0x00
 700 #define DCMD_RWRI_OP_SHL        0x01
 701 #define DCMD_RWRI_OP_OR         0x02
 702 #define DCMD_RWRI_OP_XOR        0x03
 703 #define DCMD_RWRI_OP_AND        0x04
 704 #define DCMD_RWRI_OP_SHR        0x05
 705 #define DCMD_RWRI_OP_ADD        0x06
 706 #define DCMD_RWRI_OP_ADDC       0x07
 707 
 708 #define DCMD_TYPE_MMI           0xc0    /* Indicates a Memory Move instruction 
 709                                            (three longs) */
 710 
 711 
 712 #define DNAD_REG                0x28    /* through 0x2b DMA next address for 
 713                                            data */
 714 #define DSP_REG                 0x2c    /* through 0x2f DMA SCRIPTS pointer rw */
 715 #define DSPS_REG                0x30    /* through 0x33 DMA SCRIPTS pointer 
 716                                            save rw */
 717 #define DMODE_REG_00            0x34    /* DMA mode rw */
 718 #define DMODE_00_BL1    0x80    /* Burst length bits */
 719 #define DMODE_00_BL0    0x40
 720 #define DMODE_BL_MASK   0xc0
 721 /* Burst lengths (800) */
 722 #define DMODE_BL_2      0x00    /* 2 transfer */
 723 #define DMODE_BL_4      0x40    /* 4 transfers */
 724 #define DMODE_BL_8      0x80    /* 8 transfers */
 725 #define DMODE_BL_16     0xc0    /* 16 transfers */
 726 
 727 #define DMODE_700_BW16  0x20    /* Host buswidth = 16 */
 728 #define DMODE_700_286   0x10    /* 286 mode */
 729 #define DMODE_700_IOM   0x08    /* Transfer to IO port */
 730 #define DMODE_700_FAM   0x04    /* Fixed address mode */
 731 #define DMODE_700_PIPE  0x02    /* Pipeline mode disables 
 732                                          * automatic fetch / exec 
 733                                          */
 734 #define DMODE_MAN       0x01            /* Manual start mode, 
 735                                          * requires a 1 to be written
 736                                          * to the start DMA bit in the DCNTL
 737                                          * register to run scripts 
 738                                          */
 739 
 740 #define DMODE_700_SAVE ( DMODE_00_BL_MASK | DMODE_00_BW16 | DMODE_00_286 )
 741 
 742 /* NCR53c800 series only */
 743 #define SCRATCHA_REG_800        0x34    /* through 0x37 Scratch A rw */
 744 /* NCR53c710 only */
 745 #define SCRATCB_REG_10          0x34    /* through 0x37 scratch B rw */
 746 
 747 #define DMODE_REG_10            0x38    /* DMA mode rw, NCR53c710 and newer */
 748 #define DMODE_800_SIOM          0x20    /* Source IO = 1 */
 749 #define DMODE_800_DIOM          0x10    /* Destination IO = 1 */
 750 #define DMODE_800_ERL           0x08    /* Enable Read Line */
 751 
 752 /* 35-38 are reserved on 700 and 700-66 series chips */
 753 #define DIEN_REG                0x39    /* DMA interrupt enable rw */
 754 /* 0x80, 0x40, and 0x20 are reserved on 700-series chips */
 755 #define DIEN_800_MDPE           0x40    /* Master data parity error */
 756 #define DIEN_800_BF             0x20    /* BUS fault */
 757 #define DIEN_ABRT               0x10    /* Enable aborted interrupt */
 758 #define DIEN_SSI                0x08    /* Enable single step interrupt */
 759 #define DIEN_SIR                0x04    /* Enable SCRIPTS INT command 
 760                                          * interrupt
 761                                          */
 762 /* 0x02 is reserved on 800 series chips */
 763 #define DIEN_700_WTD            0x02    /* Enable watchdog timeout interrupt */
 764 #define DIEN_700_OPC            0x01    /* Enable illegal instruction 
 765                                          * interrupt 
 766                                          */
 767 #define DIEN_800_IID            0x01    /*  Same meaning, different name */ 
 768 
 769 /*
 770  * DMA watchdog timer rw
 771  * set in 16 CLK input periods.
 772  */
 773 #define DWT_REG                 0x3a
 774 
 775 /* DMA control rw */
 776 #define DCNTL_REG               0x3b
 777 #define DCNTL_700_CF1           0x80    /* Clock divisor bits */
 778 #define DCNTL_700_CF0           0x40
 779 #define DCNTL_700_CF_MASK       0xc0
 780 /* Clock divisors                          Divisor SCLK range (MHZ) */
 781 #define DCNTL_700_CF_2          0x00    /* 2.0     37.51-50.00 */
 782 #define DCNTL_700_CF_1_5        0x40    /* 1.5     25.01-37.50 */
 783 #define DCNTL_700_CF_1          0x80    /* 1.0     16.67-25.00 */
 784 #define DCNTL_700_CF_3          0xc0    /* 3.0     50.01-66.67 (53c700-66) */
 785 
 786 #define DCNTL_700_S16           0x20    /* Load scripts 16 bits at a time */
 787 #define DCNTL_SSM               0x10    /* Single step mode */
 788 #define DCNTL_700_LLM           0x08    /* Low level mode, can only be set 
 789                                          * after selection */
 790 #define DCNTL_800_IRQM          0x08    /* Totem pole IRQ pin */
 791 #define DCNTL_STD               0x04    /* Start DMA / SCRIPTS */
 792 /* 0x02 is reserved */
 793 #define DCNTL_00_RST            0x01    /* Software reset, resets everything
 794                                          * but 286 mode bit  in DMODE. On the
 795                                          * NCR53c710, this bit moved to CTEST8
 796                                          */
 797 #define DCNTL_10_COM            0x01    /* 700 software compatibility mode */
 798 
 799 #define DCNTL_700_SAVE ( DCNTL_CF_MASK | DCNTL_S16)
 800 
 801 
 802 /* NCR53c700-66 only */
 803 #define SCRATCHB_REG_00         0x3c    /* through 0x3f scratch b rw */
 804 #define SCRATCHB_REG_800        0x5c    /* through 0x5f scratch b rw */
 805 /* NCR53c710 only */
 806 #define ADDER_REG_10            0x3c    /* Adder, NCR53c710 only */
 807 
 808 #define SIEN1_REG_800           0x41
 809 #define SIEN1_800_STO           0x04    /* selection/reselection timeout */
 810 #define SIEN1_800_GEN           0x02    /* general purpose timer */
 811 #define SIEN1_800_HTH           0x01    /* handshake to handshake */
 812 
 813 #define SIST1_REG_800           0x43
 814 #define SIST1_800_STO           0x04    /* selection/reselection timeout */
 815 #define SIST1_800_GEN           0x02    /* general purpose timer */
 816 #define SIST1_800_HTH           0x01    /* handshake to handshake */
 817 
 818 #define SLPAR_REG_800           0x44    /* Parity */
 819 
 820 #define MACNTL_REG_800          0x46    /* Memory access control */
 821 #define MACNTL_800_TYP3         0x80
 822 #define MACNTL_800_TYP2         0x40
 823 #define MACNTL_800_TYP1         0x20
 824 #define MACNTL_800_TYP0         0x10
 825 #define MACNTL_800_DWR          0x08
 826 #define MACNTL_800_DRD          0x04
 827 #define MACNTL_800_PSCPT        0x02
 828 #define MACNTL_800_SCPTS        0x01
 829 
 830 #define GPCNTL_REG_800          0x47    /* General Purpose Pin Control */
 831 
 832 /* Timeouts are expressed such that 0=off, 1=100us, doubling after that */
 833 #define STIME0_REG_800          0x48    /* SCSI Timer Register 0 */
 834 #define STIME0_800_HTH_MASK     0xf0    /* Handshake to Handshake timeout */
 835 #define STIME0_800_HTH_SHIFT    4
 836 #define STIME0_800_SEL_MASK     0x0f    /* Selection timeout */
 837 #define STIME0_800_SEL_SHIFT    0
 838 
 839 #define STIME1_REG_800          0x49
 840 #define STIME1_800_GEN_MASK     0x0f    /* General purpose timer */
 841 
 842 #define RESPID_REG_800          0x4a    /* Response ID, bit fielded */
 843 
 844 #define STEST0_REG_800          0x4c    
 845 #define STEST0_800_SLT          0x08    /* Selection response logic test */
 846 #define STEST0_800_ART          0x04    /* Arbitration priority encoder test */
 847 #define STEST0_800_SOZ          0x02    /* Synchronous offset zero */
 848 #define STEST0_800_SOM          0x01    /* Synchronous offset maximum */
 849 
 850 #define STEST1_REG_800          0x4d
 851 #define STEST1_800_SCLK         0x80    /* Disable SCSI clock */
 852 
 853 #define STEST2_REG_800          0x4e    
 854 #define STEST2_800_SCE          0x80    /* Enable SOCL/SODL */
 855 #define STEST2_800_ROF          0x40    /* Reset SCSI sync offset */
 856 #define STEST2_800_SLB          0x10    /* Enable SCSI loopback mode */
 857 #define STEST2_800_SZM          0x08    /* SCSI high impedance mode */
 858 #define STEST2_800_EXT          0x02    /* Extend REQ/ACK filter 30 to 60ns */
 859 #define STEST2_800_LOW          0x01    /* SCSI low level mode */
 860 
 861 #define STEST3_REG_800          0x4f     
 862 #define STEST3_800_TE           0x80    /* Enable active negation */
 863 #define STEST3_800_STR          0x40    /* SCSI FIFO test read */
 864 #define STEST3_800_HSC          0x20    /* Halt SCSI clock */
 865 #define STEST3_800_DSI          0x10    /* Disable single initiator response */
 866 #define STEST3_800_TTM          0x04    /* Time test mode */
 867 #define STEST3_800_CSF          0x02    /* Clear SCSI FIFO */
 868 #define STEST3_800_STW          0x01    /* SCSI FIFO test write */
 869 
 870 
 871 
 872 
 873 
 874 #define OPTION_PARITY           0x1     /* Enable parity checking */
 875 #define OPTION_TAGGED_QUEUE     0x2     /* Enable SCSI-II tagged queuing */
 876 #define OPTION_700              0x8     /* Always run NCR53c700 scripts */
 877 #define OPTION_INTFLY           0x10    /* Use INTFLY interrupts */
 878 #define OPTION_DEBUG_INTR       0x20    /* Debug interrupts */
 879 #define OPTION_DEBUG_INIT_ONLY  0x40    /* Run initialization code and 
 880                                            simple test code, return
 881                                            DID_NO_CONNECT if any SCSI
 882                                            commands are attempted. */
 883 #define OPTION_DEBUG_READ_ONLY  0x80    /* Return DID_ERROR if any 
 884                                            SCSI write is attempted */
 885 #define OPTION_DEBUG_TRACE      0x100   /* Animated trace mode, print 
 886                                            each address and instruction 
 887                                            executed to debug buffer. */
 888 #define OPTION_DEBUG_SINGLE     0x200   /* stop after executing one 
 889                                            instruction */
 890 #define OPTION_SYNCHRONOUS      0x400   /* Enable sync SCSI.  */
 891 #define OPTION_MEMORY_MAPPED    0x800   /* NCR registers have valid 
 892                                            memory mapping */
 893 #define OPTION_IO_MAPPED        0x1000  /* NCR registers have valid
 894                                            I/O mapping */
 895 #define OPTION_DEBUG_PROBE_ONLY 0x2000  /* Probe only, don't even init */
 896 #define OPTION_DEBUG_TESTS_ONLY 0x4000  /* Probe, init, run selected tests */
 897 
 898 #define OPTION_DEBUG_TEST0      0x08000 /* Run test 0 */
 899 #define OPTION_DEBUG_TEST1      0x10000 /* Run test 1 */
 900 #define OPTION_DEBUG_TEST2      0x20000 /* Run test 2 */
 901 
 902 #define OPTION_DEBUG_DUMP       0x40000 /* Dump commands */
 903 #define OPTION_DEBUG_TARGET_LIMIT 0x80000 /* Only talk to target+luns specified */
 904 #define OPTION_DEBUG_NCOMMANDS_LIMIT 0x100000 /* Limit the number of commands */
 905 #define OPTION_DEBUG_SCRIPT 0x200000 /* Print when checkpoints are passed */
 906 #define OPTION_DEBUG_FIXUP 0x400000 /* print fixup values */
 907 #define OPTION_DEBUG_DSA 0x800000
 908 #define OPTION_DEBUG_CORRUPTION 0x1000000       /* Detect script corruption */
 909 
 910 #if !defined(PERM_OPTIONS)
 911 #define PERM_OPTIONS 0
 912 #endif
 913                                 
 914 struct NCR53c7x0_synchronous {
 915     unsigned long select_indirect;      /* Value used for indirect selection */
 916     unsigned long script[6];            /* Size ?? Script used when target is 
 917                                                 reselected */
 918     unsigned renegotiate:1;             /* Force renegotiation on next   
 919                                            select */
 920 };
 921 
 922 #define CMD_FLAG_SDTR           1       /* Initiating synchronous 
 923                                            transfer negotiation */
 924 #define CMD_FLAG_WDTR           2       /* Initiating wide transfer
 925                                            negotiation */
 926 #define CMD_FLAG_DID_SDTR       4       /* did SDTR */
 927 
 928 struct NCR53c7x0_table_indirect {
 929     unsigned long count;
 930     void *address;
 931 };
 932 
 933 struct NCR53c7x0_cmd {
 934     void *real;                         /* Real, unaligned address */
 935     Scsi_Cmnd *cmd;                     /* Associated Scsi_Cmnd 
 936                                            structure, Scsi_Cmnd points
 937                                            at NCR53c7x0_cmd using 
 938                                            host_scribble structure */
 939 
 940     int size;                           /* scsi_malloc'd size of this 
 941                                            structure */
 942 
 943     int flags;
 944 
 945     unsigned char select[11];           /* Select message, includes
 946                                            IDENTIFY
 947                                            (optional) QUEUE TAG
 948                                            (optional) SDTR or WDTR
 949                                          */
 950 
 951 
 952     struct NCR53c7x0_cmd *next, *prev;  /* Linux maintained lists */
 953 
 954 
 955     unsigned long *data_transfer_start; /* Start of data transfer routines */
 956     unsigned long *data_transfer_end;   /* Address after end of data transfer o
 957                                            routines */
 958 
 959     unsigned long residual[8];          /* Residual data transfer
 960                                            shadow of data_transfer code.
 961 
 962                                            Has instruction with modified
 963                                            DBC field followed by jump to 
 964                                            CALL routine following command.
 965                                          */
 966              
 967     unsigned long dsa[0];               /* Variable length (depending
 968                                            on host type, number of scatter /
 969                                            gather buffers, etc).  */
 970 };
 971 
 972 struct NCR53c7x0_break {
 973     unsigned long *address, old_instruction[2];
 974     struct NCR53c7x0_break *next;
 975     unsigned char old_size;             /* Size of old instruction */
 976 };
 977 
 978 /* Indicates that the NCR is not executing code */
 979 #define STATE_HALTED    0               
 980 /* 
 981  * Indicates that the NCR is executing the wait for select / reselect 
 982  * script.  Only used when running NCR53c700 compatible scripts, only 
 983  * state during which an ABORT is _not_ considered an error condition.
 984  */
 985 #define STATE_WAITING   1               
 986 /* Indicates that the NCR is executing other code. */
 987 #define STATE_RUNNING   2               
 988 /* 
 989  * Indicates that the NCR was being aborted.  Only used when running 
 990  * NCR53c700 compatible scripts.  
 991  */
 992 #define STATE_ABORTING  3
 993     
 994 
 995 /* 
 996  * Where knowledge of SCSI SCRIPT(tm) specified values are needed 
 997  * in an interrupt handler, an interrupt handler exists for each 
 998  * different SCSI script so we don't have name space problems.
 999  * 
1000  * Return values of these handlers are as follows : 
1001  */
1002 #define SPECIFIC_INT_NOTHING    0       /* don't even restart */
1003 #define SPECIFIC_INT_RESTART    1       /* restart at the next instruction */
1004 #define SPECIFIC_INT_ABORT      2       /* recoverable error, abort cmd */
1005 #define SPECIFIC_INT_PANIC      3       /* unrecoverable error, panic */
1006 #define SPECIFIC_INT_DONE       4       /* normal command completion */
1007 #define SPECIFIC_INT_BREAK      5       /* break point encountered */
1008 
1009 struct NCR53c7x0_hostdata {
1010     int size;                           /* Size of entire Scsi_Host
1011                                            structure */
1012     struct Scsi_Host *next;             /* next of this type */
1013     int board;                          /* set to board type, useful if 
1014                                            we have host specific things,
1015                                            ie, a general purpose I/O 
1016                                            bit is being used to enable
1017                                            termination, etc. */
1018 
1019     int chip;                           /* set to chip type */
1020         /*
1021          * NCR53c700 = 700
1022          * NCR53c700-66 = 70066
1023          * NCR53c710 = 710
1024          * NCR53c720 = 720 
1025          * NCR53c810 = 810
1026          */
1027 
1028     /*
1029      * PCI bus, device, function, only for NCR53c8x0 chips.
1030      * pci_valid indicates that the PCI configuration information
1031      * is valid, and we can twiddle MAX_LAT, etc. as recommended
1032      * for maximum performance in the NCR documentation.
1033      */
1034     unsigned char pci_bus, pci_device_fn;
1035     unsigned pci_valid:1;
1036 
1037     unsigned long *dsp;                 /* dsp to restart with after
1038                                            all stacked interrupts are
1039                                            handled. */
1040 
1041     unsigned dsp_changed:1;             /* Has dsp changed within this
1042                                            set of stacked interrupts ? */
1043 
1044     unsigned char dstat;                /* Most recent value of dstat */
1045     unsigned dstat_valid:1;
1046 
1047     unsigned expecting_iid:1;           /* Expect IID interrupt */
1048     unsigned expecting_sto:1;           /* Expect STO interrupt */
1049     
1050     /* 
1051      * The code stays cleaner if we use variables with function
1052      * pointers and offsets that are unique for the different
1053      * scripts rather than having a slew of switch(hostdata->chip) 
1054      * statements.
1055      * 
1056      * It also means that the #defines from the SCSI SCRIPTS(tm)
1057      * don't have to be visible outside of the script-specific
1058      * instructions, preventing name space pollution.
1059      */
1060 
1061     void (* init_fixup)(struct Scsi_Host *host);
1062     void (* init_save_regs)(struct Scsi_Host *host);
1063     void (* dsa_fixup)(struct NCR53c7x0_cmd *cmd);
1064     void (* soft_reset)(struct Scsi_Host *host);
1065     int (* run_tests)(struct Scsi_Host *host);
1066 
1067     /*
1068      * Called when DSTAT_SIR is set, indicating an interrupt generated
1069      * by the INT instruction, where values are unique for each SCSI
1070      * script.  Should return one of the SPEC_* values.
1071      */
1072 
1073     int (* dstat_sir_intr)(struct Scsi_Host *host, struct NCR53c7x0_cmd *cmd);
1074 
1075 
1076     /*
1077      * Location of DSA fields for the SCSI SCRIPT corresponding to this 
1078      * chip.  
1079      */
1080 
1081     long dsa_start;                     
1082     long dsa_end;                       
1083     long dsa_next;
1084     long dsa_prev;
1085     long dsa_cmnd;
1086     long dsa_select;
1087     long dsa_msgout;
1088     long dsa_cmdout;
1089     long dsa_dataout;
1090     long dsa_datain;
1091     long dsa_msgin;
1092     long dsa_msgout_other;
1093     long dsa_write_sync;
1094     long dsa_write_resume;
1095     long dsa_jump_resume;
1096     long dsa_check_reselect;
1097     long dsa_status;
1098 
1099     /* 
1100      * Important entry points that generic fixup code needs
1101      * to know about, fixed up.
1102      */
1103 
1104     long E_accept_message;
1105     long E_dsa_code_template;
1106     long E_dsa_code_template_end;
1107     long E_command_complete;            
1108     long E_msg_in;
1109     long E_initiator_abort;
1110     long E_other_transfer;
1111     long E_target_abort;
1112     long E_schedule;                    
1113     long E_debug_break; 
1114     long E_reject_message;
1115     long E_respond_message;
1116     long E_select;
1117     long E_select_msgout;
1118     long E_test_0;
1119     long E_test_1;
1120     long E_test_2;
1121     long E_test_3;
1122     long E_dsa_zero;
1123     long E_dsa_jump_resume;
1124 
1125     int options;                        /* Bitfielded set of options enabled */
1126     long test_completed;                /* Test completed */
1127     int test_running;                   /* Test currently running */
1128     int test_source;
1129     volatile int test_dest;
1130 
1131     volatile int state;                 /* state of driver, only used for 
1132                                            OPTION_700 */
1133 
1134     unsigned char  dmode;               /* 
1135                                          * set to the address of the DMODE 
1136                                          * register for this chip.
1137                                          */
1138     unsigned char istat;                /* 
1139                                          * set to the address of the ISTAT 
1140                                          * register for this chip.
1141                                          */
1142   
1143     int scsi_clock;                     /* 
1144                                          * SCSI clock in HZ. 0 may be used 
1145                                          * for unknown, although this will
1146                                          * disable synchronous negotiation.
1147                                          */
1148 
1149     volatile int intrs;                 /* Number of interrupts */
1150     unsigned char saved_dmode;  
1151     unsigned char saved_ctest4;
1152     unsigned char saved_ctest7;
1153     unsigned char saved_dcntl;
1154     unsigned char saved_scntl3;
1155 
1156     unsigned char this_id_mask;
1157 
1158     /* Debugger information */
1159     struct NCR53c7x0_break *breakpoints, /* Linked list of all break points */
1160         *breakpoint_current;            /* Current breakpoint being stepped 
1161                                            through, NULL if we are running 
1162                                            normally. */
1163     int debug_size;                     /* Size of debug buffer */
1164     volatile int debug_count;           /* Current data count */
1165     volatile char *debug_buf;           /* Output ring buffer */
1166     volatile char *debug_write;         /* Current write pointer */
1167     volatile char *debug_read;          /* Current read pointer */
1168 
1169     /* XXX - primitive debugging junk, remove when working ? */
1170     int debug_print_limit;              /* Number of commands to print
1171                                            out exhaustive debugging
1172                                            information for if 
1173                                            OPTION_DEBUG_DUMP is set */ 
1174 
1175     unsigned char debug_lun_limit[8];   /* If OPTION_DEBUG_TARGET_LIMIT
1176                                            set, puke if commands are sent
1177                                            to other target/lun combinations */
1178 
1179     int debug_count_limit;              /* Number of commands to execute
1180                                            before puking to limit debugging 
1181                                            output */
1182                                     
1183 
1184     volatile unsigned idle:1;                   /* set to 1 if idle */
1185 
1186     /* 
1187      * Table of synchronous transfer parameters set on a per-target
1188      * basis.
1189      * 
1190      * XXX - do we need to increase this to 16 for the WIDE-SCSI
1191      * flavors of the board?
1192      */
1193     
1194     volatile struct NCR53c7x0_synchronous sync[8];
1195 
1196     volatile struct NCR53c7x0_cmd *issue_queue;
1197                                                 /* waiting to be issued by
1198                                                    Linux driver */
1199     volatile struct NCR53c7x0_cmd *running_list;        
1200                                                 /* commands running, maintained
1201                                                    by Linux driver */
1202     volatile struct NCR53c7x0_cmd *current;     /* currently connected 
1203                                                    nexus, ONLY valid for
1204                                                    NCR53c700/NCR53c700-66
1205                                                  */
1206     volatile unsigned char busy[8][8];          /* number of commands 
1207                                                    executing on each target
1208                                                  */
1209     /* 
1210      * Eventually, I'll switch to a coroutine for calling 
1211      * cmd->done(cmd), etc. so that we can overlap interrupt
1212      * processing with this code for maximum performance.
1213      */
1214     
1215     volatile struct NCR53c7x0_cmd *finished_queue;      
1216                                                 
1217 
1218     /* Shared variables between SCRIPT and host driver */
1219     volatile unsigned char *issue_dsa_head;     
1220                                                 /* commands waiting to be 
1221                                                    issued, insertions are 
1222                                                    done by Linux driver,
1223                                                    deletions are done by
1224                                                    NCR */
1225     volatile unsigned char *issue_dsa_tail;
1226     volatile unsigned char msg_buf[16];         /* buffer for messages
1227                                                    other than the command
1228                                                    complete message */
1229     volatile struct NCR53c7x0_cmd *reconnect_dsa_head;  
1230                                                 /* disconnected commands,
1231                                                    maintained by NCR */
1232     /* Data identifying nexus we are trying to match during reselection */
1233     volatile unsigned char reselected_identify; /* IDENTIFY message */
1234     volatile unsigned char reselected_tag;      /* second byte of queue tag 
1235                                                    message or 0 */
1236     int script_count;                           /* Size of script in longs */
1237     unsigned long script[0];                    /* Relocated SCSI script */
1238 
1239 };
1240 
1241 #define IRQ_NONE        255
1242 #define DMA_NONE        255
1243 #define IRQ_AUTO        254
1244 #define DMA_AUTO        254
1245 
1246 #define BOARD_GENERIC   0
1247 
1248 #define NCR53c7x0_insn_size(insn)                                       \
1249     (((insn) & DCMD_TYPE_MASK) == DCMD_TYPE_MMI ? 3 : 2)
1250     
1251 
1252 #define NCR53c7x0_local_declare()                                       \
1253     volatile unsigned char *NCR53c7x0_address_memory;                   \
1254     unsigned short NCR53c7x0_address_io;                                \
1255     int NCR53c7x0_memory_mapped
1256 
1257 #define NCR53c7x0_local_setup(host)                                     \
1258     NCR53c7x0_address_memory = (void *) (host)->base;                   \
1259     NCR53c7x0_address_io = (unsigned short) (host)->io_port;            \
1260     NCR53c7x0_memory_mapped = ((struct NCR53c7x0_hostdata *)            \
1261         host->hostdata)-> options & OPTION_MEMORY_MAPPED 
1262 
1263 #define NCR53c7x0_read8(address)                                        \
1264     (NCR53c7x0_memory_mapped ?                                          \
1265         *( (NCR53c7x0_address_memory) + (address))  :                   \
1266         inb(NCR53c7x0_address_io + (address)))
1267 
1268 #define NCR53c7x0_read16(address)                                       \
1269     (NCR53c7x0_memory_mapped ?                                          \
1270         *((unsigned short *) (NCR53c7x0_address_memory) + (address))  : \
1271         inw(NCR53c7x0_address_io + (address)))
1272 
1273 #define NCR53c7x0_read32(address)                                       \
1274     (NCR53c7x0_memory_mapped ?                                          \
1275         *((unsigned long *) (NCR53c7x0_address_memory) + (address))  :  \
1276         inl(NCR53c7x0_address_io + (address)))
1277 
1278 #define NCR53c7x0_write8(address,value)                                 \
1279     (NCR53c7x0_memory_mapped ?                                          \
1280         *((unsigned char *) (NCR53c7x0_address_memory) + (address)) =   \
1281           (value) :                                                     \
1282         outb((value), NCR53c7x0_address_io + (address)))
1283 
1284 #define NCR53c7x0_write16(address,value)                                \
1285     (NCR53c7x0_memory_mapped ?                                          \
1286         *((unsigned short *) (NCR53c7x0_address_memory) + (address)) =  \
1287           (value) :                                                     \
1288         outw((value), NCR53c7x0_address_io + (address)))
1289 
1290 #define NCR53c7x0_write32(address,value)                                \
1291     (NCR53c7x0_memory_mapped ?                                          \
1292         *((unsigned long *) (NCR53c7x0_address_memory) + (address)) =   \
1293           (value) :                                                     \
1294         outl((value), NCR53c7x0_address_io + (address)))
1295 
1296 #define patch_abs_32(script, offset, symbol, value)                     \
1297         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1298             (unsigned long)); ++i) {                                    \
1299             (script)[A_##symbol##_used[i] - (offset)] += (value);       \
1300             if (hostdata->options & OPTION_DEBUG_FIXUP)                 \
1301               printk("scsi%d : %s reference %d at 0x%lx in %s is now 0x%lx\n",\
1302                 host->host_no, #symbol, i, A_##symbol##_used[i] -       \
1303                 (offset), #script, (script)[A_##symbol##_used[i] -      \
1304                 (offset)]);                                             \
1305         }
1306 
1307 #define patch_abs_rwri_data(script, offset, symbol, value)              \
1308         for (i = 0; i < (sizeof (A_##symbol##_used) / sizeof            \
1309             (unsigned long)); ++i)                                      \
1310             (script)[A_##symbol##_used[i] - (offset)] =                 \
1311                 ((script)[A_##symbol##_used[i] - (offset)] &            \
1312                 ~DBC_RWRI_IMMEDIATE_MASK) |                             \
1313                 (((value) << DBC_RWRI_IMMEDIATE_SHIFT) &                \
1314                  DBC_RWRI_IMMEDIATE_MASK)
1315 
1316 #define patch_dsa_32(dsa, symbol, word, value)                          \
1317         {                                                               \
1318         (dsa)[(hostdata->##symbol - hostdata->dsa_start) / sizeof(long) \
1319                 + (word)] = (unsigned long) (value);                    \
1320         if (hostdata->options & OPTION_DEBUG_DSA)                       \
1321             printk("scsi : dsa %s symbol %s(%ld) word %d now 0x%lx\n",  \
1322                 #dsa, #symbol, (long) hostdata->##symbol,               \
1323                 (int) (word), (long) (value));                                  \
1324         }
1325     
1326 
1327 
1328 #endif /* NCR53c7x0_C */
1329 #endif /* NCR53c7x0_H */

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