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7
8
9
10 #undef DEBUGPICA
11
12 #include <linux/tasks.h>
13
14 #include <asm/segment.h>
15 #include <asm/cachectl.h>
16 #include <asm/mipsregs.h>
17 #include <asm/mipsconfig.h>
18 #include <asm/stackframe.h>
19 #include <asm/regdef.h>
20 #include <asm/bootinfo.h>
21 #include <asm/segment.h>
22
23 #define PAGE_SIZE 0x1000
24
25
26
27
28
29
30
31 #define PAGE_TABLE 0x0580
32 #define PAGE_SHARED 0x0580
33 #define MODE_ALIAS 0x0016
34
35 .globl _empty_bad_page
36 .globl _empty_bad_page_table
37 .globl _pg0
38 .globl _empty_zero_page
39 .globl _tmp_floppy_area
40 .globl _floppy_track_buffer
41 .globl _swapper_pg_dir
42
43 .text
44 .globl _kernelbase
45 _kernelbase:
46
47
48
49
50
51
52
53
54 .set noreorder
55 .set noat
56 except_vec0:
57 #if KERNELBASE == KSEG1
58 la k0,1f
59 jr k0
60 nop
61 1:
62 #endif
63 dmfc0 k1,CP0_CONTEXT
64 dsra k1,k1,1
65 lwu k0,(k1) # May cause another exception
66 lwu k1,4(k1)
67 dsrl k0,k0,6 # Convert to EntryLo format
68 dsrl k1,k1,6 # Convert to EntryLo format
69 dmtc0 k0,CP0_ENTRYLO0
70 dmtc0 k1,CP0_ENTRYLO1
71 tlbwr
72 eret
73
74
75
76
77
78 .org except_vec0+0x80
79 except_vec1:
80 #if KERNELBASE == KSEG1
81 la k0,1f
82 jr k0
83 nop
84 1:
85 #endif
86 la a0,xtlb_text
87 jal _panic
88 nop
89 1: j 1b
90 nop
91 xtlb_text: .asciz "XTLB Refill exception.\n"
92
93
94
95
96 .org except_vec1+0x80
97 except_vec2:
98 #if KERNELBASE == KSEG1
99 la k0,1f
100 jr k0
101 nop
102 1:
103 #endif
104
105
106
107 la a0,xtlb_text
108 jal _panic
109 nop
110 1: j 1b
111 nop
112 cache_text: .asciz "Cache error exception\n"
113
114
115
116
117 .org except_vec2+0x80
118 except_vec3:
119
120
121
122 #if KERNELBASE == KSEG1
123 la k0,1f
124 jr k0
125 nop
126 1:
127 #endif
128 .set noat
129 mfc0 k1,CP0_CAUSE
130 la k0,_exception_handlers
131
132
133
134
135
136 andi k1,k1,0x7c
137 addu k0,k0,k1
138 lw k0,(k0)
139 FILL_LDS
140 jr k0
141 nop
142
143
144
145
146
147
148 .set noreorder
149 .set at
150 kernel_entry:
151 jal refill
152 nop
153
154
155
156
157 la t0,__edata
158 la t1,__end
159 sw zero,(t0)
160 1: addiu t0,t0,4
161 bnel t0,t1,1b
162 sw zero,(t0)
163
164 #ifdef DEBUGPICA
165 la t0,_boot_info
166 lw t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
167 li t1,0x0f00 + '3'
168 sh t1,4(t0)
169 #endif
170
171 .set noreorder
172 jal _tlbflush
173 mtc0 zero,CP0_WIRED
174
175
176
177 la t0,_end
178 la t1,0x003ffffc
179 la t2,KERNELBASE
180 or t1,t2
181 li t2,0xdeadbeef
182 1: sw t2,(t0)
183 bne t0,t1,1b
184 addiu t0,t0,4
185
186
187
188 .set reorder
189 jal setup_paging
190 #if KERNELBASE == KSEG0
191 jal _sys_cacheflush
192 #endif
193
194 #ifdef DEBUGPICA
195 la t0,_boot_info
196 lw t0,OFFSET_BOOTINFO_VRAM_BASE(t0)
197 li t1,0x0f00 + '4'
198 sh t1,6(t0)
199 #endif
200
201
202
203 la sp,_init_user_stack+PAGE_SIZE-24
204 sw sp,_kernelsp
205
206 1: jal _start_kernel
207
208
209
210
211 j 1b
212
213
214
215
216
217
218
219
220 .set noreorder
221 setup_paging:
222
223
224
225
226 la t0,_boot_info
227 lw t1,OFFSET_BOOTINFO_MACHTYPE(t0)
228 sll t1,t1,2 # machtype used as index
229 la t0,map0table
230 addu t0,t0,t1
231 lw t0,(t0) # get base address
232
233
234
235
236
237 lw t1,(t0) # number of wired TLB entries
238 move t2,zero # TLB entry counter
239 addiu t3,t1,1 # wire one additional entry
240 beqz t1,2f # null, exit
241 mtc0 t3,CP0_WIRED # delay slot
242 addiu t0,t0,8
243 1: lw t4,24(t0) # PageMask
244 ld t5,0(t0) # entryHi
245 ld t6,8(t0) # entryLo0
246 ld t7,16(t0) # entryLo1
247 addiu t2,t2,1 # increment ctr
248 mtc0 t2,CP0_INDEX # set TLB entry
249 mtc0 t4,CP0_PAGEMASK
250 dmtc0 t5,CP0_ENTRYHI
251 dmtc0 t6,CP0_ENTRYLO0
252 dmtc0 t7,CP0_ENTRYLO1
253 tlbwi
254 bne t1,t2,1b # next TLB entry
255 addiu t0,t0,32 # delay slot
256
257
258
259
260
261 2: li t0,PM_4K
262 mtc0 t0,CP0_PAGEMASK
263
264 la t1,_swapper_pg_dir # swapper_pg_dir is at 0x1000
265 la t2,_swapper_pg_dir+(PAGE_SIZE-4)
266 1: sw zero,(t1)
267 bne t1,t2,1b
268 addiu t1,t1,4 # delay slot
269
270
271
272
273
274 la t0,_pg0 # swapper_pg_dir is at 0x1000
275 la t1,_pg0+PAGE_SIZE
276 li t2,KERNELBASE
277 addu t0,t2
278 addu t1,t2
279 1: sw zero,(t0)
280 addiu t0,t0,4
281 bne t0,t1,1b
282 addiu t2,t2,4 # delay slot
283
284
285
286
287
288
289 la t0,_pg0+PAGE_TABLE # set valid bit/user r/w
290 sw t0,_swapper_pg_dir
291
292 li t0,PAGE_SHARED # set valid bit/user r/w
293 la t1,_pg0
294 la t2,_pg0+PAGE_SIZE
295 li t3,KERNELBASE
296 addu t1,t3
297 addu t2,t3
298 1: sw t0,(t1)
299 addiu t1,t1,4
300 bne t1,t2,1b
301 addiu t0,t0,PAGE_SIZE # delay slot
302
303
304
305
306 mtc0 zero,CP0_INDEX
307 la t0,TLB_ROOT
308 dmtc0 t0,CP0_ENTRYHI
309 la t0,_swapper_pg_dir
310 srl t0,t0,6
311 ori t0,t0,MODE_ALIAS # uncachable, dirty, valid
312 dmtc0 t0,CP0_ENTRYLO0
313 dmtc0 zero,CP0_ENTRYLO1
314 tlbwi
315
316
317
318 la t0,_pg0
319 li t0,KERNELBASE
320 addu t0,t1
321 sw zero,(t0)
322
323
324
325
326
327
328 li t0,TLBMAP
329 dsll t0,t0,1
330 jr ra
331 dmtc0 t0,CP0_CONTEXT # delay slot
332
333
334
335
336
337
338
339
340 .globl _tlbflush
341 _tlbflush: li t0,PM_4K
342 mtc0 t0,CP0_PAGEMASK
343 lw t0,_boot_info+OFFSET_BOOTINFO_TLB_ENTRIES(t0)
344 dmtc0 zero,CP0_ENTRYLO0
345 dmtc0 zero,CP0_ENTRYLO1
346 mfc0 t2,CP0_WIRED
347 1: subu t0,t0,1
348 mtc0 t0,CP0_INDEX
349 lui t1,0x0008
350 or t1,t0,t1
351 dsll t1,t1,13
352 dmtc0 t1,CP0_ENTRYHI
353 bne t2,t0,1b
354 tlbwi # delay slot
355 jr ra
356 nop
357
358
359
360
361 #include <asm/mipsconfig.h>
362 #include <asm/regdef.h>
363 #include <asm/segment.h>
364
365 #define PAGE_SIZE 0x1000
366
367 #define CACHELINES 512
368
369 .set noreorder
370 .text
371 refill:
372
373
374
375 li t0,KSEG0
376 li t1,CACHELINES
377 1: cache 21,0(t0)
378 cache 21,32(t0)
379 cache 21,64(t0)
380 cache 21,96(t0)
381 cache 21,128(t0)
382 cache 21,160(t0)
383 cache 21,192(t0)
384 cache 21,224(t0)
385 cache 21,256(t0)
386 cache 21,288(t0)
387 cache 21,320(t0)
388 cache 21,352(t0)
389 cache 21,384(t0)
390 cache 21,416(t0)
391 cache 21,448(t0)
392 cache 21,480(t0)
393 subu t1,t1,1
394 bnez t1,1b
395 addiu t0,t0,512 # delay slot
396
397 jr ra
398 nop
399
400
401
402
403 .globl _beep
404 _beep: lw t0,beepflag
405 nop
406 bnez t0,1f
407 lbu t0,0xe0000061
408 xori t0,t0,3
409 sb t0,0xe0000061
410 li t0,1
411 sw t0,beepflag
412 1: jr ra
413 nop
414
415
416
417
418 .globl _csum
419 #if 0
420 _csum: jal _sys_cacheflush
421 move t8,ra # delay slot
422 #else
423 _csum: move t8,ra
424 #endif
425 li t0,KSEG1
426 la t1,final
427 li t2,KSEG1
428 or t0,t2
429 or t1,t2
430 move v0,zero
431 1: lw t2,(t0)
432 addiu t0,t0,4
433 bne t0,t1,1b
434 xor v0,v0,t2
435 jr t8
436 nop
437 final:
438
439 .data
440
441
442
443
444
445
446 .globl _segment_fs
447 _segment_fs: .word KERNEL_DS
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463 map0table: .word map0_dummy # machtype = unknown
464 .word map0_tyne # Deskstation Tyne
465 .word map0_pica61 # Acer Pica-61
466
467 map0_dummy: .word 0 # 0 entries
468
469
470
471
472 .align 8
473
474 map0_tyne: .word 3 # no. of wired TLB entries
475 .word 0 # pad for alignment
476
477
478
479 .quad 0xffffffffe0000000 # TLB #0 EntryHi
480 .quad 0x24000017 # TLB #0 EntryLo0
481 .quad 0 # TLB #0 EntryLo1
482 .word PM_64K # page mask
483 .word 0 # pad for alignment
484
485
486
487 .quad 0xffffffffe1000000 # TLB #1 EntryHi
488 .quad 0x04000017 # TLB #1 EntryLo0
489 .quad 0 # TLB #1 EntryLo1
490 .word PM_1M
491 .word 0 # pad for alignment
492
493
494
495 .quad 0xffffffffe2000000 # TLB #2 EntryHi
496 .quad 0x04020017 # TLB #2 EntryLo0
497 .quad 0 # TLB #2 EntryLo1
498 .word PM_1M
499 .word 0 # pad for alignment
500
501
502
503
504
505
506
507
508
509
510
511
512 map0_pica61: .word 9 # no. wired TLB entries
513 .word 0 # dummy
514
515
516
517 # .quad 0xffffffffe1000000 # BIOS mapping
518 .quad 0xffffffffe4000000 # new mapping
519 .quad 0x03ffc013
520 .quad 0x00000001 # global, not valid
521 .word PM_256K
522 .word 0
523
524
525
526 .quad 0xffffffffe0000000
527 .quad 0x02000017
528 .quad 0x00000001 # global, not valid
529 .word PM_64K
530 .word 0
531
532
533
534 .quad 0xffffffffe00e0000
535 .quad 0x02003817
536 .quad 0x02003c17
537 .word PM_64K
538 .word 0
539
540
541
542 .quad 0xffffffffe0100000
543 .quad 0x03c00017
544 .quad 0x00000001 # global, not valid
545 .word PM_4K
546 .word 0
547
548
549
550 .quad 0xffffffffe0200000
551 .quad 0x01800017
552 .quad 0x01804017
553 .word PM_1M
554 .word 0
555
556
557
558 .quad 0xffffffffe0400000
559 .quad 0x01808017
560 .quad 0x0180c017
561 .word PM_1M
562 .word 0
563
564
565
566 .quad 0xffffffffe0800000
567 .quad 0x01000017
568 .quad 0x01010017
569 .word PM_4M
570 .word 0
571
572
573
574 # .quad 0xffffffffe1000000
575 # .quad 0x01000017
576 # .quad 0x01010017
577 # .word PM_4M
578 # .word 0
579
580
581
582 .quad 0xffffffffe2000000
583 .quad 0x02400017
584 .quad 0x02440017
585 .word PM_16M
586 .word 0
587
588
589
590 .quad 0xffffffffffffe000
591 .quad 0x00000001 # nonsense...
592 .quad 0x0001ffd7
593 .word PM_4K
594 .word 0
595
596
597
598
599
600
601 #if 0
602 map0_pica61: .word 11 # no. wired TLB entries
603 .word 0 # dummy
604
605
606
607 .quad 0xfffffffffffe2000
608 .quad 0x0000029e
609 .quad 0x00000000
610 .word PM_4K
611 .word 0
612
613
614
615 .quad 0xffffffffe1000000
616 .quad 0x03ffc013
617 .quad 0x00000001 # nonsense ...
618 .word PM_256K
619 .word 0
620
621
622
623 .quad 0xffffffffe0000000
624 .quad 0x02000017
625 .quad 0x00000001 # nonsense ...
626 .word PM_64K
627 .word 0
628
629
630
631 .quad 0xffffffffe00e0000
632 .quad 0x02003817
633 .quad 0x02003c17
634 .word PM_64K
635 .word 0
636
637
638
639 .quad 0xffffffffe0100000
640 .quad 0x03c00017
641 .quad 0x00000001 # nonsense ...
642 .word PM_4K
643 .word 0
644
645
646
647 .quad 0xffffffffe0200000
648 .quad 0x01800017
649 .quad 0x01804017
650 .word PM_1M
651 .word 0
652
653
654
655 .quad 0xffffffffe0400000
656 .quad 0x01808017
657 .quad 0x0180c017
658 .word PM_1M
659 .word 0
660
661
662
663 .quad 0xffffffffe0800000
664 .quad 0x01000017
665 .quad 0x01010017
666 .word PM_4M
667 .word 0
668
669
670
671 .quad 0xffffffffe2000000
672 .quad 0x02400017
673 .quad 0x02440017
674 .word PM_16M
675 .word 0
676
677
678
679 .quad 0xffffffffffffe000
680 .quad 0x00000001 # nonsense...
681 .quad 0x0001ffd7
682 .word PM_4K
683 .word 0
684
685
686
687 .quad 0xffffffff10000000
688 .quad 0x0000141f
689 .quad 0x00000001 # nonsense
690 .word PM_64K
691 .word 0
692 #endif
693
694
695
696
697
698
699
700
701
702
703
704 .text
705
706 .org 0x1000
707 _swapper_pg_dir = 0x1000
708
709
710
711
712 .org 0x2000
713 _pg0 = 0x2000
714
715 .org 0x3000
716 _empty_bad_page = 0x3000
717
718 .org 0x4000
719 _empty_bad_page_table = 0x4000
720
721 .org 0x5000
722 _empty_zero_page = 0x5000
723
724 .org 0x6000
725
726
727
728
729
730
731 _tmp_floppy_area: .fill 1024,1,0
732
733
734
735
736
737
738 _floppy_track_buffer: .fill 512*2*36,1,0
739 .globl _kernelsp
740 _kernelsp: .word 0
741 beepflag: .word 0