root/drivers/net/de4x5.h

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   1 /*
   2     Copyright 1994 Digital Equipment Corporation.
   3 
   4     This software may be used and distributed according to  the terms of the
   5     GNU Public License, incorporated herein by reference.
   6 
   7     The author may    be  reached as davies@wanton.lkg.dec.com  or   Digital
   8     Equipment Corporation, 550 King Street, Littleton MA 01460.
   9 
  10     =========================================================================
  11 */
  12 
  13 /*
  14 ** DC21040 CSR<1..15> Register Address Map
  15 */
  16 #define DE4X5_BMR    iobase+(0x000 << lp->bus)  /* Bus Mode Register */
  17 #define DE4X5_TPD    iobase+(0x008 << lp->bus)  /* Transmit Poll Demand Reg */
  18 #define DE4X5_RPD    iobase+(0x010 << lp->bus)  /* Receive Poll Demand Reg */
  19 #define DE4X5_RRBA   iobase+(0x018 << lp->bus)  /* RX Ring Base Address Reg */
  20 #define DE4X5_TRBA   iobase+(0x020 << lp->bus)  /* TX Ring Base Address Reg */
  21 #define DE4X5_STS    iobase+(0x028 << lp->bus)  /* Status Register */
  22 #define DE4X5_OMR    iobase+(0x030 << lp->bus)  /* Operation Mode Register */
  23 #define DE4X5_IMR    iobase+(0x038 << lp->bus)  /* Interrupt Mask Register */
  24 #define DE4X5_MFC    iobase+(0x040 << lp->bus)  /* Missed Frame Counter */
  25 #define DE4X5_APROM  iobase+(0x048 << lp->bus)  /* Ethernet Address PROM */
  26 #define DE4X5_DDR    iobase+(0x050 << lp->bus)  /* Data Diagnostic Register */
  27 #define DE4X5_FDR    iobase+(0x058 << lp->bus)  /* Full Duplex Register */
  28 #define DE4X5_SISR   iobase+(0x060 << lp->bus)  /* SIA Status Register */
  29 #define DE4X5_SICR   iobase+(0x068 << lp->bus)  /* SIA Connectivity Register */
  30 #define DE4X5_STRR   iobase+(0x070 << lp->bus)  /* SIA TX/RX Register */
  31 #define DE4X5_SIGR   iobase+(0x078 << lp->bus)  /* SIA General Register */
  32 
  33 /*
  34 ** EISA Register Address Map
  35 */
  36 #define EISA_ID      iobase+0x0c80   /* EISA ID Registers */ 
  37 #define EISA_ID0     iobase+0x0c80   /* EISA ID Register 0 */ 
  38 #define EISA_ID1     iobase+0x0c81   /* EISA ID Register 1 */ 
  39 #define EISA_ID2     iobase+0x0c82   /* EISA ID Register 2 */ 
  40 #define EISA_ID3     iobase+0x0c83   /* EISA ID Register 3 */ 
  41 #define EISA_CR      iobase+0x0c84   /* EISA Control Register */
  42 #define EISA_REG0    iobase+0x0c88   /* EISA Configuration Register 0 */
  43 #define EISA_REG1    iobase+0x0c89   /* EISA Configuration Register 1 */
  44 #define EISA_REG2    iobase+0x0c8a   /* EISA Configuration Register 2 */
  45 #define EISA_REG3    iobase+0x0c8f   /* EISA Configuration Register 3 */
  46 #define EISA_APROM   iobase+0x0c90   /* Ethernet Address PROM */
  47 
  48 /*
  49 ** PCI/EISA Configuration Registers Address Map
  50 */
  51 #define PCI_CFID     iobase+0x0008   /* PCI Configuration ID Register */
  52 #define PCI_CFCS     iobase+0x000c   /* PCI Command/Status Register */
  53 #define PCI_CFRV     iobase+0x0018   /* PCI Revision Register */
  54 #define PCI_CFLT     iobase+0x001c   /* PCI Latency Timer Register */
  55 #define PCI_CBIO     iobase+0x0028   /* PCI Base I/O Register */
  56 #define PCI_CBMA     iobase+0x002c   /* PCI Base Memory Address Register */
  57 #define PCI_CFIT     iobase+0x0038   /* PCI Configuration Interrupt Register */
  58 
  59 /*
  60 ** EISA Configuration Register 0 bit definitions
  61 */
  62 #define ER0_BSW       0x80           /* EISA Bus Slave Width, 1: 32 bits */
  63 #define ER0_BMW       0x40           /* EISA Bus Master Width, 1: 32 bits */
  64 #define ER0_EPT       0x20           /* EISA PREEMPT Time, 0: 23 BCLKs */
  65 #define ER0_ISTS      0x10           /* Interrupt Status (X) */
  66 #define ER0_LI        0x08           /* Latch Interrupts */
  67 #define ER0_INTL      0x06           /* INTerrupt Level */
  68 #define ER0_INTT      0x01           /* INTerrupt Type, 0: Level, 1: Edge */
  69 
  70 /*
  71 ** EISA Configuration Register 1 bit definitions
  72 */
  73 #define ER1_IAM       0xe0           /* ISA Address Mode */
  74 #define ER1_IAE       0x10           /* ISA Addressing Enable */
  75 #define ER1_UPIN      0x0f           /* User Pins */
  76 
  77 /*
  78 ** EISA Configuration Register 2 bit definitions
  79 */
  80 #define ER2_BRS       0xc0           /* Boot ROM Size */
  81 #define ER2_BRA       0x3c           /* Boot ROM Address <16:13> */
  82 
  83 /*
  84 ** EISA Configuration Register 3 bit definitions
  85 */
  86 #define ER3_BWE       0x40           /* Burst Write Enable */
  87 #define ER3_BRE       0x04           /* Burst Read Enable */
  88 #define ER3_LSR       0x02           /* Local Software Reset */
  89 
  90 /*
  91 ** PCI Configuration ID Register (PCI_CFID)
  92 */
  93 #define CFID_DID    0xff00           /* Device ID */
  94 #define CFID_VID    0x00ff           /* Vendor ID */
  95 #define DC21040_DID 0x0002           /* Unique Device ID # */
  96 #define DC21040_VID 0x1011           /* DC21040 Manufacturer */
  97 
  98 /*
  99 ** PCI Configuration Command/Status Register (PCI_CFCS)
 100 */
 101 #define CFCS_DPE    0x80000000       /* Detected Parity Error (S) */
 102 #define CFCS_SSE    0x40000000       /* Signal System Error   (S) */
 103 #define CFCS_RMA    0x20000000       /* Receive Master Abort  (S) */
 104 #define CFCS_RTA    0x10000000       /* Receive Target Abort  (S) */
 105 #define CFCS_DST    0x06000000       /* DEVSEL Timing         (S) */
 106 #define CFCS_DPR    0x01000000       /* Data Parity Report    (S) */
 107 #define CFCS_FBB    0x00800000       /* Fast Back-To-Back     (S) */
 108 #define CFCS_SLE    0x00000100       /* System Error Enable   (C) */
 109 #define CFCS_PER    0x00000040       /* Parity Error Response (C) */
 110 #define CFCS_MO     0x00000004       /* Master Operation      (C) */
 111 #define CFCS_MSA    0x00000002       /* Memory Space Access   (C) */
 112 #define CFCS_IOSA   0x00000001       /* I/O Space Access      (C) */
 113 
 114 /*
 115 ** PCI Configuration Revision Register (PCI_CFRV)
 116 */
 117 #define CFRV_BC     0xff000000       /* Base Class */
 118 #define CFRV_SC     0x00ff0000       /* Subclass */
 119 #define CFRV_SN     0x000000f0       /* Step Number */
 120 #define CFRV_RN     0x0000000f       /* Revision Number */
 121 #define BASE_CLASS  0x02000000       /* Indicates Network Controller */
 122 #define SUB_CLASS   0x00000000       /* Indicates Ethernet Controller */
 123 #define STEP_NUMBER 0x00000020       /* Increments for future chips */
 124 #define REV_NUMBER  0x00000003       /* 0x00, 0x01, 0x02, 0x03: Rev in Step */
 125 #define CFRV_MASK   0xffff0000       /* Register mask */
 126 
 127 /*
 128 ** PCI Configuration Latency Timer Register (PCI_CFLT)
 129 */
 130 #define CFLT_BC     0x0000ff00       /* Latency Timer bits */
 131 
 132 /*
 133 ** PCI Configuration Base I/O Address Register (PCI_CBIO)
 134 */
 135 #define CBIO_MASK   0x0000ff80       /* Base I/O Address Mask */
 136 #define CBIO_IOSI   0x00000001       /* I/O Space Indicator (RO, value is 1) */
 137 
 138 /*
 139 ** DC21040 Bus Mode Register (DE4X5_BMR)
 140 */
 141 #define BMR_TAP    0x00060000       /* Transmit Automatic Polling */
 142 #define BMR_DAS    0x00010000       /* Diagnostic Address Space */
 143 #define BMR_CAL    0x0000c000       /* Cache Alignment */
 144 #define BMR_PBL    0x00003f00       /* Programmable Burst Length */
 145 #define BMR_BLE    0x00000080       /* Big/Little Endian */
 146 #define BMR_DSL    0x0000007c       /* Descriptor Skip Length */
 147 #define BMR_BAR    0x00000002       /* Bus ARbitration */
 148 #define BMR_SWR    0x00000001       /* Software Reset */
 149 
 150 #define TAP_NOPOLL 0x00000000       /* No automatic polling */
 151 #define TAP_200US  0x00020000       /* TX automatic polling every 200us */
 152 #define TAP_800US  0x00040000       /* TX automatic polling every 800us */
 153 #define TAP_1_6MS  0x00060000       /* TX automatic polling every 1.6ms */
 154 
 155 #define CAL_NOUSE  0x00000000       /* Not used */
 156 #define CAL_8LONG  0x00004000       /* 8-longword alignment */
 157 #define CAL_16LONG 0x00008000       /* 16-longword alignment */
 158 #define CAL_32LONG 0x0000c000       /* 32-longword alignment */
 159 
 160 #define PBL_0      0x00000000       /*  DMA burst length = amount in RX FIFO */
 161 #define PBL_1      0x00000100       /*  1 longword  DMA burst length */
 162 #define PBL_2      0x00000200       /*  2 longwords DMA burst length */
 163 #define PBL_4      0x00000400       /*  4 longwords DMA burst length */
 164 #define PBL_8      0x00000800       /*  8 longwords DMA burst length */
 165 #define PBL_16     0x00001000       /* 16 longwords DMA burst length */
 166 #define PBL_32     0x00002000       /* 32 longwords DMA burst length */
 167 
 168 #define DSL_1      0x00000004       /*  1 longword  / descriptor */
 169 #define DSL_2      0x00000008       /*  2 longwords / descriptor */
 170 #define DSL_4      0x00000010       /*  4 longwords / descriptor */
 171 #define DSL_8      0x00000020       /*  8 longwords / descriptor */
 172 #define DSL_16     0x00000040       /* 16 longwords / descriptor */
 173 #define DSL_32     0x00000080       /* 32 longwords / descriptor */
 174 
 175 /*
 176 ** DC21040 Transmit Poll Demand Register (DE4X5_TPD)
 177 */
 178 #define TPD        0x00000001       /* Transmit Poll Demand */
 179 
 180 /*
 181 ** DC21040 Receive Poll Demand Register (DE4X5_RPD)
 182 */
 183 #define RPD        0x00000001       /* Receive Poll Demand */
 184 
 185 /*
 186 ** DC21040 Receive Ring Base Address Register (DE4X5_RRBA)
 187 */
 188 #define RRBA       0xfffffffc       /* RX Descriptor List Start Address */
 189 
 190 /*
 191 ** DC21040 Transmit Ring Base Address Register (DE4X5_TRBA)
 192 */
 193 #define TRBA       0xfffffffc       /* TX Descriptor List Start Address */
 194 
 195 /*
 196 ** DC21040 Status Register (DE4X5_STS)
 197 */
 198 #define STS_EB     0x03800000       /* Error Bits */
 199 #define STS_TS     0x00700000       /* Transmit Process State */
 200 #define STS_RS     0x000e0000       /* Receive Process State */
 201 #define STS_NIS    0x00010000       /* Normal Interrupt Summary */
 202 #define STS_AIS    0x00008000       /* Abnormal Interrupt Summary */
 203 #define STS_SE     0x00002000       /* System Error */
 204 #define STS_LNF    0x00001000       /* Link Fail */
 205 #define STS_FD     0x00000800       /* Full-Duplex Short Frame Received */
 206 #define STS_AT     0x00000400       /* AUI/TP Pin */
 207 #define STS_RWT    0x00000200       /* Receive Watchdog Time-Out */
 208 #define STS_RPS    0x00000100       /* Receive Process Stopped */
 209 #define STS_RU     0x00000080       /* Receive Buffer Unavailable */
 210 #define STS_RI     0x00000040       /* Receive Interrupt */
 211 #define STS_UNF    0x00000020       /* Transmit Underflow */
 212 #define STS_TJT    0x00000008       /* Transmit Jabber Time-Out */
 213 #define STS_TU     0x00000004       /* Transmit Buffer Unavailable */
 214 #define STS_TPS    0x00000002       /* Transmit Process Stopped */
 215 #define STS_TI     0x00000001       /* Transmit Interrupt */
 216 
 217 #define EB_PAR     0x00000000       /* Parity Error */
 218 #define EB_MA      0x00800000       /* Master Abort */
 219 #define EB_TA      0x01000000       /* Target Abort */
 220 #define EB_RES0    0x01800000       /* Reserved */
 221 #define EB_RES1    0x02000000       /* Reserved */
 222 
 223 #define TS_STOP    0x00000000       /* Stopped */
 224 #define TS_FTD     0x00100000       /* Fetch Transmit Descriptor */
 225 #define TS_WEOT    0x00200000       /* Wait for End Of Transmission */
 226 #define TS_QDAT    0x00300000       /* Queue skb data into TX FIFO */
 227 #define TS_RES     0x00400000       /* Reserved */
 228 #define TS_SPKT    0x00500000       /* Setup Packet */
 229 #define TS_SUSP    0x00600000       /* Suspended */
 230 #define TS_CLTD    0x00700000       /* Close Transmit Descriptor */
 231 
 232 #define RS_STOP    0x00000000       /* Stopped */
 233 #define RS_FRD     0x00020000       /* Fetch Receive Descriptor */
 234 #define RS_CEOR    0x00040000       /* Check for End of Receive Packet */
 235 #define RS_WFRP    0x00060000       /* Wait for Receive Packet */
 236 #define RS_SUSP    0x00080000       /* Suspended */
 237 #define RS_CLRD    0x000a0000       /* Close Receive Descriptor */
 238 #define RS_FLUSH   0x000c0000       /* Flush RX FIFO */
 239 #define RS_QRFS    0x000e0000       /* Queue RX FIFO into RX Skb */
 240 
 241 #define INT_CANCEL 0x0001ffff       /* For zeroing all interrupt sources */
 242 
 243 /*
 244 ** DC21040 Operation Mode Register (DE4X5_OMR)
 245 */
 246 #define OMR_CA     0x00020000       /* Capture Effect Enable */
 247 #define OMR_BP     0x00010000       /* Back Pressure */
 248 #define OMR_TR     0x0000c000       /* Threshold Control Bits */
 249 #define OMR_ST     0x00002000       /* Start/Stop Transmission Command */
 250 #define OMR_FC     0x00001000       /* Force Collision Mode */
 251 #define OMR_OM     0x00000c00       /* Operating Mode */
 252 #define OMR_FD     0x00000200       /* Full Duplex Mode */
 253 #define OMR_FKD    0x00000100       /* Flaky Oscillator Disable */
 254 #define OMR_PM     0x00000080       /* Pass All Multicast */
 255 #define OMR_PR     0x00000040       /* Promiscuous Mode */
 256 #define OMR_SB     0x00000020       /* Start/Stop Backoff Counter */
 257 #define OMR_IF     0x00000010       /* Inverse Filtering */
 258 #define OMR_PB     0x00000008       /* Pass Bad Frames */
 259 #define OMR_HO     0x00000004       /* Hash Only Filtering Mode */
 260 #define OMR_SR     0x00000002       /* Start/Stop Receive */
 261 #define OMR_HP     0x00000001       /* Hash/Perfect Receive Filtering Mode */
 262 
 263 #define TR_72      0x00000000       /* Threshold set to 72 bytes */
 264 #define TR_96      0x00004000       /* Threshold set to 96 bytes */
 265 #define TR_128     0x00008000       /* Threshold set to 128 bytes */
 266 #define TR_160     0x0000c000       /* Threshold set to 160 bytes */
 267 
 268 /*
 269 ** DC21040 Interrupt Mask Register (DE4X5_IMR)
 270 */
 271 #define IMR_NIM    0x00010000       /* Normal Interrupt Summary Mask */
 272 #define IMR_AIM    0x00008000       /* Abnormal Interrupt Summary Mask */
 273 #define IMR_SEM    0x00002000       /* System Error Mask */
 274 #define IMR_LFM    0x00001000       /* Link Fail Mask */
 275 #define IMR_FDM    0x00000800       /* Full-Duplex Mask */
 276 #define IMR_ATM    0x00000400       /* AUI/TP Switch Mask */
 277 #define IMR_RWM    0x00000200       /* Receive Watchdog Time-Out Mask */
 278 #define IMR_RSM    0x00000100       /* Receive Stopped Mask */
 279 #define IMR_RUM    0x00000080       /* Receive Buffer Unavailable Mask */
 280 #define IMR_RIM    0x00000040       /* Receive Interrupt Mask */
 281 #define IMR_UNM    0x00000020       /* Underflow Interrupt Mask */
 282 #define IMR_TJM    0x00000008       /* Transmit Time-Out Jabber Mask */
 283 #define IMR_TUM    0x00000004       /* Transmit Buffer Unavailable Mask */
 284 #define IMR_TSM    0x00000002       /* Transmission Stopped Mask */
 285 #define IMR_TIM    0x00000001       /* Transmit Interrupt Mask */
 286 
 287 /*
 288 ** DC21040 Missed Frame Counter (DE4X5_MFC)
 289 */
 290 #define MFC_OVFL   0x00010000       /* Counter Overflow Bit */
 291 #define MFC_CNTR   0x0000ffff       /* Counter Bits */
 292 
 293 /*
 294 ** DC21040 Ethernet Address PROM (DE4X5_APROM)
 295 */
 296 #define APROM_DN   0x80000000       /* Data Not Valid */
 297 #define APROM_DT   0x000000ff       /* Address Byte */
 298 
 299 /*
 300 ** DC21040 Full Duplex Register (DE4X5_FDR)
 301 */
 302 #define FDR_FDACV  0x0000ffff       /* Full Duplex Auto Configuration Value */
 303 
 304 /*
 305 ** DC21040 SIA Status Register (DE4X5_SISR)
 306 */
 307 #define SISR_DAO   0x00000080       /* PLL All One */
 308 #define SISR_DAZ   0x00000040       /* PLL All Zero */
 309 #define SISR_DSP   0x00000020       /* PLL Self-Test Pass */
 310 #define SISR_DSD   0x00000010       /* PLL Self-Test Done */
 311 #define SISR_APS   0x00000008       /* Auto Polarity State */
 312 #define SISR_LKF   0x00000004       /* Link Fail Status */
 313 #define SISR_NCR   0x00000002       /* Network Connection Error */
 314 #define SISR_PAUI  0x00000001       /* AUI_TP Indication */
 315 
 316 #define SIA_RESET  0x00000000       /* SIA Reset */
 317 
 318 /*
 319 ** DC21040 SIA Connectivity Register (DE4X5_SICR)
 320 */
 321 #define SICR_OE57  0x00008000       /* Output Enable 5 6 7 */
 322 #define SICR_OE24  0x00004000       /* Output Enable 2 4 */
 323 #define SICR_OE13  0x00002000       /* Output Enable 1 3 */
 324 #define SICR_IE    0x00001000       /* Input Enable */
 325 #define SICR_EXT   0x00000000       /* SIA MUX Select External SIA Mode */
 326 #define SICR_D_SIA 0x00000400       /* SIA MUX Select Diagnostics - SIA Sigs */
 327 #define SICR_DPLL  0x00000800       /* SIA MUX Select Diagnostics - DPLL Sigs*/
 328 #define SICR_APLL  0x00000a00       /* SIA MUX Select Diagnostics - DPLL Sigs*/
 329 #define SICR_D_RxM 0x00000c00       /* SIA MUX Select Diagnostics - RxM Sigs */
 330 #define SICR_M_RxM 0x00000d00       /* SIA MUX Select Diagnostics - RxM Sigs */
 331 #define SICR_LNKT  0x00000e00       /* SIA MUX Select Diagnostics - Link Test*/
 332 #define SICR_SEL   0x00000f00       /* SIA MUX Select AUI or TP with LEDs */
 333 #define SICR_ASE   0x00000080       /* APLL Start Enable*/
 334 #define SICR_SIM   0x00000040       /* Serial Interface Input Multiplexer */
 335 #define SICR_ENI   0x00000020       /* Encoder Input Multiplexer */
 336 #define SICR_EDP   0x00000010       /* SIA PLL External Input Enable */
 337 #define SICR_AUI   0x00000008       /* 10Base-T or AUI */
 338 #define SICR_CAC   0x00000004       /* CSR Auto Configuration */
 339 #define SICR_PS    0x00000002       /* Pin AUI/TP Selection */
 340 #define SICR_SRL   0x00000001       /* SIA Reset */
 341 #define SICR_RESET 0xffff0000       /* Reset value for SICR */
 342 
 343 /*
 344 ** DC21040 SIA Transmit and Receive Register (DE4X5_STRR)
 345 */
 346 #define STRR_SPP   0x00004000       /* Set Polarity Plus */
 347 #define STRR_APE   0x00002000       /* Auto Polarity Enable */
 348 #define STRR_LTE   0x00001000       /* Link Test Enable */
 349 #define STRR_SQE   0x00000800       /* Signal Quality Enable */
 350 #define STRR_CLD   0x00000400       /* Collision Detect Enable */
 351 #define STRR_CSQ   0x00000200       /* Collision Squelch Enable */
 352 #define STRR_RSQ   0x00000100       /* Receive Squelch Enable */
 353 #define STRR_CPEN  0x00000030       /* Compensation Enable */
 354 #define STRR_LSE   0x00000008       /* Link Pulse Send Enable */
 355 #define STRR_DREN  0x00000004       /* Driver Enable */
 356 #define STRR_LBK   0x00000002       /* Loopback Enable */
 357 #define STRR_ECEN  0x00000001       /* Encoder Enable */
 358 #define STRR_RESET 0xffffffff       /* Reset value for STRR */
 359 
 360 /*
 361 ** DC21040 SIA General Register (DE4X5_SIGR)
 362 */
 363 #define SIGR_FRL   0x00002000       /* Force Receiver Low */
 364 #define SIGR_DPST  0x00001000       /* PLL Self Test Start */
 365 #define SIGR_FLF   0x00000400       /* Force Link Fail */
 366 #define SIGR_FUSQ  0x00000200       /* Force Unsquelch */
 367 #define SIGR_TSCK  0x00000100       /* Test Clock */
 368 #define SIGR_RWR   0x00000020       /* Receive Watchdog Release */
 369 #define SIGR_RWD   0x00000010       /* Receive Watchdog Disable */
 370 #define SIGR_JCK   0x00000004       /* Jabber Clock */
 371 #define SIGR_HUJ   0x00000002       /* Host Unjab */
 372 #define SIGR_JBD   0x00000001       /* Jabber Disable */
 373 #define SIGR_RESET 0xffff0000       /* Reset value for SIGR */
 374 
 375 /*
 376 ** Receive Descriptor Bit Summary
 377 */
 378 #define R_OWN      0x80000000       /* Own Bit */
 379 #define RD_FL      0x7fff0000       /* Frame Length */
 380 #define RD_ES      0x00008000       /* Error Summary */
 381 #define RD_LE      0x00004000       /* Length Error */
 382 #define RD_DT      0x00003000       /* Data Type */
 383 #define RD_RF      0x00000800       /* Runt Frame */
 384 #define RD_MF      0x00000400       /* Multicast Frame */
 385 #define RD_FS      0x00000200       /* First Descriptor */
 386 #define RD_LS      0x00000100       /* Last Descriptor */
 387 #define RD_TL      0x00000080       /* Frame Too Long */
 388 #define RD_CS      0x00000040       /* Collision Seen */
 389 #define RD_FT      0x00000020       /* Frame Type */
 390 #define RD_RJ      0x00000010       /* Receive Watchdog */
 391 #define RD_DB      0x00000004       /* Dribbling Bit */
 392 #define RD_CE      0x00000002       /* CRC Error */
 393 #define RD_OF      0x00000001       /* Overflow */
 394 
 395 #define RD_RER     0x02000000       /* Receive End Of Ring */
 396 #define RD_RCH     0x01000000       /* Second Address Chained */
 397 #define RD_RBS2    0x003ff800       /* Buffer 2 Size */
 398 #define RD_RBS1    0x000007ff       /* Buffer 1 Size */
 399 
 400 /*
 401 ** Transmit Descriptor Bit Summary
 402 */
 403 #define T_OWN      0x80000000       /* Own Bit */
 404 #define TD_ES      0x00008000       /* Error Summary */
 405 #define TD_TO      0x00004000       /* Transmit Jabber Time-Out */
 406 #define TD_LO      0x00000800       /* Loss Of Carrier */
 407 #define TD_NC      0x00000400       /* No Carrier */
 408 #define TD_LC      0x00000200       /* Late Collision */
 409 #define TD_EC      0x00000100       /* Excessive Collisions */
 410 #define TD_HF      0x00000080       /* Heartbeat Fail */
 411 #define TD_CC      0x00000078       /* Collision Counter */
 412 #define TD_LF      0x00000004       /* Link Fail */
 413 #define TD_UF      0x00000002       /* Underflow Error */
 414 #define TD_DE      0x00000001       /* Deferred */
 415 
 416 #define TD_IC      0x80000000       /* Interrupt On Completion */
 417 #define TD_LS      0x40000000       /* Last Segment */
 418 #define TD_FS      0x20000000       /* First Segment */
 419 #define TD_FT1     0x10000000       /* Filtering Type */
 420 #define TD_SET     0x08000000       /* Setup Packet */
 421 #define TD_AC      0x04000000       /* Add CRC Disable */
 422 #define TD_TER     0x02000000       /* Transmit End Of Ring */
 423 #define TD_TCH     0x01000000       /* Second Address Chained */
 424 #define TD_DPD     0x00800000       /* Disabled Padding */
 425 #define TD_FT0     0x00400000       /* Filtering Type */
 426 #define TD_RBS2    0x003ff800       /* Buffer 2 Size */
 427 #define TD_RBS1    0x000007ff       /* Buffer 1 Size */
 428 
 429 #define PERFECT_F  0x00000000
 430 #define HASH_F     TD_FT0
 431 #define INVERSE_F  TD_FT1
 432 #define HASH_O_F   TD_FT1| TD_F0
 433 
 434 /*
 435 ** Miscellaneous
 436 */
 437 #define PCI  0
 438 #define EISA 1
 439 
 440 #define NC         0               /* No Connection */
 441 #define TP         1               /* 10Base-T */
 442 #define BNC        2               /* Thinwire */
 443 #define AUI        3               /* Thickwire */
 444   
 445 #define HASH_TABLE_LEN   512       /* Bits */
 446 
 447 #define SETUP_FRAME_LEN  192       /* Bytes */
 448 #define PERF_PA_OFFSET   180       /* Bytes */
 449 #define IMPERF_PA_OFFSET 156       /* Bytes */
 450 
 451 #define POLL_DEMAND       1
 452 
 453 #define MASK_INTERRUPTS   1
 454 #define UNMASK_INTERRUPTS 0
 455 
 456 /*
 457 ** Include the IOCTL stuff
 458 */
 459 #include <linux/sockios.h>
 460 
 461 #define DE4X5IOCTL      SIOCDEVPRIVATE
 462 
 463 struct de4x5_ioctl {
 464         unsigned short cmd;                /* Command to run */
 465         unsigned short len;                /* Length of the data buffer */
 466         unsigned char  *data;              /* Pointer to the data buffer */
 467 };
 468 
 469 /* 
 470 ** Recognised commands for the driver 
 471 */
 472 #define DE4X5_GET_HWADDR        0x01 /* Get the hardware address */
 473 #define DE4X5_SET_HWADDR        0x02 /* Get the hardware address */
 474 #define DE4X5_SET_PROM          0x03 /* Set Promiscuous Mode */
 475 #define DE4X5_CLR_PROM          0x04 /* Clear Promiscuous Mode */
 476 #define DE4X5_SAY_BOO           0x05 /* Say "Boo!" to the kernel log file */
 477 #define DE4X5_GET_MCA           0x06 /* Get a multicast address */
 478 #define DE4X5_SET_MCA           0x07 /* Set a multicast address */
 479 #define DE4X5_CLR_MCA           0x08 /* Clear a multicast address */
 480 #define DE4X5_MCA_EN            0x09 /* Enable a multicast address group */
 481 #define DE4X5_GET_STATS         0x0a /* Get the driver statistics */
 482 #define DE4X5_CLR_STATS         0x0b /* Zero out the driver statistics */
 483 #define DE4X5_GET_OMR           0x0c /* Get the OMR Register contents */
 484 #define DE4X5_SET_OMR           0x0d /* Set the OMR Register contents */
 485 #define DE4X5_GET_REG           0x0e /* Get the DE4X5 Registers */
 486 
 487 
 488 

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