This source file includes following definitions.
- de4x5_probe
- de4x5_hw_init
- de4x5_open
- de4x5_init
- de4x5_queue_pkt
- de4x5_interrupt
- de4x5_rx
- de4x5_tx
- de4x5_close
- de4x5_get_stats
- load_packet
- set_multicast_list
- SetMulticastFilter
- eisa_probe
- pci_probe
- alloc_device
- autoconf_media
- dc21040_autoconf
- dc21041_autoconf
- dc21140_autoconf
- test_media
- ping_media
- test_ans
- reset_init_sia
- load_ms_timer
- create_packet
- dce_us_delay
- dce_ms_delay
- EISA_signature
- DevicePresent
- aprom_crc
- srom_rd
- srom_latch
- srom_command
- srom_address
- srom_data
- sendto_srom
- getfrom_srom
- build_setup_frame
- de4x5_ioctl
- init_module
- cleanup_module
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133 static char *version = "de4x5.c:v0.241 4/18/95 davies@wanton.lkg.dec.com\n";
134
135 #include <linux/config.h>
136 #ifdef MODULE
137 #include <linux/module.h>
138 #include <linux/version.h>
139 #else
140 #define MOD_INC_USE_COUNT
141 #define MOD_DEC_USE_COUNT
142 #endif
143
144 #include <linux/kernel.h>
145 #include <linux/sched.h>
146 #include <linux/string.h>
147 #include <linux/interrupt.h>
148 #include <linux/ptrace.h>
149 #include <linux/errno.h>
150 #include <linux/ioport.h>
151 #include <linux/malloc.h>
152 #include <linux/pci.h>
153 #include <linux/delay.h>
154 #include <asm/bitops.h>
155 #include <asm/io.h>
156 #include <asm/dma.h>
157 #include <asm/segment.h>
158
159 #include <linux/netdevice.h>
160 #include <linux/etherdevice.h>
161 #include <linux/skbuff.h>
162
163 #include <linux/time.h>
164 #include <linux/types.h>
165 #include <linux/unistd.h>
166
167 #include "de4x5.h"
168
169 #ifdef DE4X5_DEBUG
170 static int de4x5_debug = DE4X5_DEBUG;
171 #else
172 static int de4x5_debug = 1;
173 #endif
174
175 #ifdef DE4X5_AUTOSENSE
176 static int de4x5_autosense = DE4X5_AUTOSENSE;
177 #else
178 static int de4x5_autosense = AUTO;
179 #endif
180
181
182
183
184 #define PROBE_LENGTH 32
185 #define ETH_PROM_SIG 0xAA5500FFUL
186
187
188
189
190 #define PKT_BUF_SZ 1544
191 #define MAX_PKT_SZ 1514
192 #define MAX_DAT_SZ 1500
193 #define MIN_DAT_SZ 1
194 #define PKT_HDR_LEN 14
195
196 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
197 #define CRC_POLYNOMIAL_LE 0xedb88320UL
198
199
200
201
202 #define DE4X5_EISA_IO_PORTS 0x0c00
203 #define DE4X5_EISA_TOTAL_SIZE 0xfff
204
205 #define MAX_EISA_SLOTS 16
206 #define EISA_SLOT_INC 0x1000
207
208 #define DE4X5_SIGNATURE {"DE425",""}
209 #define DE4X5_NAME_LENGTH 8
210
211
212
213
214 #define PCI_MAX_BUS_NUM 8
215 #define DE4X5_PCI_TOTAL_SIZE 0x80
216
217
218
219
220
221
222
223 #define ALIGN4 ((u_long)4 - 1)
224 #define ALIGN8 ((u_long)8 - 1)
225 #define ALIGN16 ((u_long)16 - 1)
226 #define ALIGN32 ((u_long)32 - 1)
227 #define ALIGN64 ((u_long)64 - 1)
228 #define ALIGN128 ((u_long)128 - 1)
229
230 #define ALIGN ALIGN32
231 #define CACHE_ALIGN CAL_16LONG
232 #define DESC_SKIP_LEN DSL_0
233
234 #define DESC_ALIGN
235
236 #ifndef IS_NOT_DEC
237 static int is_not_dec = 0;
238 #else
239 static int is_not_dec = 1;
240 #endif
241
242
243
244
245 static u_long irq_mask = IMR_SEM | IMR_RIM | IMR_RUM | IMR_TIM | IMR_TUM ;
246
247 static u_long irq_en = IMR_NIM | IMR_AIM;
248
249 #define ENABLE_IRQs { \
250 imr |= irq_en;\
251 outl(imr, DE4X5_IMR); \
252 }
253
254 #define DISABLE_IRQs {\
255 imr = inl(DE4X5_IMR);\
256 imr &= ~irq_en;\
257 outl(imr, DE4X5_IMR); \
258 }
259
260 #define UNMASK_IRQs {\
261 imr |= irq_mask;\
262 outl(imr, DE4X5_IMR); \
263 }
264
265 #define MASK_IRQs {\
266 imr = inl(DE4X5_IMR);\
267 imr &= ~irq_mask;\
268 outl(imr, DE4X5_IMR); \
269 }
270
271
272
273
274 #define START_DE4X5 {\
275 omr = inl(DE4X5_OMR);\
276 omr |= OMR_ST | OMR_SR;\
277 outl(omr, DE4X5_OMR); \
278 }
279
280 #define STOP_DE4X5 {\
281 omr = inl(DE4X5_OMR);\
282 omr &= ~(OMR_ST|OMR_SR);\
283 outl(omr, DE4X5_OMR); \
284 }
285
286
287
288
289 #define RESET_SIA outl(0, DE4X5_SICR);
290
291
292
293
294 struct de4x5_srom {
295 char reserved[18];
296 char version;
297 char num_adapters;
298 char ieee_addr[6];
299 char info[100];
300 short chksum;
301 };
302
303
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305
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307
308
309
310 #define NUM_RX_DESC 8
311 #define NUM_TX_DESC 8
312 #define BUFF_ALLOC_RETRIES 10
313 #define RX_BUFF_SZ 1536
314
315
316 struct de4x5_desc {
317 volatile long status;
318 u_long des1;
319 char *buf;
320 char *next;
321 DESC_ALIGN
322 };
323
324
325
326
327 #define DE4X5_PKT_STAT_SZ 16
328 #define DE4X5_PKT_BIN_SZ 128
329
330
331 struct de4x5_private {
332 char adapter_name[80];
333 struct de4x5_desc rx_ring[NUM_RX_DESC];
334 struct de4x5_desc tx_ring[NUM_TX_DESC];
335 struct sk_buff *skb[NUM_TX_DESC];
336 int rx_new, rx_old;
337 int tx_new, tx_old;
338 char setup_frame[SETUP_FRAME_LEN];
339 struct enet_statistics stats;
340 struct {
341 unsigned long bins[DE4X5_PKT_STAT_SZ];
342 unsigned long unicast;
343 unsigned long multicast;
344 unsigned long broadcast;
345 unsigned long excessive_collisions;
346 unsigned long tx_underruns;
347 unsigned long excessive_underruns;
348 } pktStats;
349 char rxRingSize;
350 char txRingSize;
351 char bus;
352 u_short chipset;
353 long media;
354 int autosense;
355 int tx_enable;
356 char lostMedia;
357 int setup_f;
358 };
359
360
361
362
363
364
365
366
367
368 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
369 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
370 lp->tx_old -lp->tx_new-1)
371
372
373
374
375
376 static int de4x5_open(struct device *dev);
377 static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
378 static void de4x5_interrupt(int irq, struct pt_regs *regs);
379 static int de4x5_close(struct device *dev);
380 static struct enet_statistics *de4x5_get_stats(struct device *dev);
381 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
382 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
383
384
385
386
387 static int de4x5_hw_init(struct device *dev, short iobase);
388 static int de4x5_init(struct device *dev);
389 static int de4x5_rx(struct device *dev);
390 static int de4x5_tx(struct device *dev);
391
392 static int autoconf_media(struct device *dev);
393 static void create_packet(struct device *dev, char *frame, int len);
394 static void dce_us_delay(u_long usec);
395 static void dce_ms_delay(u_long msec);
396 static void load_packet(struct device *dev, char *buf, u_long flags, struct sk_buff *skb);
397 static void dc21040_autoconf(struct device *dev);
398 static void dc21041_autoconf(struct device *dev);
399 static void dc21140_autoconf(struct device *dev);
400 static long test_media(struct device *dev, long irqs, long irq_mask, long csr13, long csr14, long csr15, long msec);
401 static long ping_media(struct device *dev);
402 static void reset_init_sia(struct device *dev, long sicr, long strr, long sigr);
403 static int test_ans(struct device *dev, long irqs, long irq_mask, long msec);
404 static void load_ms_timer(struct device *dev, u_long msec);
405 static int EISA_signature(char *name, long eisa_id);
406 static int DevicePresent(short iobase);
407 static short srom_rd(u_short address, u_char offset);
408 static void srom_latch(u_long command, u_short address);
409 static void srom_command(u_long command, u_short address);
410 static void srom_address(u_long command, u_short address, u_char offset);
411 static short srom_data(u_long command, u_short address);
412
413 static void sendto_srom(u_long command, u_short addr);
414 static long getfrom_srom(u_short addr);
415 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs);
416 static int aprom_crc (struct device *dev);
417
418 static void eisa_probe(struct device *dev, short iobase);
419 static void pci_probe(struct device *dev, short iobase);
420 static struct device *alloc_device(struct device *dev, int iobase);
421 static char *build_setup_frame(struct device *dev, int mode);
422
423 #ifdef MODULE
424 int init_module(void);
425 void cleanup_module(void);
426 static int autoprobed = 1, loading_module = 1;
427 # else
428 static unsigned char de4x5_irq[] = {5,9,10,11};
429 static int autoprobed = 0, loading_module = 0;
430 #endif
431
432 static char name[DE4X5_NAME_LENGTH + 1];
433 static int num_de4x5s = 0, num_eth = 0;
434
435
436
437
438
439
440 static struct bus_type {
441 int bus;
442 int device;
443 int chipset;
444 struct de4x5_srom srom;
445 int autosense;
446 } bus;
447
448
449
450
451 #define RESET_DE4X5 {\
452 long i;\
453 i=inl(DE4X5_BMR);\
454 outl(i | BMR_SWR, DE4X5_BMR);\
455 outl(i, DE4X5_BMR);\
456 for (i=0;i<5;i++) inl(DE4X5_BMR);\
457 }
458
459
460
461 int de4x5_probe(struct device *dev)
462 {
463 int tmp = num_de4x5s, iobase = dev->base_addr;
464 int status = -ENODEV;
465
466 if ((iobase == 0) && loading_module){
467 printk("Autoprobing is not supported when loading a module based driver.\n");
468 status = -EIO;
469 } else {
470
471 eisa_probe(dev, iobase);
472 pci_probe(dev, iobase);
473
474 if ((tmp == num_de4x5s) && (iobase != 0)) {
475 printk("%s: de4x5_probe() cannot find device at 0x%04x.\n", dev->name,
476 iobase);
477 }
478
479
480
481
482
483 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
484
485 if (dev->priv) status = 0;
486 if (iobase == 0) autoprobed = 1;
487 }
488
489 return status;
490 }
491
492 static int
493 de4x5_hw_init(struct device *dev, short iobase)
494 {
495 struct bus_type *lp = &bus;
496 int tmpbus, tmpchs, i, j, status=0;
497 char *tmp;
498 u_long nicsr;
499
500
501 if (lp->chipset == DC21041) {
502 outl(0, PCI_CFDA);
503 dce_ms_delay(10);
504 }
505
506 RESET_DE4X5;
507
508 if (((nicsr=inl(DE4X5_STS)) & (STS_TS | STS_RS)) == 0) {
509
510
511
512 if (lp->bus == PCI) {
513 if (!is_not_dec) {
514 if ((lp->chipset == DC21040) || (lp->chipset == DC21041)) {
515 strcpy(name, "DE435");
516 } else if (lp->chipset == DC21140) {
517 strcpy(name, "DE500");
518 }
519 } else {
520 strcpy(name, "UNKNOWN");
521 }
522 } else {
523 EISA_signature(name, EISA_ID0);
524 }
525
526 if (*name != '\0') {
527 dev->base_addr = iobase;
528
529 if (lp->bus == EISA) {
530 printk("%s: %s at %#3x (EISA slot %d)",
531 dev->name, name, (u_short)iobase, (((u_short)iobase>>12)&0x0f));
532 } else {
533 printk("%s: %s at %#3x (PCI device %d)", dev->name, name, (u_short)iobase,lp->device);
534 }
535
536 printk(", h/w address ");
537 status = aprom_crc(dev);
538 for (i = 0; i < ETH_ALEN - 1; i++) {
539 printk("%2.2x:", dev->dev_addr[i]);
540 }
541 printk("%2.2x,\n", dev->dev_addr[i]);
542
543 tmpbus = lp->bus;
544 tmpchs = lp->chipset;
545
546 if (status == 0) {
547 struct de4x5_private *lp;
548
549
550
551
552
553 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
554 GFP_KERNEL);
555
556
557
558 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
559 lp = (struct de4x5_private *)dev->priv;
560 memset(dev->priv, 0, sizeof(struct de4x5_private));
561 lp->bus = tmpbus;
562 lp->chipset = tmpchs;
563
564
565
566
567 if (de4x5_autosense & AUTO) {
568 lp->autosense = AUTO;
569 } else {
570 if (lp->chipset != DC21140) {
571 if ((lp->chipset == DC21040) && (de4x5_autosense & TP_NW)) {
572 de4x5_autosense = TP;
573 }
574 if ((lp->chipset == DC21041) && (de4x5_autosense & BNC_AUI)) {
575 de4x5_autosense = BNC;
576 }
577 lp->autosense = de4x5_autosense & 0x001f;
578 } else {
579 lp->autosense = de4x5_autosense & 0x00c0;
580 }
581 }
582
583 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
584 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
585 DE4X5_EISA_TOTAL_SIZE),
586 lp->adapter_name);
587
588
589
590
591
592
593 for (tmp=NULL, j=0; (j<BUFF_ALLOC_RETRIES) && (tmp==NULL); j++) {
594 if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
595 GFP_KERNEL)) != NULL) {
596 tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
597 for (i=0; i<NUM_RX_DESC; i++) {
598 lp->rx_ring[i].status = 0;
599 lp->rx_ring[i].des1 = RX_BUFF_SZ;
600 lp->rx_ring[i].buf = tmp + i * RX_BUFF_SZ;
601 lp->rx_ring[i].next = NULL;
602 }
603 }
604 }
605
606 if (tmp != NULL) {
607 lp->rxRingSize = NUM_RX_DESC;
608 lp->txRingSize = NUM_TX_DESC;
609
610
611 lp->rx_ring[lp->rxRingSize - 1].des1 |= RD_RER;
612 lp->tx_ring[lp->txRingSize - 1].des1 |= TD_TER;
613
614
615 outl((long)lp->rx_ring, DE4X5_RRBA);
616 outl((long)lp->tx_ring, DE4X5_TRBA);
617
618 lp->tx_enable = TRUE;
619
620 if (dev->irq < 2) {
621 #ifndef MODULE
622 unsigned char irqnum;
623 u_long omr;
624 autoirq_setup(0);
625
626 omr = inl(DE4X5_OMR);
627 outl(IMR_AIM|IMR_RUM, DE4X5_IMR);
628 outl(OMR_SR | omr, DE4X5_OMR);
629
630 irqnum = autoirq_report(1);
631 if (!irqnum) {
632 printk(" and failed to detect IRQ line.\n");
633 status = -ENXIO;
634 } else {
635 for (dev->irq=0,i=0; (i<sizeof(de4x5_irq)) && (!dev->irq); i++) {
636 if (irqnum == de4x5_irq[i]) {
637 dev->irq = irqnum;
638 printk(" and uses IRQ%d.\n", dev->irq);
639 }
640 }
641
642 if (!dev->irq) {
643 printk(" but incorrect IRQ line detected.\n");
644 status = -ENXIO;
645 }
646 }
647
648 outl(0, DE4X5_IMR);
649
650 #endif
651 } else {
652 printk(" and requires IRQ%d (not probed).\n", dev->irq);
653 }
654 } else {
655 printk("%s: Kernel could not allocate RX buffer memory.\n",
656 dev->name);
657 status = -ENXIO;
658 }
659 if (status) release_region(iobase, (lp->bus == PCI ?
660 DE4X5_PCI_TOTAL_SIZE :
661 DE4X5_EISA_TOTAL_SIZE));
662 } else {
663 printk(" which has an Ethernet PROM CRC error.\n");
664 status = -ENXIO;
665 }
666 } else {
667 status = -ENXIO;
668 }
669 } else {
670 status = -ENXIO;
671 }
672
673 if (!status) {
674 if (de4x5_debug > 0) {
675 printk(version);
676 }
677
678
679 dev->open = &de4x5_open;
680 dev->hard_start_xmit = &de4x5_queue_pkt;
681 dev->stop = &de4x5_close;
682 dev->get_stats = &de4x5_get_stats;
683 #ifdef HAVE_MULTICAST
684 dev->set_multicast_list = &set_multicast_list;
685 #endif
686 dev->do_ioctl = &de4x5_ioctl;
687
688 dev->mem_start = 0;
689
690
691 ether_setup(dev);
692
693
694 if (lp->chipset == DC21041) {
695 outl(0, DE4X5_SICR);
696 outl(CFDA_PSM, PCI_CFDA);
697 }
698 } else {
699 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
700 if (lp) {
701 kfree_s(lp->rx_ring[0].buf, RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
702 }
703 if (dev->priv) {
704 kfree_s(dev->priv, sizeof(struct de4x5_private) + ALIGN);
705 dev->priv = NULL;
706 }
707 }
708
709 return status;
710 }
711
712
713 static int
714 de4x5_open(struct device *dev)
715 {
716 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
717 short iobase = dev->base_addr;
718 int i, status = 0;
719 long imr, omr, sts;
720
721
722
723
724 if (lp->chipset == DC21041) {
725 outl(0, PCI_CFDA);
726 dce_ms_delay(10);
727 }
728
729 if (request_irq(dev->irq, (void *)de4x5_interrupt, 0, lp->adapter_name)) {
730 printk("de4x5_open(): Requested IRQ%d is busy\n",dev->irq);
731 status = -EAGAIN;
732 } else {
733
734 irq2dev_map[dev->irq] = dev;
735
736
737
738 status = de4x5_init(dev);
739
740 if (de4x5_debug > 1){
741 printk("%s: de4x5 open with irq %d\n",dev->name,dev->irq);
742 printk("\tphysical address: ");
743 for (i=0;i<6;i++){
744 printk("%2.2x:",(short)dev->dev_addr[i]);
745 }
746 printk("\n");
747 printk("Descriptor head addresses:\n");
748 printk("\t0x%8.8lx 0x%8.8lx\n",(long)lp->rx_ring,(long)lp->tx_ring);
749 printk("Descriptor addresses:\nRX: ");
750 for (i=0;i<lp->rxRingSize-1;i++){
751 if (i < 3) {
752 printk("0x%8.8lx ",(long)&lp->rx_ring[i].status);
753 }
754 }
755 printk("...0x%8.8lx\n",(long)&lp->rx_ring[i].status);
756 printk("TX: ");
757 for (i=0;i<lp->txRingSize-1;i++){
758 if (i < 3) {
759 printk("0x%8.8lx ", (long)&lp->tx_ring[i].status);
760 }
761 }
762 printk("...0x%8.8lx\n", (long)&lp->tx_ring[i].status);
763 printk("Descriptor buffers:\nRX: ");
764 for (i=0;i<lp->rxRingSize-1;i++){
765 if (i < 3) {
766 printk("0x%8.8lx ",(long)lp->rx_ring[i].buf);
767 }
768 }
769 printk("...0x%8.8lx\n",(long)lp->rx_ring[i].buf);
770 printk("TX: ");
771 for (i=0;i<lp->txRingSize-1;i++){
772 if (i < 3) {
773 printk("0x%8.8lx ", (long)lp->tx_ring[i].buf);
774 }
775 }
776 printk("...0x%8.8lx\n", (long)lp->tx_ring[i].buf);
777 printk("Ring size: \nRX: %d\nTX: %d\n",
778 (short)lp->rxRingSize,
779 (short)lp->txRingSize);
780 printk("\tstatus: %d\n", status);
781 }
782
783 if (!status) {
784 dev->tbusy = 0;
785 dev->start = 1;
786 dev->interrupt = UNMASK_INTERRUPTS;
787 dev->trans_start = jiffies;
788
789 START_DE4X5;
790
791
792 imr = 0;
793 UNMASK_IRQs;
794
795
796 sts = inl(DE4X5_STS);
797 outl(sts, DE4X5_STS);
798
799 ENABLE_IRQs;
800 }
801 if (de4x5_debug > 1) {
802 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
803 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
804 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
805 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
806 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
807 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
808 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
809 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
810 }
811 }
812
813 MOD_INC_USE_COUNT;
814
815 return status;
816 }
817
818
819
820
821
822
823
824
825
826 static int
827 de4x5_init(struct device *dev)
828 {
829 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
830 short iobase = dev->base_addr;
831 int status = 0;
832 long i, j, bmr, omr;
833
834
835 set_bit(0, (void *)&dev->tbusy);
836
837 RESET_DE4X5;
838
839 bmr = inl(DE4X5_BMR);
840 bmr |= PBL_8 | DESC_SKIP_LEN | CACHE_ALIGN;
841 outl(bmr, DE4X5_BMR);
842
843 if (lp->chipset != DC21140) {
844 omr = TR_96;
845 lp->setup_f = HASH_PERF;
846 } else {
847 omr = OMR_SDP | OMR_SF;
848 lp->setup_f = PERFECT;
849 }
850 outl((long)lp->rx_ring, DE4X5_RRBA);
851 outl((long)lp->tx_ring, DE4X5_TRBA);
852
853 lp->rx_new = lp->rx_old = 0;
854 lp->tx_new = lp->tx_old = 0;
855
856 for (i = 0; i < lp->rxRingSize; i++) {
857 lp->rx_ring[i].status = R_OWN;
858 }
859
860 for (i = 0; i < lp->txRingSize; i++) {
861 lp->tx_ring[i].status = 0;
862 }
863
864
865 SetMulticastFilter(dev, 0, NULL);
866
867 if (lp->chipset != DC21140) {
868 load_packet(dev, lp->setup_frame, HASH_F|TD_SET|SETUP_FRAME_LEN, NULL);
869 } else {
870 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
871 }
872 outl(omr|OMR_ST, DE4X5_OMR);
873
874
875 for (j=0, i=0;(i<100) && (j==0);i++) {
876 if (lp->tx_ring[lp->tx_new].status >= 0) j=1;
877 }
878 outl(omr, DE4X5_OMR);
879
880 if (i == 100) {
881 printk("%s: Setup frame timed out, status %08x\n", dev->name,
882 inl(DE4X5_STS));
883 status = -EIO;
884 }
885
886 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
887 lp->tx_old = lp->tx_new;
888
889
890 if (autoconf_media(dev) == 0) {
891 status = -EIO;
892 }
893
894 return 0;
895 }
896
897
898
899
900 static int
901 de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
902 {
903 volatile struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
904 int iobase = dev->base_addr;
905 int status = 0;
906 u_long imr, omr, sts;
907
908 sts = inl(DE4X5_STS);
909
910
911
912
913
914
915 if (dev->tbusy || (lp->lostMedia > LOST_MEDIA_THRESHOLD)) {
916 int tickssofar = jiffies - dev->trans_start;
917 if (tickssofar < 10 && (lp->lostMedia <= LOST_MEDIA_THRESHOLD)) {
918 status = -1;
919 } else {
920 printk("%s: transmit timed out, status %08x, tbusy:%d, lostMedia:%d tickssofar:%d, resetting.\n",dev->name, inl(DE4X5_STS), dev->tbusy, lp->lostMedia, tickssofar);
921
922
923 STOP_DE4X5;
924 status = de4x5_init(dev);
925
926
927 if (!status) {
928
929 dev->interrupt = UNMASK_INTERRUPTS;
930 dev->start = 1;
931 dev->tbusy = 0;
932 dev->trans_start = jiffies;
933
934 START_DE4X5;
935
936
937 imr = 0;
938 UNMASK_IRQs;
939
940
941 sts = inl(DE4X5_STS);
942 outl(sts, DE4X5_STS);
943
944 ENABLE_IRQs;
945 } else {
946 printk("%s: hardware initialisation failure, status %08x.\n",
947 dev->name, inl(DE4X5_STS));
948 }
949 }
950 } else if (skb == NULL) {
951 dev_tint(dev);
952 } else if (skb->len > 0) {
953
954
955
956
957
958 if (set_bit(0, (void*)&dev->tbusy) != 0)
959 printk("%s: Transmitter access conflict.\n", dev->name);
960
961 if (TX_BUFFS_AVAIL) {
962 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
963 if (lp->tx_enable) {
964 outl(POLL_DEMAND, DE4X5_TPD);
965 }
966
967 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
968
969 dev->trans_start = jiffies;
970 }
971
972 if (TX_BUFFS_AVAIL) {
973 dev->tbusy = 0;
974 }
975 }
976
977 return status;
978 }
979
980
981
982
983 static void
984 de4x5_interrupt(int irq, struct pt_regs *regs)
985 {
986 struct device *dev = (struct device *)(irq2dev_map[irq]);
987 struct de4x5_private *lp;
988 int iobase;
989 u_long imr, omr, sts;
990
991 if (dev == NULL) {
992 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
993 } else {
994 lp = (struct de4x5_private *)dev->priv;
995 iobase = dev->base_addr;
996
997 if (dev->interrupt)
998 printk("%s: Re-entering the interrupt handler.\n", dev->name);
999
1000 dev->interrupt = MASK_INTERRUPTS;
1001
1002
1003
1004
1005
1006
1007
1008 sts = inl(DE4X5_STS);
1009 MASK_IRQs;
1010
1011 outl(sts, DE4X5_STS);
1012
1013 if (sts & (STS_RI | STS_RU))
1014 de4x5_rx(dev);
1015
1016 if (sts & (STS_TI | STS_TU))
1017 de4x5_tx(dev);
1018
1019 if (sts & STS_SE) {
1020 STOP_DE4X5;
1021 printk("%s: Fatal bus error occurred, sts=0x%08lx, device stopped.\n",
1022 dev->name, sts);
1023 }
1024
1025 if (TX_BUFFS_AVAIL && dev->tbusy) {
1026 dev->tbusy = 0;
1027 mark_bh(NET_BH);
1028 }
1029
1030 dev->interrupt = UNMASK_INTERRUPTS;
1031
1032 UNMASK_IRQs;
1033 }
1034
1035 return;
1036 }
1037
1038 static int
1039 de4x5_rx(struct device *dev)
1040 {
1041 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1042 int i, entry;
1043 volatile long status;
1044 char *buf;
1045
1046 for (entry = lp->rx_new; lp->rx_ring[entry].status >= 0;entry = lp->rx_new) {
1047 status = lp->rx_ring[entry].status;
1048
1049 if (status & RD_FS) {
1050 lp->rx_old = entry;
1051 }
1052
1053 if (status & RD_LS) {
1054 if (status & RD_ES) {
1055 lp->stats.rx_errors++;
1056 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1057 if (status & RD_CE) lp->stats.rx_crc_errors++;
1058 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1059 } else {
1060 struct sk_buff *skb;
1061 short pkt_len = (short)(lp->rx_ring[entry].status >> 16) - 4;
1062
1063 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1064 skb->len = pkt_len;
1065 skb->dev = dev;
1066
1067 if (entry < lp->rx_old) {
1068 short len = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
1069 memcpy(skb->data, lp->rx_ring[lp->rx_old].buf, len);
1070 memcpy(skb->data + len, lp->rx_ring[0].buf, pkt_len - len);
1071 } else {
1072 memcpy(skb->data, lp->rx_ring[lp->rx_old].buf, pkt_len);
1073 }
1074
1075
1076
1077
1078
1079 netif_rx(skb);
1080
1081
1082
1083
1084 lp->stats.rx_packets++;
1085 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1086 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1087 lp->pktStats.bins[i]++;
1088 i = DE4X5_PKT_STAT_SZ;
1089 }
1090 }
1091 buf = skb->data;
1092 if (buf[0] & 0x01) {
1093 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1094 lp->pktStats.broadcast++;
1095 } else {
1096 lp->pktStats.multicast++;
1097 }
1098 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1099 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1100 lp->pktStats.unicast++;
1101 }
1102
1103 lp->pktStats.bins[0]++;
1104 if (lp->pktStats.bins[0] == 0) {
1105 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1106 }
1107 } else {
1108 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1109 lp->stats.rx_dropped++;
1110 break;
1111 }
1112 }
1113
1114
1115 for (; lp->rx_old!=entry; lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1116 lp->rx_ring[lp->rx_old].status = R_OWN;
1117 }
1118 lp->rx_ring[entry].status = R_OWN;
1119 }
1120
1121
1122
1123
1124 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1125 }
1126
1127 return 0;
1128 }
1129
1130
1131
1132
1133 static int
1134 de4x5_tx(struct device *dev)
1135 {
1136 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1137 int entry, iobase = dev->base_addr;
1138 long status;
1139
1140 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1141 status = lp->tx_ring[entry].status;
1142 if (status < 0) {
1143 break;
1144 } else if (status & TD_ES) {
1145 lp->stats.tx_errors++;
1146 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1147 if (status & TD_LC) lp->stats.tx_window_errors++;
1148 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1149 if (status & TD_LC) lp->stats.collisions++;
1150 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1151 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1152
1153 if (status & (TD_LO | TD_NC | TD_EC | TD_LF)) {
1154 lp->lostMedia++;
1155 } else {
1156 outl(POLL_DEMAND, DE4X5_TPD);
1157 }
1158 } else {
1159 lp->stats.tx_packets++;
1160 lp->lostMedia = 0;
1161 }
1162
1163 if (lp->skb[entry] != NULL) {
1164 dev_kfree_skb(lp->skb[entry], FREE_WRITE);
1165 }
1166
1167
1168 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1169 }
1170
1171 return 0;
1172 }
1173
1174 static int
1175 de4x5_close(struct device *dev)
1176 {
1177 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1178 int iobase = dev->base_addr;
1179 u_long imr, omr;
1180
1181 dev->start = 0;
1182 dev->tbusy = 1;
1183
1184 if (de4x5_debug > 1) {
1185 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1186 dev->name, inl(DE4X5_STS));
1187 }
1188
1189
1190
1191
1192 DISABLE_IRQs;
1193
1194 STOP_DE4X5;
1195
1196
1197
1198
1199 free_irq(dev->irq);
1200 irq2dev_map[dev->irq] = 0;
1201
1202 MOD_DEC_USE_COUNT;
1203
1204
1205 if (lp->chipset == DC21041) {
1206 outl(0, DE4X5_SICR);
1207 outl(CFDA_PSM, PCI_CFDA);
1208 }
1209
1210 return 0;
1211 }
1212
1213 static struct enet_statistics *
1214 de4x5_get_stats(struct device *dev)
1215 {
1216 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1217 int iobase = dev->base_addr;
1218
1219 lp->stats.rx_missed_errors = (int) (inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1220
1221 return &lp->stats;
1222 }
1223
1224 static void load_packet(struct device *dev, char *buf, u_long flags, struct sk_buff *skb)
1225 {
1226 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1227
1228 lp->tx_ring[lp->tx_new].buf = buf;
1229 lp->tx_ring[lp->tx_new].des1 &= TD_TER;
1230 lp->tx_ring[lp->tx_new].des1 |= flags;
1231 lp->skb[lp->tx_new] = skb;
1232 lp->tx_ring[lp->tx_new].status = T_OWN;
1233
1234 return;
1235 }
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246 static void
1247 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1248 {
1249 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1250 int iobase = dev->base_addr;
1251
1252
1253 if (irq2dev_map[dev->irq] != NULL) {
1254 if (num_addrs >= 0) {
1255 SetMulticastFilter(dev, num_addrs, (char *)addrs);
1256 if (lp->setup_f == HASH_PERF) {
1257 load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
1258 SETUP_FRAME_LEN, NULL);
1259 } else {
1260 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1261 SETUP_FRAME_LEN, NULL);
1262 }
1263
1264 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1265 outl(POLL_DEMAND, DE4X5_TPD);
1266 dev->trans_start = jiffies;
1267 }
1268 }
1269
1270 return;
1271 }
1272
1273
1274
1275
1276
1277
1278 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs)
1279 {
1280 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1281 int i, j, bit, byte, iobase = dev->base_addr;
1282 u_short hashcode;
1283 u_long crc, omr, poly = CRC_POLYNOMIAL_LE;
1284 char *pa;
1285
1286 omr = inl(DE4X5_OMR);
1287 pa = build_setup_frame(dev, ALL);
1288
1289 if (lp->setup_f == HASH_PERF) {
1290 if (num_addrs == HASH_TABLE_LEN) {
1291 omr |= OMR_PM;
1292 } else {
1293 omr &= ~OMR_PM;
1294
1295 for (i=0;i<num_addrs;i++) {
1296 if ((*addrs & 0x01) == 1) {
1297 crc = 0xffffffff;
1298 for (byte=0;byte<ETH_ALEN;byte++) {
1299
1300 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1301 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1302 }
1303 }
1304 hashcode = crc & HASH_BITS;
1305
1306 byte = hashcode >> 3;
1307 bit = 1 << (hashcode & 0x07);
1308
1309 byte <<= 1;
1310 if (byte & 0x02) {
1311 byte -= 1;
1312 }
1313 lp->setup_frame[byte] |= bit;
1314
1315 } else {
1316 addrs += ETH_ALEN;
1317 }
1318 }
1319 }
1320 } else {
1321 omr &= ~OMR_PM;
1322 for (j=0; j<num_addrs; j++) {
1323 for (i=0; i<ETH_ALEN; i++) {
1324 *(pa + (i&1)) = *addrs++;
1325 if (i & 0x01) pa += 4;
1326 }
1327 }
1328 }
1329 outl(omr, DE4X5_OMR);
1330
1331 return;
1332 }
1333
1334
1335
1336
1337
1338 static void eisa_probe(struct device *dev, short ioaddr)
1339 {
1340 int i, maxSlots;
1341 int status;
1342 u_short vendor, device, iobase;
1343 struct bus_type *lp = &bus;
1344 char name[DE4X5_STRLEN];
1345 long cfid;
1346
1347 if (!ioaddr && autoprobed) return ;
1348 if ((ioaddr < 0x1000) && (ioaddr > 0)) return;
1349
1350 lp->bus = EISA;
1351
1352 if (ioaddr == 0) {
1353 iobase = EISA_SLOT_INC;
1354 i = 1;
1355 maxSlots = MAX_EISA_SLOTS;
1356 } else {
1357 iobase = ioaddr;
1358 i = (ioaddr >> 12);
1359 maxSlots = i + 1;
1360 }
1361
1362 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1363 if (EISA_signature(name, EISA_ID)) {
1364 cfid = inl(PCI_CFID);
1365 device = (u_short)(cfid >> 16);
1366 vendor = (u_short) cfid;
1367
1368 lp->bus = EISA;
1369 lp->chipset = device;
1370 if (DevicePresent(EISA_APROM) == 0) {
1371
1372 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
1373 outl(0x00004000, PCI_CFLT);
1374 outl((u_long)iobase, PCI_CBIO);
1375
1376 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
1377 if ((dev = alloc_device(dev, iobase)) != NULL) {
1378 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1379 num_de4x5s++;
1380 }
1381 num_eth++;
1382 }
1383 } else if (autoprobed) {
1384 printk("%s: region already allocated at 0x%04x.\n", dev->name, iobase);
1385 }
1386 }
1387 }
1388 }
1389
1390 return;
1391 }
1392
1393
1394
1395
1396 #define PCI_DEVICE (dev_num << 3)
1397 #define PCI_LAST_DEV 32
1398
1399 static void pci_probe(struct device *dev, short ioaddr)
1400
1401 {
1402 u_char irq;
1403 u_short pb, dev_num, dev_last;
1404 u_short vendor, device, status;
1405 u_long class, iobase;
1406 struct bus_type *lp = &bus;
1407
1408 if (!ioaddr && autoprobed) return ;
1409
1410 if (pcibios_present()) {
1411 lp->bus = PCI;
1412
1413 if (ioaddr < 0x1000) {
1414 pb = (u_short)(ioaddr >> 8);
1415 dev_num = (u_short)(ioaddr & 0xff);
1416 } else {
1417 pb = 0;
1418 dev_num = 0;
1419 }
1420 if (ioaddr > 0) {
1421 dev_last = (dev_num < PCI_LAST_DEV) ? dev_num + 1 : PCI_LAST_DEV;
1422 } else {
1423 dev_last = PCI_LAST_DEV;
1424 }
1425
1426 for (; (dev_num < dev_last) && (dev != NULL); dev_num++) {
1427 pcibios_read_config_dword(pb, PCI_DEVICE, PCI_CLASS_REVISION, &class);
1428 if (class != 0xffffffff) {
1429 pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
1430 pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &device);
1431 if (is_DC21040 || is_DC21041 || is_DC21140) {
1432
1433 lp->device = dev_num;
1434
1435
1436 lp->chipset = device;
1437
1438
1439 pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &iobase);
1440 iobase &= CBIO_MASK;
1441
1442
1443 pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &irq);
1444
1445
1446 pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
1447 status |= PCI_COMMAND_IO | PCI_COMMAND_MASTER;
1448 pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
1449
1450
1451 if ((DevicePresent(DE4X5_APROM) == 0) || is_not_dec) {
1452 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
1453 if ((dev = alloc_device(dev, iobase)) != NULL) {
1454 dev->irq = irq;
1455 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1456 num_de4x5s++;
1457 }
1458 num_eth++;
1459 }
1460 } else if (autoprobed) {
1461 printk("%s: region already allocated at 0x%04x.\n", dev->name, (u_short)iobase);
1462 }
1463 }
1464 }
1465 }
1466 }
1467 }
1468
1469 return;
1470 }
1471
1472
1473
1474
1475
1476 static struct device *alloc_device(struct device *dev, int iobase)
1477 {
1478 int addAutoProbe = 0;
1479 struct device *tmp = NULL, *ret;
1480 int (*init)(struct device *) = NULL;
1481
1482
1483
1484
1485 if (!loading_module) {
1486 while (dev->next != NULL) {
1487 if ((dev->base_addr == 0xffe0) || (dev->base_addr == 0)) break;
1488 dev = dev->next;
1489 num_eth++;
1490 }
1491
1492
1493
1494
1495
1496 if ((dev->base_addr == 0) && (num_de4x5s > 0)) {
1497 addAutoProbe++;
1498 tmp = dev->next;
1499 init = dev->init;
1500 }
1501
1502
1503
1504
1505
1506 if ((dev->next == NULL) &&
1507 !((dev->base_addr == 0xffe0) || (dev->base_addr == 0))){
1508 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1509 GFP_KERNEL);
1510
1511 dev = dev->next;
1512 if (dev == NULL) {
1513 printk("eth%d: Device not initialised, insufficient memory\n",
1514 num_eth);
1515 } else {
1516
1517
1518
1519
1520
1521 dev->name = (char *)(dev + sizeof(struct device));
1522 if (num_eth > 9999) {
1523 sprintf(dev->name,"eth????");
1524 } else {
1525 sprintf(dev->name,"eth%d", num_eth);
1526 }
1527 dev->base_addr = iobase;
1528 dev->next = NULL;
1529 dev->init = &de4x5_probe;
1530 num_de4x5s++;
1531 }
1532 }
1533 ret = dev;
1534
1535
1536
1537
1538
1539 if (ret != NULL) {
1540 if (addAutoProbe) {
1541 for (; (tmp->next!=NULL) && (tmp->base_addr!=0xffe0); tmp=tmp->next);
1542
1543
1544
1545
1546
1547 if ((tmp->next == NULL) && !(tmp->base_addr == 0xffe0)) {
1548 tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1549 GFP_KERNEL);
1550 tmp = tmp->next;
1551 if (tmp == NULL) {
1552 printk("%s: Insufficient memory to extend the device list.\n",
1553 dev->name);
1554 } else {
1555
1556
1557
1558
1559
1560 tmp->name = (char *)(tmp + sizeof(struct device));
1561 if (num_eth > 9999) {
1562 sprintf(tmp->name,"eth????");
1563 } else {
1564 sprintf(tmp->name,"eth%d", num_eth);
1565 }
1566 tmp->base_addr = 0;
1567 tmp->next = NULL;
1568 tmp->init = init;
1569 }
1570 } else {
1571 tmp->base_addr = 0;
1572 }
1573 }
1574 }
1575 } else {
1576 ret = dev;
1577 }
1578
1579 return ret;
1580 }
1581
1582
1583
1584
1585
1586
1587
1588 static int autoconf_media(struct device *dev)
1589 {
1590 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1591 int iobase = dev->base_addr;
1592
1593 if (lp->chipset == DC21040) {
1594 lp->media = (lp->autosense == AUTO ? TP : lp->autosense);
1595 dc21040_autoconf(dev);
1596 } else if (lp->chipset == DC21041) {
1597 lp->media = (lp->autosense == AUTO ? TP_NW : lp->autosense);
1598 dc21041_autoconf(dev);
1599 } else if (lp->chipset == DC21140) {
1600
1601 lp->media = (lp->autosense == AUTO ? _10Mb : lp->autosense);
1602 dc21140_autoconf(dev);
1603 }
1604
1605 if (de4x5_debug >= 1 ) {
1606 if (lp->chipset != DC21140) {
1607 printk("%s: Media is %s\n",dev->name,
1608 (lp->media == NC ? "unconnected!" :
1609 (lp->media == TP ? "TP." :
1610 (lp->media == ANS ? "TP/Nway." :
1611 (lp->media == BNC ? "BNC." :
1612 (lp->media == AUI ? "AUI." :
1613 "BNC/AUI."
1614 ))))));
1615 } else {
1616 printk("%s: Mode is forced to %s\n",dev->name,
1617 (lp->media == NC ? "link down.":
1618 (lp->media == _100Mb ? "100Mb/s." :
1619 (lp->media == _10Mb ? "10Mb/s." :
1620 "\?\?\?"
1621 ))));
1622 }
1623 }
1624
1625 if (lp->media) {
1626 lp->lostMedia = 0;
1627 inl(DE4X5_MFC);
1628 }
1629 dce_ms_delay(10);
1630
1631 return (lp->media);
1632 }
1633
1634 static void dc21040_autoconf(struct device *dev)
1635 {
1636 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1637 int iobase = dev->base_addr;
1638 u_long i, sisr = 0, linkBad;
1639 u_long t_3s = 3000;
1640
1641 switch (lp->media) {
1642 case TP:
1643 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1644 for (linkBad=1,i=0;(i<t_3s) && linkBad && !(sisr & SISR_NCR);i++) {
1645 if (((sisr = inl(DE4X5_SISR)) & SISR_LKF) == 0) linkBad = 0;
1646 dce_ms_delay(1);
1647 }
1648 if (linkBad && (lp->autosense == AUTO)) {
1649 lp->media = BNC_AUI;
1650 dc21040_autoconf(dev);
1651 }
1652 break;
1653
1654 case BNC:
1655 case AUI:
1656 case BNC_AUI:
1657 reset_init_sia(dev, 0x8f09, 0x0705, 0x0006);
1658 dce_ms_delay(330);
1659 linkBad = ping_media(dev);
1660 if (linkBad && (lp->autosense == AUTO)) {
1661 lp->media = NC;
1662 dc21040_autoconf(dev);
1663 }
1664 break;
1665
1666 case NC:
1667 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1668 break;
1669 }
1670
1671 return;
1672 }
1673
1674
1675
1676
1677
1678
1679
1680 static void dc21041_autoconf(struct device *dev)
1681 {
1682 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1683 int iobase = dev->base_addr;
1684 u_long sts, irqs, irq_mask, omr;
1685
1686 switch (lp->media) {
1687 case TP_NW:
1688 omr = inl(DE4X5_OMR);
1689 outl(omr | OMR_FD, DE4X5_OMR);
1690 irqs = STS_LNF | STS_LNP;
1691 irq_mask = IMR_LFM | IMR_LPM;
1692 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
1693 if (sts & STS_LNP) {
1694 lp->media = ANS;
1695 } else {
1696 lp->media = AUI;
1697 }
1698 dc21041_autoconf(dev);
1699 break;
1700
1701 case ANS:
1702 irqs = STS_LNP;
1703 irq_mask = IMR_LPM;
1704 sts = test_ans(dev, irqs, irq_mask, 3000);
1705 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1706 lp->media = TP;
1707 dc21041_autoconf(dev);
1708 }
1709 break;
1710
1711 case TP:
1712 omr = inl(DE4X5_OMR);
1713 outl(omr & ~OMR_FD, DE4X5_OMR);
1714 irqs = STS_LNF | STS_LNP;
1715 irq_mask = IMR_LFM | IMR_LPM;
1716 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
1717 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1718 if (inl(DE4X5_SISR) & SISR_NRA) {
1719 lp->media = AUI;
1720 } else {
1721 lp->media = BNC;
1722 }
1723 dc21041_autoconf(dev);
1724 }
1725 break;
1726
1727 case AUI:
1728 omr = inl(DE4X5_OMR);
1729 outl(omr & ~OMR_FD, DE4X5_OMR);
1730 irqs = 0;
1731 irq_mask = 0;
1732 sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x000e, 1000);
1733 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1734 lp->media = BNC;
1735 dc21041_autoconf(dev);
1736 }
1737 break;
1738
1739 case BNC:
1740 omr = inl(DE4X5_OMR);
1741 outl(omr & ~OMR_FD, DE4X5_OMR);
1742 irqs = 0;
1743 irq_mask = 0;
1744 sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x0006, 1000);
1745 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1746 lp->media = NC;
1747 } else {
1748 if (ping_media(dev)) lp->media = NC;
1749 }
1750 break;
1751
1752 case NC:
1753 omr = inl(DE4X5_OMR);
1754 outl(omr | OMR_FD, DE4X5_OMR);
1755 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);
1756 break;
1757 }
1758
1759 return;
1760 }
1761
1762
1763
1764
1765 static void dc21140_autoconf(struct device *dev)
1766 {
1767 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1768 int iobase = dev->base_addr;
1769 u_long omr;
1770
1771 switch(lp->media) {
1772 case _100Mb:
1773 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1774 outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);
1775 outl(GEP_FDXD | GEP_MODE, DE4X5_GEP);
1776 break;
1777
1778 case _10Mb:
1779 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1780 outl(omr | OMR_TTM, DE4X5_OMR);
1781 outl(GEP_FDXD, DE4X5_GEP);
1782 break;
1783 }
1784
1785 return;
1786 }
1787
1788 static long test_media(struct device *dev, long irqs, long irq_mask, long csr13, long csr14, long csr15, long msec)
1789 {
1790 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1791 int iobase = dev->base_addr;
1792 long sts, time, csr12;
1793
1794 reset_init_sia(dev, csr13, csr14, csr15);
1795
1796
1797 load_ms_timer(dev, msec);
1798
1799
1800 sts = inl(DE4X5_STS);
1801 outl(sts, DE4X5_STS);
1802
1803
1804 csr12 = inl(DE4X5_SISR);
1805 outl(csr12, DE4X5_SISR);
1806
1807
1808 do {
1809 time = inl(DE4X5_GPT) & GPT_VAL;
1810 sts = inl(DE4X5_STS);
1811 } while ((time != 0) && !(sts & irqs));
1812
1813 sts = inl(DE4X5_STS);
1814
1815 return sts;
1816 }
1817
1818
1819
1820
1821
1822 static long ping_media(struct device *dev)
1823 {
1824 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1825 int entry, iobase = dev->base_addr;
1826 char frame[64];
1827 long i, linkBad, omr;
1828 u_long t_3s = 3000;
1829
1830 create_packet(dev, frame, sizeof(frame));
1831
1832 entry = lp->tx_new;
1833 load_packet(dev, frame, TD_LS | TD_FS | sizeof(frame),NULL);
1834
1835 omr = inl(DE4X5_OMR);
1836 outl(omr|OMR_ST, DE4X5_OMR);
1837
1838 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1839 lp->tx_old = lp->tx_new;
1840
1841
1842 for (linkBad=1,i=0;(i<t_3s) && linkBad;i++) {
1843 if ((inl(DE4X5_SISR) & SISR_NCR) == 1) break;
1844 if (lp->tx_ring[entry].status >= 0) linkBad=0;
1845 dce_ms_delay(1);
1846 }
1847 outl(omr, DE4X5_OMR);
1848
1849 return ((linkBad || (lp->tx_ring[entry].status & TD_ES)) ? 1 : 0);
1850 }
1851
1852
1853
1854
1855
1856 static int test_ans(struct device *dev, long irqs, long irq_mask, long msec)
1857 {
1858 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1859 int iobase = dev->base_addr;
1860 long sts, ans;
1861
1862 outl(irq_mask, DE4X5_IMR);
1863
1864
1865 load_ms_timer(dev, msec);
1866
1867
1868 sts = inl(DE4X5_STS);
1869 outl(sts, DE4X5_STS);
1870
1871
1872 do {
1873 ans = inl(DE4X5_SISR) & SISR_ANS;
1874 sts = inl(DE4X5_STS);
1875 } while (!(sts & irqs) && (ans ^ ANS_NWOK) != 0);
1876
1877 return ((sts & STS_LNP) && ((ans ^ ANS_NWOK) == 0) ? STS_LNP : 0);
1878 }
1879
1880
1881
1882
1883 static void reset_init_sia(struct device *dev, long sicr, long strr, long sigr)
1884 {
1885 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1886 int iobase = dev->base_addr;
1887
1888 RESET_SIA;
1889 outl(sigr, DE4X5_SIGR);
1890 outl(strr, DE4X5_STRR);
1891 outl(sicr, DE4X5_SICR);
1892
1893 return;
1894 }
1895
1896
1897
1898
1899 static void load_ms_timer(struct device *dev, u_long msec)
1900 {
1901 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1902 int iobase = dev->base_addr;
1903
1904 outl((long)(msec * 10000)/2048, DE4X5_GPT);
1905
1906 return;
1907 }
1908
1909
1910
1911
1912 static void create_packet(struct device *dev, char *frame, int len)
1913 {
1914 int i;
1915 char *buf = frame;
1916
1917 for (i=0; i<ETH_ALEN; i++) {
1918 *buf++ = dev->dev_addr[i];
1919 }
1920 for (i=0; i<ETH_ALEN; i++) {
1921 *buf++ = dev->dev_addr[i];
1922 }
1923
1924 *buf++ = 0;
1925 *buf++ = 1;
1926
1927 return;
1928 }
1929
1930
1931
1932
1933 static void dce_us_delay(u_long usec)
1934 {
1935 udelay(usec);
1936
1937 return;
1938 }
1939
1940
1941
1942
1943 static void dce_ms_delay(u_long msec)
1944 {
1945 u_long i;
1946
1947 for (i=0; i<msec; i++) {
1948 dce_us_delay(1000);
1949 }
1950
1951 return;
1952 }
1953
1954
1955
1956
1957
1958 int EISA_signature(char *name, long eisa_id)
1959 {
1960 unsigned long i;
1961 char *signatures[] = DE4X5_SIGNATURE;
1962 char ManCode[DE4X5_STRLEN];
1963 union {
1964 long ID;
1965 char Id[4];
1966 } Eisa;
1967 int status = 0;
1968
1969 *name = '\0';
1970 Eisa.ID = inl(eisa_id);
1971
1972 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
1973 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
1974 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
1975 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
1976 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
1977 ManCode[5]='\0';
1978
1979 for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
1980 if (strstr(ManCode, signatures[i]) != NULL) {
1981 strcpy(name,ManCode);
1982 status = 1;
1983 }
1984 }
1985
1986 return status;
1987 }
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001 static int DevicePresent(short aprom_addr)
2002 {
2003 union {
2004 struct {
2005 u_long a;
2006 u_long b;
2007 } llsig;
2008 char Sig[sizeof(long) << 1];
2009 } dev;
2010 char data;
2011 long i, j, tmp;
2012 short sigLength;
2013 int status = 0;
2014 struct bus_type *lp = &bus;
2015
2016 dev.llsig.a = ETH_PROM_SIG;
2017 dev.llsig.b = ETH_PROM_SIG;
2018 sigLength = sizeof(long) << 1;
2019
2020 if (lp->chipset == DC21040) {
2021 for (i=0,j=0;(j<sigLength) && (i<PROBE_LENGTH+sigLength-1);i++) {
2022 if (lp->bus == PCI) {
2023 while ((tmp = inl(aprom_addr)) < 0);
2024 data = (char)tmp;
2025 } else {
2026 data = inb(aprom_addr);
2027 }
2028 if (dev.Sig[j] == data) {
2029 j++;
2030 } else {
2031 if (data == dev.Sig[0]) {
2032 j=1;
2033 } else {
2034 j=0;
2035 }
2036 }
2037 }
2038
2039 if (j!=sigLength) {
2040 status = -ENODEV;
2041 }
2042
2043 } else {
2044 short *p = (short *)&lp->srom;
2045 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
2046 *p++ = srom_rd(aprom_addr, i);
2047 }
2048 }
2049
2050 return status;
2051 }
2052
2053 static int aprom_crc(struct device *dev)
2054 {
2055 int iobase = dev->base_addr;
2056 long i, k, tmp;
2057 unsigned short j,chksum;
2058 unsigned char status = 0;
2059 struct bus_type *lp = &bus;
2060
2061 for (i=0,k=0,j=0;j<3;j++) {
2062 k <<= 1 ;
2063 if (k > 0xffff) k-=0xffff;
2064
2065 if (lp->bus == PCI) {
2066 if (lp->chipset == DC21040) {
2067 while ((tmp = inl(DE4X5_APROM)) < 0);
2068 k += (u_char) tmp;
2069 dev->dev_addr[i++] = (u_char) tmp;
2070 while ((tmp = inl(DE4X5_APROM)) < 0);
2071 k += (u_short) (tmp << 8);
2072 dev->dev_addr[i++] = (u_char) tmp;
2073 } else {
2074 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2075 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2076 }
2077 } else {
2078 k += (u_char) (tmp = inb(EISA_APROM));
2079 dev->dev_addr[i++] = (u_char) tmp;
2080 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
2081 dev->dev_addr[i++] = (u_char) tmp;
2082 }
2083
2084 if (k > 0xffff) k-=0xffff;
2085 }
2086 if (k == 0xffff) k=0;
2087
2088 if (lp->bus == PCI) {
2089 if (lp->chipset == DC21040) {
2090 while ((tmp = inl(DE4X5_APROM)) < 0);
2091 chksum = (u_char) tmp;
2092 while ((tmp = inl(DE4X5_APROM)) < 0);
2093 chksum |= (u_short) (tmp << 8);
2094 if (k != chksum) status = -1;
2095 }
2096 } else {
2097 chksum = (u_char) inb(EISA_APROM);
2098 chksum |= (u_short) (inb(EISA_APROM) << 8);
2099 if (k != chksum) status = -1;
2100 }
2101
2102
2103 return status;
2104 }
2105
2106
2107
2108
2109 static short srom_rd(u_short addr, u_char offset)
2110 {
2111 sendto_srom(SROM_RD | SROM_SR, addr);
2112
2113 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
2114 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
2115 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
2116
2117 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
2118 }
2119
2120 static void srom_latch(u_long command, u_short addr)
2121 {
2122 sendto_srom(command, addr);
2123 sendto_srom(command | DT_CLK, addr);
2124 sendto_srom(command, addr);
2125
2126 return;
2127 }
2128
2129 static void srom_command(u_long command, u_short addr)
2130 {
2131 srom_latch(command, addr);
2132 srom_latch(command, addr);
2133 srom_latch((command & 0x0000ff00) | DT_CS, addr);
2134
2135 return;
2136 }
2137
2138 static void srom_address(u_long command, u_short addr, u_char offset)
2139 {
2140 long i;
2141 char a;
2142
2143 a = (char)(offset << 2);
2144 for (i=0; i<6; i++, a <<= 1) {
2145 srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
2146 }
2147 dce_us_delay(1);
2148
2149 i = (getfrom_srom(addr) >> 3) & 0x01;
2150 if (i != 0) {
2151 printk("Bad SROM address phase.....\n");
2152 }
2153
2154 return;
2155 }
2156
2157 static short srom_data(u_long command, u_short addr)
2158 {
2159 int i;
2160 short word = 0;
2161 long tmp;
2162
2163 for (i=0; i<16; i++) {
2164 sendto_srom(command | DT_CLK, addr);
2165 tmp = getfrom_srom(addr);
2166 sendto_srom(command, addr);
2167
2168 word = (word << 1) | ((tmp >> 3) & 0x01);
2169 }
2170
2171 sendto_srom(command & 0x0000ff00, addr);
2172
2173 return word;
2174 }
2175
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191 static void sendto_srom(u_long command, u_short addr)
2192 {
2193 outl(command, addr);
2194 dce_us_delay(1);
2195
2196 return;
2197 }
2198
2199 static long getfrom_srom(u_short addr)
2200 {
2201 long tmp;
2202
2203 tmp = inl(addr);
2204 dce_us_delay(1);
2205
2206 return tmp;
2207 }
2208
2209 static char *build_setup_frame(struct device *dev, int mode)
2210 {
2211 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2212 int i;
2213 char *pa = lp->setup_frame;
2214
2215
2216 if (mode == ALL) {
2217 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
2218 }
2219
2220 if (lp->setup_f == HASH_PERF) {
2221 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
2222 *(pa + i) = dev->dev_addr[i];
2223 if (i & 0x01) pa += 2;
2224 }
2225 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
2226 } else {
2227 for (i=0; i<ETH_ALEN; i++) {
2228 *(pa + (i&1)) = dev->dev_addr[i];
2229 if (i & 0x01) pa += 4;
2230 }
2231 for (i=0; i<ETH_ALEN; i++) {
2232 *(pa + (i&1)) = (char) 0xff;
2233 if (i & 0x01) pa += 4;
2234 }
2235 }
2236
2237 return pa;
2238 }
2239
2240
2241
2242
2243
2244 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
2245 {
2246 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2247 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
2248 int i, j, iobase = dev->base_addr, status = 0;
2249 u_long omr;
2250 union {
2251 unsigned char addr[(HASH_TABLE_LEN * ETH_ALEN)];
2252 unsigned short sval[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
2253 unsigned long lval[(HASH_TABLE_LEN * ETH_ALEN) >> 2];
2254 } tmp;
2255
2256 switch(ioc->cmd) {
2257 case DE4X5_GET_HWADDR:
2258 for (i=0; i<ETH_ALEN; i++) {
2259 tmp.addr[i] = dev->dev_addr[i];
2260 }
2261 ioc->len = ETH_ALEN;
2262 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2263
2264 break;
2265 case DE4X5_SET_HWADDR:
2266 if (suser()) {
2267 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
2268 for (i=0; i<ETH_ALEN; i++) {
2269 dev->dev_addr[i] = tmp.addr[i];
2270 }
2271 build_setup_frame(dev, PHYS_ADDR_ONLY);
2272
2273 while (set_bit(0, (void *)&dev->tbusy) != 0);
2274 if (lp->setup_f == HASH_PERF) {
2275 load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
2276 SETUP_FRAME_LEN, NULL);
2277 } else {
2278 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2279 SETUP_FRAME_LEN, NULL);
2280 }
2281 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2282 outl(POLL_DEMAND, DE4X5_TPD);
2283 dev->tbusy = 0;
2284
2285 } else {
2286 status = -EPERM;
2287 }
2288
2289 break;
2290 case DE4X5_SET_PROM:
2291 if (suser()) {
2292 omr = inl(DE4X5_OMR);
2293 omr |= OMR_PR;
2294 outl(omr, DE4X5_OMR);
2295 } else {
2296 status = -EPERM;
2297 }
2298
2299 break;
2300 case DE4X5_CLR_PROM:
2301 if (suser()) {
2302 omr = inl(DE4X5_OMR);
2303 omr &= ~OMR_PR;
2304 outb(omr, DE4X5_OMR);
2305 } else {
2306 status = -EPERM;
2307 }
2308
2309 break;
2310 case DE4X5_SAY_BOO:
2311 printk("%s: Boo!\n", dev->name);
2312
2313 break;
2314 case DE4X5_GET_MCA:
2315 ioc->len = (HASH_TABLE_LEN >> 3);
2316 memcpy_tofs(ioc->data, lp->setup_frame, 192);
2317
2318 break;
2319 case DE4X5_SET_MCA:
2320 if (suser()) {
2321 if (ioc->len != HASH_TABLE_LEN) {
2322 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
2323 }
2324 set_multicast_list(dev, ioc->len, tmp.addr);
2325 } else {
2326 status = -EPERM;
2327 }
2328
2329 break;
2330 case DE4X5_CLR_MCA:
2331 if (suser()) {
2332 set_multicast_list(dev, 0, NULL);
2333 } else {
2334 status = -EPERM;
2335 }
2336
2337 break;
2338 case DE4X5_MCA_EN:
2339 if (suser()) {
2340 omr = inl(DE4X5_OMR);
2341 omr |= OMR_PM;
2342 outl(omr, DE4X5_OMR);
2343 } else {
2344 status = -EPERM;
2345 }
2346
2347 break;
2348 case DE4X5_GET_STATS:
2349 cli();
2350 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
2351 ioc->len = DE4X5_PKT_STAT_SZ;
2352 sti();
2353
2354 break;
2355 case DE4X5_CLR_STATS:
2356 if (suser()) {
2357 cli();
2358 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
2359 sti();
2360 } else {
2361 status = -EPERM;
2362 }
2363
2364 break;
2365 case DE4X5_GET_OMR:
2366 tmp.addr[0] = inl(DE4X5_OMR);
2367 memcpy_tofs(ioc->data, tmp.addr, 1);
2368
2369 break;
2370 case DE4X5_SET_OMR:
2371 if (suser()) {
2372 memcpy_fromfs(tmp.addr, ioc->data, 1);
2373 outl(tmp.addr[0], DE4X5_OMR);
2374 } else {
2375 status = -EPERM;
2376 }
2377
2378 break;
2379 case DE4X5_GET_REG:
2380 tmp.lval[0] = inl(DE4X5_STS);
2381 tmp.lval[1] = inl(DE4X5_BMR);
2382 tmp.lval[2] = inl(DE4X5_IMR);
2383 tmp.lval[3] = inl(DE4X5_OMR);
2384 tmp.lval[4] = inl(DE4X5_SISR);
2385 tmp.lval[5] = inl(DE4X5_SICR);
2386 tmp.lval[6] = inl(DE4X5_STRR);
2387 tmp.lval[7] = inl(DE4X5_SIGR);
2388 memcpy_tofs(ioc->data, tmp.addr, 32);
2389
2390 break;
2391
2392 #define DE4X5_DUMP 0x0f
2393
2394 case DE4X5_DUMP:
2395 j = 0;
2396 tmp.addr[j++] = dev->irq;
2397 for (i=0; i<ETH_ALEN; i++) {
2398 tmp.addr[j++] = dev->dev_addr[i];
2399 }
2400 tmp.addr[j++] = lp->rxRingSize;
2401 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
2402 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
2403
2404 for (i=0;i<lp->rxRingSize-1;i++){
2405 if (i < 3) {
2406 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2407 }
2408 }
2409 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2410 for (i=0;i<lp->txRingSize-1;i++){
2411 if (i < 3) {
2412 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2413 }
2414 }
2415 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2416
2417 for (i=0;i<lp->rxRingSize-1;i++){
2418 if (i < 3) {
2419 tmp.lval[j>>2] = (long)lp->rx_ring[i].buf; j+=4;
2420 }
2421 }
2422 tmp.lval[j>>2] = (long)lp->rx_ring[i].buf; j+=4;
2423 for (i=0;i<lp->txRingSize-1;i++){
2424 if (i < 3) {
2425 tmp.lval[j>>2] = (long)lp->tx_ring[i].buf; j+=4;
2426 }
2427 }
2428 tmp.lval[j>>2] = (long)lp->tx_ring[i].buf; j+=4;
2429
2430 for (i=0;i<lp->rxRingSize;i++){
2431 tmp.lval[j>>2] = lp->rx_ring[i].status; j+=4;
2432 }
2433 for (i=0;i<lp->txRingSize;i++){
2434 tmp.lval[j>>2] = lp->tx_ring[i].status; j+=4;
2435 }
2436
2437 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
2438 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
2439 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
2440 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
2441 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
2442 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
2443 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
2444 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
2445
2446 tmp.addr[j++] = lp->txRingSize;
2447 tmp.addr[j++] = dev->tbusy;
2448
2449 ioc->len = j;
2450 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2451
2452 break;
2453 default:
2454 status = -EOPNOTSUPP;
2455 }
2456
2457 return status;
2458 }
2459
2460 #ifdef MODULE
2461 char kernel_version[] = UTS_RELEASE;
2462 static struct device thisDE4X5 = {
2463 " ",
2464 0, 0, 0, 0,
2465 0x2000, 10,
2466 0, 0, 0, NULL, de4x5_probe };
2467
2468 int io=0x000b;
2469 int irq=10;
2470
2471 int
2472 init_module(void)
2473 {
2474 thisDE4X5.base_addr=io;
2475 thisDE4X5.irq=irq;
2476 if (register_netdev(&thisDE4X5) != 0)
2477 return -EIO;
2478 return 0;
2479 }
2480
2481 void
2482 cleanup_module(void)
2483 {
2484 struct de4x5_private *lp = (struct de4x5_private *) thisDE4X5.priv;
2485
2486 if (MOD_IN_USE) {
2487 printk("%s: device busy, remove delayed\n",thisDE4X5.name);
2488 } else {
2489 release_region(thisDE4X5.base_addr, (lp->bus == PCI ?
2490 DE4X5_PCI_TOTAL_SIZE :
2491 DE4X5_EISA_TOTAL_SIZE));
2492 if (lp) {
2493 kfree_s(lp->rx_ring[0].buf, RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
2494 }
2495 kfree_s(thisDE4X5.priv, sizeof(struct de4x5_private) + ALIGN);
2496 thisDE4X5.priv = NULL;
2497
2498 unregister_netdev(&thisDE4X5);
2499 }
2500 }
2501 #endif
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