root/include/linux/cyclades.h

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INCLUDED FROM


   1 struct cyclades_card {
   2     int base_addr;
   3     int irq;
   4     int num_chips; /* implies card type, 0 if card is absent */
   5     int first_line; /* line number of first channel of first chip on card */
   6 };
   7 
   8 struct cyclades_chip {
   9   int filler;
  10 };
  11 
  12 struct cyclades_monitor {
  13         unsigned long           int_count;
  14         unsigned long           char_count;
  15         unsigned long           char_max;
  16         unsigned long           char_last;
  17 };
  18 
  19 /*
  20  * This is our internal structure for each serial port's state.
  21  * 
  22  * Many fields are paralleled by the structure used by the serial_struct
  23  * structure.
  24  *
  25  * For definitions of the flags field, see tty.h
  26  */
  27 
  28 struct cyclades_port {
  29         int                     magic;
  30         int                     type;
  31         int                     card;
  32         int                     line;
  33         int                     flags;          /* defined in tty.h */
  34         struct tty_struct       *tty;
  35         int                     read_status_mask;
  36         int                     timeout;
  37         int                     xmit_fifo_size;
  38         int                     cor1,cor2,cor3,cor4,cor5;
  39         int                     tbpr,tco,rbpr,rco;
  40         int                     ignore_status_mask;
  41         int                     close_delay;
  42         int                     IER;    /* Interrupt Enable Register */
  43         int                     event;
  44         unsigned long           last_active;
  45         int                     count;  /* # of fd on device */
  46         int                     x_char; /* to be pushed out ASAP */
  47         int                     x_break;
  48         int                     blocked_open; /* # of blocked opens */
  49         long                    session; /* Session of opening process */
  50         long                    pgrp; /* pgrp of opening process */
  51         unsigned char           *xmit_buf;
  52         int                     xmit_head;
  53         int                     xmit_tail;
  54         int                     xmit_cnt;
  55         int                     default_threshold;
  56         int                     default_timeout;
  57         struct tq_struct        tqueue;
  58         struct termios          normal_termios;
  59         struct termios          callout_termios;
  60         struct wait_queue       *open_wait;
  61         struct wait_queue       *close_wait;
  62         struct cyclades_monitor mon;
  63 };
  64 
  65 #define CYCLADES_MAGIC  0x4359
  66 
  67 #define CYGETMON                0x435901
  68 #define CYGETTHRESH             0x435902
  69 #define CYSETTHRESH             0x435903
  70 #define CYGETDEFTHRESH          0x435904
  71 #define CYSETDEFTHRESH          0x435905
  72 #define CYGETTIMEOUT            0x435906
  73 #define CYSETTIMEOUT            0x435907
  74 #define CYGETDEFTIMEOUT         0x435908
  75 #define CYSETDEFTIMEOUT         0x435909
  76 
  77 /*
  78  * Events are used to schedule things to happen at timer-interrupt
  79  * time, instead of at cy interrupt time.
  80  */
  81 #define Cy_EVENT_READ_PROCESS   0
  82 #define Cy_EVENT_WRITE_WAKEUP   1
  83 #define Cy_EVENT_HANGUP         2
  84 #define Cy_EVENT_BREAK          3
  85 #define Cy_EVENT_OPEN_WAKEUP    4
  86 
  87 
  88 
  89 #define CyMaxChipsPerCard 8
  90 
  91 /**** CD1400 registers ****/
  92 
  93 #define CyRegSize  0x0400
  94 #define Cy_HwReset 0x1400
  95 #define Cy_ClrIntr 0x1800
  96 
  97 /* Global Registers */
  98 
  99 #define CyGFRCR         (0x40*2)
 100 #define      CyRevE             (44)
 101 #define CyCAR           (0x68*2)
 102 #define      CyCHAN_0           (0x00)
 103 #define      CyCHAN_1           (0x01)
 104 #define      CyCHAN_2           (0x02)
 105 #define      CyCHAN_3           (0x03)
 106 #define CyGCR           (0x4B*2)
 107 #define      CyCH0_SERIAL       (0x00)
 108 #define      CyCH0_PARALLEL     (0x80)
 109 #define CySVRR          (0x67*2)
 110 #define      CySRModem          (0x04)
 111 #define      CySRTransmit       (0x02)
 112 #define      CySRReceive        (0x01)
 113 #define CyRICR          (0x44*2)
 114 #define CyTICR          (0x45*2)
 115 #define CyMICR          (0x46*2)
 116 #define      CyICR0             (0x00)
 117 #define      CyICR1             (0x01)
 118 #define      CyICR2             (0x02)
 119 #define      CyICR3             (0x03)
 120 #define CyRIR           (0x6B*2)
 121 #define CyTIR           (0x6A*2)
 122 #define CyMIR           (0x69*2)
 123 #define      CyIRDirEq          (0x80)
 124 #define      CyIRBusy           (0x40)
 125 #define      CyIRUnfair         (0x20)
 126 #define      CyIRContext        (0x1C)
 127 #define      CyIRChannel        (0x03)
 128 #define CyPPR           (0x7E*2)
 129 #define      CyCLOCK_20_1MS     (0x27)
 130 #define      CyCLOCK_25_1MS     (0x31)
 131 
 132 /* Virtual Registers */
 133 
 134 #define CyRIVR          (0x43*2)
 135 #define CyTIVR          (0x42*2)
 136 #define CyMIVR          (0x41*2)
 137 #define      CyIVRMask (0x07)
 138 #define      CyIVRRxEx (0x07)
 139 #define      CyIVRRxOK (0x03)
 140 #define      CyIVRTxOK (0x02)
 141 #define      CyIVRMdmOK (0x01)
 142 #define CyTDR           (0x63*2)
 143 #define CyRDSR          (0x62*2)
 144 #define      CyTIMEOUT          (0x80)
 145 #define      CySPECHAR          (0x70)
 146 #define      CyBREAK            (0x08)
 147 #define      CyPARITY           (0x04)
 148 #define      CyFRAME            (0x02)
 149 #define      CyOVERRUN          (0x01)
 150 #define CyMISR          (0x4C*2)
 151 /* see CyMCOR_ and CyMSVR_ for bits*/
 152 #define CyEOSRR         (0x60*2)
 153 
 154 /* Channel Registers */
 155 
 156 #define CyLIVR          (0x18*2)
 157 #define      CyMscsr            (0x01)
 158 #define      CyTdsr             (0x02)
 159 #define      CyRgdsr            (0x03)
 160 #define      CyRedsr            (0x07)
 161 #define CyCCR           (0x05*2)
 162 /* Format 1 */
 163 #define      CyCHAN_RESET       (0x80)
 164 #define      CyCHIP_RESET       (0x81)
 165 #define      CyFlushTransFIFO   (0x82)
 166 /* Format 2 */
 167 #define      CyCOR_CHANGE       (0x40)
 168 #define      CyCOR1ch           (0x02)
 169 #define      CyCOR2ch           (0x04)
 170 #define      CyCOR3ch           (0x08)
 171 /* Format 3 */
 172 #define      CySEND_SPEC_1      (0x21)
 173 #define      CySEND_SPEC_2      (0x22)
 174 #define      CySEND_SPEC_3      (0x23)
 175 #define      CySEND_SPEC_4      (0x24)
 176 /* Format 4 */
 177 #define      CyCHAN_CTL         (0x10)
 178 #define      CyDIS_RCVR         (0x01)
 179 #define      CyENB_RCVR         (0x02)
 180 #define      CyDIS_XMTR         (0x04)
 181 #define      CyENB_XMTR         (0x08)
 182 #define CySRER          (0x06*2)
 183 #define      CyMdmCh            (0x80)
 184 #define      CyRxData           (0x10)
 185 #define      CyTxRdy            (0x04)
 186 #define      CyTxMpty           (0x02)
 187 #define      CyNNDT             (0x01)
 188 #define CyCOR1          (0x08*2)
 189 #define      CyPARITY_NONE      (0x00)
 190 #define      CyPARITY_0         (0x20)
 191 #define      CyPARITY_1         (0xA0)
 192 #define      CyPARITY_E         (0x40)
 193 #define      CyPARITY_O         (0xC0)
 194 #define      Cy_1_STOP          (0x00)
 195 #define      Cy_1_5_STOP        (0x04)
 196 #define      Cy_2_STOP          (0x08)
 197 #define      Cy_5_BITS          (0x00)
 198 #define      Cy_6_BITS          (0x01)
 199 #define      Cy_7_BITS          (0x02)
 200 #define      Cy_8_BITS          (0x03)
 201 #define CyCOR2          (0x09*2)
 202 #define      CyIXM              (0x80)
 203 #define      CyTxIBE            (0x40)
 204 #define      CyETC              (0x20)
 205 #define      CyAUTO_TXFL        (0x60)
 206 #define      CyLLM              (0x10)
 207 #define      CyRLM              (0x08)
 208 #define      CyRtsAO            (0x04)
 209 #define      CyCtsAE            (0x02)
 210 #define      CyDsrAE            (0x01)
 211 #define CyCOR3          (0x0A*2)
 212 #define      CySPL_CH_DRANGE    (0x80)  /* special character detect range */
 213 #define      CySPL_CH_DET1      (0x40)  /* enable special character detection
 214                                                                on SCHR4-SCHR3 */
 215 #define      CyFL_CTRL_TRNSP    (0x20)  /* Flow Control Transparency */
 216 #define      CySPL_CH_DET2      (0x10)  /* Enable special character detection
 217                                                                on SCHR2-SCHR1 */
 218 #define      CyREC_FIFO         (0x0F)  /* Receive FIFO threshold */
 219 #define CyCOR4          (0x1E*2)
 220 #define CyCOR5          (0x1F*2)
 221 #define CyCCSR          (0x0B*2)
 222 #define      CyRxEN             (0x80)
 223 #define      CyRxFloff          (0x40)
 224 #define      CyRxFlon           (0x20)
 225 #define      CyTxEN             (0x08)
 226 #define      CyTxFloff          (0x04)
 227 #define      CyTxFlon           (0x02)
 228 #define CyRDCR          (0x0E*2)
 229 #define CySCHR1         (0x1A*2)
 230 #define CySCHR2         (0x1B*2)
 231 #define CySCHR3         (0x1C*2)
 232 #define CySCHR4         (0x1D*2)
 233 #define CySCRL          (0x22*2)
 234 #define CySCRH          (0x23*2)
 235 #define CyLNC           (0x24*2)
 236 #define CyMCOR1         (0x15*2)
 237 #define CyMCOR2         (0x16*2)
 238 #define CyRTPR          (0x21*2)
 239 #define CyMSVR1         (0x6C*2)
 240 #define CyMSVR2         (0x6D*2)
 241 #define      CyDSR              (0x80)
 242 #define      CyCTS              (0x40)
 243 #define      CyRI               (0x20)
 244 #define      CyDCD              (0x10)
 245 #define      CyDTR              (0x02)
 246 #define      CyRTS              (0x01)
 247 #define CyPVSR          (0x6F*2)
 248 #define CyRBPR          (0x78*2)
 249 #define CyRCOR          (0x7C*2)
 250 #define CyTBPR          (0x72*2)
 251 #define CyTCOR          (0x76*2)
 252 
 253 /* max number of chars in the FIFO */
 254 
 255 #define CyMAX_CHAR_FIFO 12
 256 
 257 /***************************************************************************/

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