arch/mips/kernel/cache.S

/* */
   1 /*
   2  * arch/mips/kernel/cache.S
   3  *
   4  * Copyright (C) 1994, 1995 Waldorf Electronics
   5  * Written by Ralf Baechle
   6  *
   7  * Flush instruction/data caches
   8  *
   9  * Parameters: a0 - starting address to flush
  10  *             a1 - size of area to be flushed
  11  *             a2 - which caches to be flushed
  12  *
  13  * FIXME:      - ignores parameters
  14  *             - doesn't know about second level caches
  15  *             - only knows how to handle the R4600
  16  */
  17 
  18 #include <asm/mipsconfig.h>
  19 #include <asm/regdef.h>
  20 #include <asm/segment.h>
  21 
  22 #define PAGE_SIZE       0x1000
  23 
  24 #define CACHELINES      512             /* number of cachelines    */
  25 
  26                 .set    noreorder
  27                 .globl  _sys_cacheflush
  28                 .text
  29 _sys_cacheflush:
  30                 /*
  31                  * Writeback/invalidate the data cache
  32                  */
  33                 li      t0,KSEG0
  34                 li      t1,CACHELINES
  35 1:              cache   1,0(t0)
  36                 cache   1,32(t0)
  37                 cache   1,64(t0)
  38                 cache   1,96(t0)
  39                 cache   1,128(t0)
  40                 cache   1,160(t0)
  41                 cache   1,192(t0)
  42                 cache   1,224(t0)
  43                 cache   1,256(t0)
  44                 cache   1,288(t0)
  45                 cache   1,320(t0)
  46                 cache   1,352(t0)
  47                 cache   1,384(t0)
  48                 cache   1,416(t0)
  49                 cache   1,448(t0)
  50                 cache   1,480(t0)
  51                 subu    t1,t1,1
  52                 bnez    t1,1b
  53                 addiu   t0,t0,512                       # delay slot
  54 
  55                 /*
  56                  * Flush the instruction cache
  57                  */
  58                 lui     t0,0x8000
  59                 li      t1,CACHELINES
  60 1:              cache   0,0(t0) 
  61                 cache   0,32(t0)
  62                 cache   0,64(t0)
  63                 cache   0,96(t0)
  64                 cache   0,128(t0)
  65                 cache   0,160(t0)
  66                 cache   0,192(t0)
  67                 cache   0,224(t0)
  68                 cache   0,256(t0)
  69                 cache   0,288(t0)
  70                 cache   0,320(t0)
  71                 cache   0,352(t0)
  72                 cache   0,384(t0)
  73                 cache   0,416(t0)
  74                 cache   0,448(t0)
  75                 cache   0,480(t0)
  76                 subu    t1,t1,1
  77                 bnez    t1,1b
  78                 addiu   t0,t0,512                       # delay slot
  79 
  80                 j       ra
  81                 nop
/* */
root/arch/mips/kernel/cache.S
