This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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129 static char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #ifdef MODULE
132 #include <linux/module.h>
133 #include <linux/version.h>
134 #endif
135
136 #include <stdarg.h>
137 #include <linux/kernel.h>
138 #include <linux/sched.h>
139 #include <linux/string.h>
140 #include <linux/ptrace.h>
141 #include <linux/errno.h>
142 #include <linux/ioport.h>
143 #include <linux/malloc.h>
144 #include <linux/interrupt.h>
145 #include <asm/bitops.h>
146 #include <asm/io.h>
147 #include <asm/dma.h>
148 #include <asm/segment.h>
149
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/skbuff.h>
153
154 #include <linux/time.h>
155 #include <linux/types.h>
156 #include <linux/unistd.h>
157
158 #include "ewrk3.h"
159
160 #ifdef EWRK3_DEBUG
161 static int ewrk3_debug = EWRK3_DEBUG;
162 #else
163 static int ewrk3_debug = 1;
164 #endif
165
166 #ifndef PROBE_LENGTH
167 #define PROBE_LENGTH 32
168 #endif
169
170 #ifndef PROBE_SEQUENCE
171 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
172 #endif
173
174 #ifndef EWRK3_SIGNATURE
175 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
176 #define EWRK3_NAME_LENGTH 8
177 #endif
178
179 #ifndef EWRK3_RAM_BASE_ADDRESSES
180 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
181 #endif
182
183
184
185
186
187
188
189
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193
194
195
196
197 #define EWRK3_IO_BASE 0x100
198 #define EWRK3_IOP_INC 0x20
199 #define EWRK3_TOTAL_SIZE 0x20
200 #define EWRK3_IO_SEARCH 0x007dff7f
201 static long mem_chkd = EWRK3_IO_SEARCH;
202
203
204 #ifndef MAX_NUM_EWRK3S
205 #define MAX_NUM_EWRK3S 21
206 #endif
207
208 #ifndef EWRK3_EISA_IO_PORTS
209 #define EWRK3_EISA_IO_PORTS 0x0c00
210 #endif
211
212 #ifndef MAX_EISA_SLOTS
213 #define MAX_EISA_SLOTS 8
214 #define EISA_SLOT_INC 0x1000
215 #endif
216
217 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
218 #define CRC_POLYNOMIAL_LE 0xedb88320UL
219
220
221
222
223 #define IO_ONLY 0x00
224 #define SHMEM_2K 0x800
225 #define SHMEM_32K 0x8000
226 #define SHMEM_64K 0x10000
227
228
229
230
231 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
232
233 #define ENABLE_IRQs \
234 icr |= irq_mask;\
235 outb(icr, EWRK3_ICR)
236
237 #define DISABLE_IRQs \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~irq_mask;\
240 outb(icr, EWRK3_ICR)
241
242
243
244
245 #define START_EWRK3 \
246 csr = inb(EWRK3_CSR);\
247 csr &= ~(TXD|RXD);\
248 outb(csr, EWRK3_CSR)
249
250 #define STOP_EWRK3 \
251 csr = (TXD|RXD);\
252 outb(csr, EWRK3_CSR)
253
254
255
256
257 #define EWRK3_PKT_STAT_SZ 16
258 #define EWRK3_PKT_BIN_SZ 128
259
260
261 struct ewrk3_private {
262 long shmem_base;
263 long shmem_length;
264 struct enet_statistics stats;
265 struct {
266 unsigned long bins[EWRK3_PKT_STAT_SZ];
267 unsigned long unicast;
268 unsigned long multicast;
269 unsigned long broadcast;
270 unsigned long excessive_collisions;
271 unsigned long tx_underruns;
272 unsigned long excessive_underruns;
273 } pktStats;
274 short mPage;
275 unsigned char lemac;
276 unsigned char hard_strapped;
277 unsigned char lock;
278 unsigned char txc;
279 };
280
281
282
283
284 #define FORCE_2K_MODE \
285 shmem_length = SHMEM_2K;\
286 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
287
288
289
290
291 static int ewrk3_open(struct device *dev);
292 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
293 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
294 static int ewrk3_close(struct device *dev);
295 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
296 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
297 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
298
299
300
301
302 static int ewrk3_hw_init(struct device *dev, short iobase);
303 static void ewrk3_init(struct device *dev);
304 static int ewrk3_rx(struct device *dev);
305 static int ewrk3_tx(struct device *dev);
306
307 static void EthwrkSignature(char * name, char *eeprom_image);
308 static int DevicePresent(short iobase);
309 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
310
311 static int Read_EEPROM(short iobase, unsigned char eaddr);
312 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
313 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
314
315 #ifndef MODULE
316 static struct device *isa_probe(struct device *dev);
317 static struct device *eisa_probe(struct device *dev);
318 static struct device *alloc_device(struct device *dev, int iobase);
319
320 static int num_ewrk3s = 0, num_eth = 0;
321 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
322
323 #else
324 int init_module(void);
325 void cleanup_module(void);
326
327 #endif
328
329 static int autoprobed = 0;
330
331
332
333
334 #define INIT_EWRK3 {\
335 int i;\
336 outb(EEPROM_INIT, EWRK3_IOPR);\
337 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
338 }
339
340
341
342
343 int ewrk3_probe(struct device *dev)
344 {
345 int base_addr = dev->base_addr;
346 int status = -ENODEV;
347 #ifndef MODULE
348 struct device *eth0;
349 #endif
350
351 if (base_addr > 0x0ff) {
352 if (!autoprobed) {
353 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
354 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
355 if (DevicePresent(base_addr) == 0) {
356
357 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
358 status = ewrk3_hw_init(dev, base_addr);
359 } else {
360 printk("ewrk3_probe(): No device found\n");
361 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
362 }
363 }
364 } else {
365 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
366 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
367 }
368 } else {
369 status = ewrk3_hw_init(dev, base_addr);
370 }
371 } else if (base_addr > 0) {
372 status = -ENXIO;
373
374 #ifdef MODULE
375 } else {
376 printk("Autoprobing is not supported when loading a module based driver.\n");
377 status = -EIO;
378 #else
379 } else if (!autoprobed) {
380
381 eth0=isa_probe(dev);
382 eth0=eisa_probe(eth0);
383 if (dev->priv) status=0;
384 autoprobed = 1;
385 } else {
386 status = -ENXIO;
387 #endif
388
389 }
390
391 if (status) dev->base_addr = base_addr;
392
393 return status;
394 }
395
396 static int
397 ewrk3_hw_init(struct device *dev, short iobase)
398 {
399 struct ewrk3_private *lp;
400 int i, status=0;
401 unsigned long mem_start, shmem_length;
402 char name[EWRK3_NAME_LENGTH + 1];
403 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
404 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
405
406
407
408
409
410 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
411 INIT_EWRK3;
412
413 nicsr = inb(EWRK3_CSR);
414
415
416
417
418 DISABLE_IRQs;
419
420 if (nicsr == TXD|RXD) {
421
422
423
424
425 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
426 union {
427 short val;
428 char c[2];
429 } tmp;
430
431 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
432 eeprom_image[i] = tmp.c[0];
433 eeprom_image[i+1] = tmp.c[1];
434
435 chksum += eeprom_image[i] + eeprom_image[i+1];
436 }
437
438 if (chksum != 0) {
439 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
440 status = -ENXIO;
441 } else {
442
443
444
445 EthwrkSignature(name, eeprom_image);
446
447 if (*name != '\0') {
448 dev->base_addr = iobase;
449
450 if (iobase > 0x400) {
451 outb(eisa_cr, EISA_CR);
452 }
453
454 lemac = eeprom_image[EEPROM_CHIPVER];
455 cmr = inb(EWRK3_CMR);
456
457 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
458 ((lemac == LeMAC2) && !(cmr & HS))) {
459 printk("%s: %s at %#3x", dev->name, name, iobase);
460 hard_strapped = 1;
461 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
462
463 printk("%s: %s at %#3x (EISA slot %d)",
464 dev->name, name, iobase, ((iobase>>12)&0x0f));
465 } else {
466 printk("%s: %s at %#3x", dev->name, name, iobase);
467 }
468
469 if (!status) {
470 printk(", h/w address ");
471 if (lemac == LeMAC2) {
472 for (i = 0;i < ETH_ALEN - 1;i++) {
473 printk("%2.2x:", dev->dev_addr[i] =
474 eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 }
477 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
478 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
479 } else {
480 DevicePresent(iobase);
481 for (i = 0; i < ETH_ALEN - 1; i++) {
482 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
486 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
487 }
488
489 if (aprom_crc(dev, eeprom_image, lemac)) {
490 printk(" which has an EEPROM CRC error.\n");
491 status = -ENXIO;
492 } else {
493 if (lemac == LeMAC2) {
494 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
495 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
496 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
497 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
498 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
499 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
500 }
501 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
502 outb(cmr, EWRK3_CMR);
503
504 cr = inb(EWRK3_CR);
505 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
506 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
507 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
508 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
509 outb(cr, EWRK3_CR);
510
511
512
513
514
515 mem_start = inb(EWRK3_MBR);
516 shmem_length = 0;
517 if (mem_start != 0) {
518 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
519 mem_start *= SHMEM_64K;
520 shmem_length = SHMEM_64K;
521 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
522 mem_start *= SHMEM_32K;
523 shmem_length = SHMEM_32K;
524 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
525 mem_start = mem_start * SHMEM_2K + 0x80000;
526 shmem_length = SHMEM_2K;
527 } else {
528 status = -ENXIO;
529 }
530 }
531
532
533
534
535
536
537
538 if (!status) {
539 if (hard_strapped) {
540 printk(" is hard strapped.\n");
541 } else if (mem_start) {
542 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
543 printk(" at 0x%.5lx", mem_start);
544 } else {
545 printk(" is in I/O only mode");
546 }
547
548
549 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
550 GFP_KERNEL);
551 lp = (struct ewrk3_private *)dev->priv;
552 memset(dev->priv, 0, sizeof(struct ewrk3_private));
553 lp->shmem_base = mem_start;
554 lp->shmem_length = shmem_length;
555 lp->lemac = lemac;
556 lp->hard_strapped = hard_strapped;
557
558 lp->mPage = 64;
559 if (cmr & DRAM) lp->mPage <<= 1 ;
560
561 if (!hard_strapped) {
562
563
564
565 icr |= IE;
566 outb(icr, EWRK3_ICR);
567
568
569 dev->dma = 0;
570
571
572
573 if (dev->irq < 2) {
574 #ifndef MODULE
575 unsigned char irqnum;
576
577 autoirq_setup(0);
578
579
580
581
582 icr |=TNEM;
583 outb(1,EWRK3_TDQ);
584 outb(icr, EWRK3_ICR);
585
586 irqnum = irq[((icr & IRQ_SEL) >> 4)];
587
588 dev->irq = autoirq_report(1);
589 if ((dev->irq) && (irqnum == dev->irq)) {
590 printk(" and uses IRQ%d.\n", dev->irq);
591 } else {
592 if (!dev->irq) {
593 printk(" and failed to detect IRQ line.\n");
594 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
595 printk(" and an illegal IRQ line detected.\n");
596 } else {
597 printk(", but incorrect IRQ line detected.\n");
598 }
599 status = -ENXIO;
600 }
601
602 DISABLE_IRQs;
603
604 #endif
605 } else {
606 printk(" and requires IRQ%d.\n", dev->irq);
607 }
608 }
609 } else {
610 status = -ENXIO;
611 }
612 }
613 }
614 } else {
615 status = -ENXIO;
616 }
617 }
618
619 if (!status) {
620 if (ewrk3_debug > 0) {
621 printk(version);
622 }
623
624
625 dev->open = &ewrk3_open;
626 dev->hard_start_xmit = &ewrk3_queue_pkt;
627 dev->stop = &ewrk3_close;
628 dev->get_stats = &ewrk3_get_stats;
629 #ifdef HAVE_MULTICAST
630 dev->set_multicast_list = &set_multicast_list;
631 #endif
632 dev->do_ioctl = &ewrk3_ioctl;
633
634 dev->mem_start = 0;
635
636
637 ether_setup(dev);
638 }
639 } else {
640 status = -ENXIO;
641 }
642
643 return status;
644 }
645
646
647 static int
648 ewrk3_open(struct device *dev)
649 {
650 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
651 int i, iobase = dev->base_addr;
652 int status = 0;
653 unsigned char icr, csr;
654
655
656
657
658 STOP_EWRK3;
659
660 if (!lp->hard_strapped) {
661 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
662 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
663 status = -EAGAIN;
664 } else {
665
666 irq2dev_map[dev->irq] = dev;
667
668
669
670
671 ewrk3_init(dev);
672
673 if (ewrk3_debug > 1){
674 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
675 printk("\tphysical address: ");
676 for (i=0;i<6;i++){
677 printk("%2.2x:",(short)dev->dev_addr[i]);
678 }
679 printk("\n");
680 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
681 if (lp->shmem_length == 0) {
682 printk("\tno shared memory, I/O only mode\n");
683 } else {
684 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
685 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
686 }
687 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
688 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
689 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
690 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
691 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
692 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
693 }
694
695 dev->tbusy = 0;
696 dev->start = 1;
697 dev->interrupt = UNMASK_INTERRUPTS;
698
699
700
701
702 icr = inb(EWRK3_ICR);
703 ENABLE_IRQs;
704
705 }
706 } else {
707 dev->start = 0;
708 dev->tbusy = 1;
709 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
710 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
711 }
712
713 #ifdef MODULE
714 MOD_INC_USE_COUNT;
715 #endif
716
717
718 return status;
719 }
720
721
722
723
724 static void
725 ewrk3_init(struct device *dev)
726 {
727 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
728 char csr, page;
729 short iobase = dev->base_addr;
730
731
732
733
734 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
735
736
737
738
739 while (inb(EWRK3_TQ));
740 while (inb(EWRK3_TDQ));
741 while (inb(EWRK3_RQ));
742 while (inb(EWRK3_FMQ));
743
744
745
746
747 for (page=1;page<lp->mPage;page++) {
748 outb(page, EWRK3_FMQ);
749 }
750
751 lp->lock = 0;
752
753 START_EWRK3;
754 }
755
756
757
758
759 static int
760 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
761 {
762 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
763 int iobase = dev->base_addr;
764 int status = 0;
765 unsigned char icr, csr;
766
767
768 if (dev->tbusy || lp->lock) {
769 int tickssofar = jiffies - dev->trans_start;
770 if (tickssofar < 10) {
771 status = -1;
772 } else if (!lp->hard_strapped) {
773 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
774 dev->name, inb(EWRK3_CSR));
775
776
777
778
779 DISABLE_IRQs;
780
781
782
783
784 STOP_EWRK3;
785
786 ewrk3_init(dev);
787
788
789
790
791 ENABLE_IRQs;
792
793 dev->tbusy=0;
794 dev->trans_start = jiffies;
795 }
796 } else if (skb == NULL) {
797 dev_tint(dev);
798 } else if (skb->len > 0) {
799
800
801
802
803
804 if (set_bit(0, (void*)&dev->tbusy) != 0)
805 printk("%s: Transmitter access conflict.\n", dev->name);
806
807 DISABLE_IRQs;
808
809
810
811
812 if (inb(EWRK3_FMQC) > 0) {
813 unsigned char *buf;
814 unsigned char page;
815
816 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
817 buf = NULL;
818
819
820
821
822 while (set_bit(0, (void *)&lp->lock) != 0);
823 if (lp->shmem_length == IO_ONLY) {
824 outb(page, EWRK3_IOPR);
825 } else if (lp->shmem_length == SHMEM_2K) {
826 buf = (char *) lp->shmem_base;
827 outb(page, EWRK3_MPR);
828 } else if (lp->shmem_length == SHMEM_32K) {
829 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
830 outb((page >> 4), EWRK3_MPR);
831 } else if (lp->shmem_length == SHMEM_64K) {
832 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
833 outb((page >> 5), EWRK3_MPR);
834 } else {
835 status = -1;
836 printk("%s: Oops - your private data area is hosed!\n",dev->name);
837 }
838
839 if (!status) {
840
841
842
843
844
845
846 if (lp->shmem_length == IO_ONLY) {
847 int i;
848 unsigned char *p = skb->data;
849
850 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
851 outb((char)(skb->len & 0xff), EWRK3_DATA);
852 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
853 outb((char)0x04, EWRK3_DATA);
854 for (i=0; i<skb->len; i++) {
855 outb(*p++, EWRK3_DATA);
856 }
857 outb(page, EWRK3_TQ);
858 } else {
859 *buf++ = (char)(QMODE | PAD | IFC);
860 *buf++ = (char)(skb->len & 0xff);
861 if (lp->txc) {
862 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
863 *buf++ = 0x04;
864 *(buf + skb->len) = 0x00;
865 memcpy(buf, skb->data, PRELOAD);
866 outb(page, EWRK3_TQ);
867 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
868 *(buf + skb->len) = 0xff;
869 } else {
870 *buf++ = (char)((skb->len >> 8) & 0xff);
871 *buf++ = 0x04;
872 memcpy(buf, skb->data, skb->len);
873 outb(page, EWRK3_TQ);
874 }
875 }
876
877 dev->trans_start = jiffies;
878
879 dev_kfree_skb (skb, FREE_WRITE);
880
881 } else {
882 outb(page, EWRK3_FMQ);
883 }
884 lp->lock = 0;
885 } else {
886 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
887 (unsigned char) page);
888 }
889 } else {
890 printk("ewrk3_queue_pkt(): No free resources...\n");
891 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
892 }
893
894
895 if (inb(EWRK3_FMQC) > 0) {
896 dev->tbusy = 0;
897 }
898
899 ENABLE_IRQs;
900 }
901
902 return status;
903 }
904
905
906
907
908 static void
909 ewrk3_interrupt(int irq, struct pt_regs * regs)
910 {
911 struct device *dev = (struct device *)(irq2dev_map[irq]);
912 struct ewrk3_private *lp;
913 int iobase;
914 unsigned char icr, cr, csr;
915
916 if (dev == NULL) {
917 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
918 } else {
919 lp = (struct ewrk3_private *)dev->priv;
920 iobase = dev->base_addr;
921
922 if (dev->interrupt)
923 printk("%s: Re-entering the interrupt handler.\n", dev->name);
924
925 dev->interrupt = MASK_INTERRUPTS;
926
927
928 csr = inb(EWRK3_CSR);
929
930
931
932
933 DISABLE_IRQs;
934
935 cr = inb(EWRK3_CR);
936 cr |= LED;
937 outb(cr, EWRK3_CR);
938
939 if (csr & RNE)
940 ewrk3_rx(dev);
941
942 if (csr & TNE)
943 ewrk3_tx(dev);
944
945
946
947
948
949
950
951 if (inb(EWRK3_FMQC)) {
952 irq_mask |= TXDM|RXDM;
953 csr &= ~(TXD|RXD);
954 outb(csr, EWRK3_CSR);
955 dev->tbusy = 0;
956 mark_bh(NET_BH);
957 } else {
958 irq_mask &= ~(TXDM|RXDM);
959 }
960
961
962 cr &= ~LED;
963 outb(cr, EWRK3_CR);
964
965 dev->interrupt = UNMASK_INTERRUPTS;
966
967 ENABLE_IRQs;
968 }
969
970 return;
971 }
972
973 static int
974 ewrk3_rx(struct device *dev)
975 {
976 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
977 int i, iobase = dev->base_addr;
978 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
979 int status = 0;
980
981 while (inb(EWRK3_RQC) && !status) {
982 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
983 buf = NULL;
984
985
986
987
988
989 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
990 if (lp->shmem_length == IO_ONLY) {
991 tmpPage = inb(EWRK3_IOPR);
992 } else {
993 tmpPage = inb(EWRK3_MPR);
994 }
995 }
996
997
998
999
1000 if (lp->shmem_length == IO_ONLY) {
1001 outb(page, EWRK3_IOPR);
1002 } else if (lp->shmem_length == SHMEM_2K) {
1003 buf = (char *) lp->shmem_base;
1004 outb(page, EWRK3_MPR);
1005 } else if (lp->shmem_length == SHMEM_32K) {
1006 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1007 outb((page >> 4), EWRK3_MPR);
1008 } else if (lp->shmem_length == SHMEM_64K) {
1009 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1010 outb((page >> 5), EWRK3_MPR);
1011 } else {
1012 status = -1;
1013 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1014 }
1015
1016 if (!status) {
1017 char rx_status;
1018 int pkt_len;
1019
1020 if (lp->shmem_length == IO_ONLY) {
1021 rx_status = inb(EWRK3_DATA);
1022 pkt_len = inb(EWRK3_DATA);
1023 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1024 } else {
1025 rx_status = (char)(*buf++);
1026 pkt_len = (short)(*buf+((*(buf+1))<<8));
1027 buf+=3;
1028 }
1029
1030 if (!(rx_status & ROK)) {
1031 lp->stats.rx_errors++;
1032 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1033 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1034 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1035 } else {
1036 struct sk_buff *skb;
1037
1038 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1039 skb->len = pkt_len;
1040 skb->dev = dev;
1041
1042 if (lp->shmem_length == IO_ONLY) {
1043 unsigned char *p = skb->data;
1044
1045 *p = inb(EWRK3_DATA);
1046 for (i=0; i<skb->len; i++) {
1047 *p++ = inb(EWRK3_DATA);
1048 }
1049 } else {
1050 memcpy(skb->data, buf, pkt_len);
1051 }
1052
1053
1054
1055
1056
1057 netif_rx(skb);
1058
1059
1060
1061
1062 lp->stats.rx_packets++;
1063 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1064 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1065 lp->pktStats.bins[i]++;
1066 i = EWRK3_PKT_STAT_SZ;
1067 }
1068 }
1069 buf = skb->data;
1070 if (buf[0] & 0x01) {
1071 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1072 lp->pktStats.broadcast++;
1073 } else {
1074 lp->pktStats.multicast++;
1075 }
1076 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1077 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1078 lp->pktStats.unicast++;
1079 }
1080
1081 lp->pktStats.bins[0]++;
1082 if (lp->pktStats.bins[0] == 0) {
1083 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1084 }
1085 } else {
1086 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1087 lp->stats.rx_dropped++;
1088 break;
1089 }
1090 }
1091 }
1092
1093
1094
1095 outb(page, EWRK3_FMQ);
1096
1097 if (tmpLock) {
1098 if (lp->shmem_length == IO_ONLY) {
1099 outb(tmpPage, EWRK3_IOPR);
1100 } else {
1101 outb(tmpPage, EWRK3_MPR);
1102 }
1103 }
1104 lp->lock = 0;
1105 } else {
1106 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1107 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1108 }
1109 }
1110 return status;
1111 }
1112
1113
1114
1115
1116 static int
1117 ewrk3_tx(struct device *dev)
1118 {
1119 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1120 int iobase = dev->base_addr;
1121 unsigned char tx_status;
1122
1123 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1124 if (tx_status & VSTS) {
1125 if (tx_status & MAC_TXE) {
1126 lp->stats.tx_errors++;
1127 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1128 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1129 if (tx_status & MAC_CTU) {
1130 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1131 lp->pktStats.tx_underruns++;
1132 } else {
1133 lp->pktStats.excessive_underruns++;
1134 }
1135 } else if (tx_status & MAC_COLL) {
1136 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1137 lp->stats.collisions++;
1138 } else {
1139 lp->pktStats.excessive_collisions++;
1140 }
1141 }
1142 } else {
1143 lp->stats.tx_packets++;
1144 }
1145 }
1146 }
1147
1148 return 0;
1149 }
1150
1151 static int
1152 ewrk3_close(struct device *dev)
1153 {
1154 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1155 int iobase = dev->base_addr;
1156 unsigned char icr, csr;
1157
1158 dev->start = 0;
1159 dev->tbusy = 1;
1160
1161 if (ewrk3_debug > 1) {
1162 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1163 dev->name, inb(EWRK3_CSR));
1164 }
1165
1166
1167
1168
1169 DISABLE_IRQs;
1170
1171 STOP_EWRK3;
1172
1173
1174
1175
1176
1177
1178
1179 while (inb(EWRK3_TQ));
1180 while (inb(EWRK3_TDQ));
1181 while (inb(EWRK3_RQ));
1182
1183 if (!lp->hard_strapped) {
1184 free_irq(dev->irq);
1185
1186 irq2dev_map[dev->irq] = 0;
1187 }
1188
1189 #ifdef MODULE
1190 MOD_DEC_USE_COUNT;
1191 #endif
1192
1193 return 0;
1194 }
1195
1196 static struct enet_statistics *
1197 ewrk3_get_stats(struct device *dev)
1198 {
1199 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1200
1201
1202
1203 return &lp->stats;
1204 }
1205
1206
1207
1208
1209
1210
1211
1212
1213 static void
1214 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1215 {
1216 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1217 int iobase = dev->base_addr;
1218 char *multicast_table;
1219 unsigned char csr;
1220
1221 csr = inb(EWRK3_CSR);
1222
1223 if (lp->shmem_length == IO_ONLY) {
1224 multicast_table = (char *) PAGE0_HTE;
1225 } else {
1226 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1227 }
1228
1229 if (num_addrs >= 0) {
1230 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1231 csr &= ~PME;
1232 csr |= MCE;
1233 outb(csr, EWRK3_CSR);
1234 } else {
1235 csr |= PME;
1236 csr &= ~MCE;
1237 outb(csr, EWRK3_CSR);
1238 }
1239 }
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1250 {
1251 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1252 int i, iobase = dev->base_addr;
1253 char j, bit, byte;
1254 short *p = (short *) multicast_table;
1255 u_short hashcode;
1256 u_long crc, poly = CRC_POLYNOMIAL_LE;
1257
1258 while (set_bit(0, (void *)&lp->lock) != 0);
1259
1260 if (lp->shmem_length == IO_ONLY) {
1261 outb(0, EWRK3_IOPR);
1262 outw((short)((long)multicast_table), EWRK3_PIR1);
1263 } else {
1264 outb(0, EWRK3_MPR);
1265 }
1266
1267 if (num_addrs == HASH_TABLE_LEN) {
1268 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1269 if (lp->shmem_length == IO_ONLY) {
1270 outb(0xff, EWRK3_DATA);
1271 } else {
1272 *p++ = 0xffff;
1273 i++;
1274 }
1275 }
1276 } else {
1277
1278 if (lp->shmem_length == IO_ONLY) {
1279 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1280 outb(0x00, EWRK3_DATA);
1281 }
1282 outb(0x80, EWRK3_DATA); i++;
1283 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1284 outb(0x00, EWRK3_DATA);
1285 }
1286 } else {
1287 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1288 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1289 }
1290
1291
1292 for (i=0;i<num_addrs;i++) {
1293 if ((*addrs & 0x01) == 1) {
1294 crc = 0xffffffff;
1295 for (byte=0;byte<ETH_ALEN;byte++) {
1296
1297 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1298 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1299 }
1300 }
1301 hashcode = crc & ((1 << 9) - 1);
1302
1303 byte = hashcode >> 3;
1304 bit = 1 << (hashcode & 0x07);
1305
1306 if (lp->shmem_length == IO_ONLY) {
1307 unsigned char tmp;
1308
1309 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1310 tmp = inb(EWRK3_DATA);
1311 tmp |= bit;
1312 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1313 outb(tmp, EWRK3_DATA);
1314 } else {
1315 multicast_table[byte] |= bit;
1316 }
1317 } else {
1318 addrs += ETH_ALEN;
1319 }
1320 }
1321 }
1322
1323 lp->lock = 0;
1324
1325 return;
1326 }
1327
1328 #ifndef MODULE
1329
1330
1331
1332 static struct device *isa_probe(struct device *dev)
1333 {
1334 int i, iobase, status;
1335 unsigned long int tmp = mem_chkd;
1336
1337 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1338 i < 24;
1339 iobase += EWRK3_IOP_INC, i++) {
1340 if (tmp & 0x01) {
1341
1342 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1343 if (DevicePresent(iobase) == 0) {
1344
1345
1346
1347
1348 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1349 if (num_ewrk3s > 0) {
1350 dev = alloc_device(dev, iobase);
1351 } else {
1352 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1353 num_ewrk3s++;
1354 }
1355 }
1356 num_eth++;
1357 } else {
1358 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1359 }
1360 } else {
1361 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1362 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1363 }
1364 }
1365 tmp >>= 1;
1366 }
1367
1368 return dev;
1369 }
1370
1371
1372
1373
1374
1375 static struct device *eisa_probe(struct device *dev)
1376 {
1377 int i, iobase = EWRK3_EISA_IO_PORTS;
1378 int status;
1379
1380 iobase+=EISA_SLOT_INC;
1381 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1382
1383
1384 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1385 if (DevicePresent(iobase) == 0) {
1386
1387
1388
1389
1390 mem_chkd |= (0x01 << (i + 24));
1391 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1392 if (num_ewrk3s > 0) {
1393 dev = alloc_device(dev, iobase);
1394 } else {
1395 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1396 num_ewrk3s++;
1397 }
1398 }
1399 num_eth++;
1400 }
1401 }
1402 }
1403 return dev;
1404 }
1405
1406
1407
1408
1409
1410 static struct device *alloc_device(struct device *dev, int iobase)
1411 {
1412
1413
1414
1415 while (dev->next != NULL) {
1416 if (dev->next->base_addr == 0xffe0) break;
1417 dev = dev->next;
1418 num_eth++;
1419 }
1420
1421
1422
1423
1424
1425 if (dev->next == NULL) {
1426 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1427 GFP_KERNEL);
1428 if (dev->next == NULL) {
1429 printk("eth%d: Device not initialised, insufficient memory\n",
1430 num_eth);
1431 }
1432 }
1433
1434
1435
1436
1437
1438
1439 if ((dev->next != NULL) &&
1440 (num_eth > 0) && (num_eth < 9999)) {
1441 dev = dev->next;
1442 dev->name = (char *)(dev + sizeof(struct device));
1443 sprintf(dev->name,"eth%d", num_eth);
1444 dev->base_addr = iobase;
1445 dev->next = NULL;
1446 dev->init = &ewrk3_probe;
1447 num_ewrk3s++;
1448 }
1449
1450 return dev;
1451 }
1452 #endif
1453
1454
1455
1456
1457 static int Read_EEPROM(short iobase, unsigned char eaddr)
1458 {
1459 int i;
1460
1461 outb((eaddr & 0x3f), EWRK3_PIR1);
1462 outb(EEPROM_RD, EWRK3_IOPR);
1463 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1464
1465 return inw(EWRK3_EPROM1);
1466 }
1467
1468
1469
1470
1471 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1472 {
1473 int i;
1474
1475 outb(EEPROM_WR_EN, EWRK3_IOPR);
1476 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1477 outw(data, EWRK3_EPROM1);
1478 outb((eaddr & 0x3f), EWRK3_PIR1);
1479 outb(EEPROM_WR, EWRK3_IOPR);
1480 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1481 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1482 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1483
1484 return 0;
1485 }
1486
1487
1488
1489
1490 static void EthwrkSignature(char *name, char *eeprom_image)
1491 {
1492 unsigned long i,j,k;
1493 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1494
1495 strcpy(name, "");
1496 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1497 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1498 if (signatures[i][k] == eeprom_image[j]) {
1499 k++;
1500 } else {
1501 k=0;
1502 }
1503 }
1504 if (k == strlen(signatures[i])) {
1505 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1506 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1507 name[EWRK3_NAME_LENGTH] = '\0';
1508 }
1509 }
1510 }
1511
1512 return;
1513 }
1514
1515
1516
1517
1518
1519
1520 static int DevicePresent(short iobase)
1521 {
1522 static short fp=1,sigLength=0;
1523 static char devSig[] = PROBE_SEQUENCE;
1524 char data;
1525 int i, j, status = 0;
1526 static char asc2hex(char value);
1527
1528
1529
1530
1531 if (fp) {
1532 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1533 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1534 devSig[i]<<=4;
1535 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1536 devSig[j]=devSig[i]+devSig[i+1];
1537 } else {
1538 status= -1;
1539 }
1540 } else {
1541 status= -1;
1542 }
1543 }
1544 sigLength=j;
1545 fp = 0;
1546 }
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556 if (!status) {
1557 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1558 data = inb(EWRK3_APROM);
1559 if (devSig[j] == data) {
1560 j++;
1561 } else {
1562 j=0;
1563 }
1564 }
1565
1566 if (j!=sigLength) {
1567 status = -ENODEV;
1568 }
1569 }
1570
1571 return status;
1572 }
1573
1574 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1575 {
1576 long k;
1577 unsigned short j,chksum;
1578 unsigned char crc, lfsr, sd, status = 0;
1579 int iobase = dev->base_addr;
1580
1581 if (chipType == LeMAC2) {
1582 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1583 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1584 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1585 crc = (crc >> 1) + lfsr;
1586 }
1587 }
1588 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1589 } else {
1590 for (k=0,j=0;j<3;j++) {
1591 k <<= 1 ;
1592 if (k > 0xffff) k-=0xffff;
1593 k += inw(EWRK3_PAR0 + (j<<1));
1594 if (k > 0xffff) k-=0xffff;
1595 }
1596 if (k == 0xffff) k=0;
1597 chksum = inb(EWRK3_APROM);
1598 chksum |= (inb(EWRK3_APROM)<<8);
1599 if (k != chksum) status = -1;
1600 }
1601
1602 return status;
1603 }
1604
1605
1606
1607
1608
1609 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1610 {
1611 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1612 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1613 int i, j, iobase = dev->base_addr, status = 0;
1614 unsigned char csr;
1615 union {
1616 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1617 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1618 } tmp;
1619
1620 switch(ioc->cmd) {
1621 case EWRK3_GET_HWADDR:
1622 for (i=0; i<ETH_ALEN; i++) {
1623 tmp.addr[i] = dev->dev_addr[i];
1624 }
1625 ioc->len = ETH_ALEN;
1626 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1627
1628 break;
1629 case EWRK3_SET_HWADDR:
1630 if (suser()) {
1631 csr = inb(EWRK3_CSR);
1632 csr |= (TXD|RXD);
1633 outb(csr, EWRK3_CSR);
1634
1635 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1636 for (i=0; i<ETH_ALEN; i++) {
1637 dev->dev_addr[i] = tmp.addr[i];
1638 outb(tmp.addr[i], EWRK3_PAR0 + i);
1639 }
1640
1641 csr &= ~(TXD|RXD);
1642 outb(csr, EWRK3_CSR);
1643 } else {
1644 status = -EPERM;
1645 }
1646
1647 break;
1648 case EWRK3_SET_PROM:
1649 if (suser()) {
1650 csr = inb(EWRK3_CSR);
1651 csr |= PME;
1652 csr &= ~MCE;
1653 outb(csr, EWRK3_CSR);
1654 } else {
1655 status = -EPERM;
1656 }
1657
1658 break;
1659 case EWRK3_CLR_PROM:
1660 if (suser()) {
1661 csr = inb(EWRK3_CSR);
1662 csr &= ~PME;
1663 outb(csr, EWRK3_CSR);
1664 } else {
1665 status = -EPERM;
1666 }
1667
1668 break;
1669 case EWRK3_SAY_BOO:
1670 printk("%s: Boo!\n", dev->name);
1671
1672 break;
1673 case EWRK3_GET_MCA:
1674 while (set_bit(0, (void *)&lp->lock) != 0);
1675 if (lp->shmem_length == IO_ONLY) {
1676 outb(0, EWRK3_IOPR);
1677 outw(PAGE0_HTE, EWRK3_PIR1);
1678 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1679 tmp.addr[i] = inb(EWRK3_DATA);
1680 }
1681 } else {
1682 outb(0, EWRK3_MPR);
1683 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1684 }
1685 ioc->len = (HASH_TABLE_LEN >> 3);
1686 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1687 lp->lock = 0;
1688
1689 break;
1690 case EWRK3_SET_MCA:
1691 if (suser()) {
1692 if (ioc->len != HASH_TABLE_LEN) {
1693 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1694 }
1695 set_multicast_list(dev, ioc->len, tmp.addr);
1696 } else {
1697 status = -EPERM;
1698 }
1699
1700 break;
1701 case EWRK3_CLR_MCA:
1702 if (suser()) {
1703 set_multicast_list(dev, 0, NULL);
1704 } else {
1705 status = -EPERM;
1706 }
1707
1708 break;
1709 case EWRK3_MCA_EN:
1710 if (suser()) {
1711 csr = inb(EWRK3_CSR);
1712 csr |= MCE;
1713 csr &= ~PME;
1714 outb(csr, EWRK3_CSR);
1715 } else {
1716 status = -EPERM;
1717 }
1718
1719 break;
1720 case EWRK3_GET_STATS:
1721 cli();
1722 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1723 ioc->len = EWRK3_PKT_STAT_SZ;
1724 sti();
1725
1726 break;
1727 case EWRK3_CLR_STATS:
1728 if (suser()) {
1729 cli();
1730 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1731 sti();
1732 } else {
1733 status = -EPERM;
1734 }
1735
1736 break;
1737 case EWRK3_GET_CSR:
1738 tmp.addr[0] = inb(EWRK3_CSR);
1739 memcpy_tofs(ioc->data, tmp.addr, 1);
1740
1741 break;
1742 case EWRK3_SET_CSR:
1743 if (suser()) {
1744 memcpy_fromfs(tmp.addr, ioc->data, 1);
1745 outb(tmp.addr[0], EWRK3_CSR);
1746 } else {
1747 status = -EPERM;
1748 }
1749
1750 break;
1751 case EWRK3_GET_EEPROM:
1752 if (suser()) {
1753 for (i=0; i<(EEPROM_MAX>>1); i++) {
1754 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1755 }
1756 i = EEPROM_MAX;
1757 tmp.addr[i++] = inb(EWRK3_CMR);
1758 for (j=0;j<ETH_ALEN;j++) {
1759 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1760 }
1761 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1762 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1763 } else {
1764 status = -EPERM;
1765 }
1766
1767 break;
1768 case EWRK3_SET_EEPROM:
1769 if (suser()) {
1770 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1771 for (i=0; i<(EEPROM_MAX>>1); i++) {
1772 Write_EEPROM(tmp.val[i], iobase, i);
1773 }
1774 } else {
1775 status = -EPERM;
1776 }
1777
1778 break;
1779 case EWRK3_GET_CMR:
1780 tmp.addr[0] = inb(EWRK3_CMR);
1781 memcpy_tofs(ioc->data, tmp.addr, 1);
1782
1783 break;
1784 case EWRK3_SET_TX_CUT_THRU:
1785 if (suser()) {
1786 lp->txc = 1;
1787 } else {
1788 status = -EPERM;
1789 }
1790
1791 break;
1792 case EWRK3_CLR_TX_CUT_THRU:
1793 if (suser()) {
1794 lp->txc = 0;
1795 } else {
1796 status = -EPERM;
1797 }
1798
1799 break;
1800 default:
1801 status = -EOPNOTSUPP;
1802 }
1803
1804 return status;
1805 }
1806
1807 static char asc2hex(char value)
1808 {
1809 value -= 0x30;
1810 if (value >= 0) {
1811 if (value > 9) {
1812 value &= 0x1f;
1813 value -= 0x07;
1814 if ((value < 0x0a) || (value > 0x0f)) {
1815 value = -1;
1816 }
1817 }
1818 } else {
1819 value = -1;
1820 }
1821 return value;
1822 }
1823
1824 #ifdef MODULE
1825 char kernel_version[] = UTS_RELEASE;
1826 static struct device thisEthwrk = {
1827 " ",
1828 0, 0, 0, 0,
1829 0x300, 5,
1830 0, 0, 0, NULL, ewrk3_probe };
1831
1832 int io=0x300;
1833 int irq=5;
1834
1835 int
1836 init_module(void)
1837 {
1838 thisEthwrk.base_addr=io;
1839 thisEthwrk.irq=irq;
1840 if (register_netdev(&thisEthwrk) != 0)
1841 return -EIO;
1842 return 0;
1843 }
1844
1845 void
1846 cleanup_module(void)
1847 {
1848 if (MOD_IN_USE) {
1849 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1850 } else {
1851 unregister_netdev(&thisEthwrk);
1852 }
1853 }
1854 #endif
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866