This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
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129 static char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #ifdef MODULE
132 #include <linux/module.h>
133 #include <linux/version.h>
134 #endif
135
136 #include <stdarg.h>
137 #include <linux/kernel.h>
138 #include <linux/sched.h>
139 #include <linux/string.h>
140 #include <linux/ptrace.h>
141 #include <linux/errno.h>
142 #include <linux/ioport.h>
143 #include <linux/malloc.h>
144 #include <linux/interrupt.h>
145 #include <asm/bitops.h>
146 #include <asm/io.h>
147 #include <asm/dma.h>
148 #include <asm/segment.h>
149
150 #include <linux/netdevice.h>
151 #include <linux/etherdevice.h>
152 #include <linux/skbuff.h>
153
154 #include <linux/time.h>
155 #include <linux/types.h>
156 #include <linux/unistd.h>
157
158 #include "ewrk3.h"
159
160 #ifdef EWRK3_DEBUG
161 static int ewrk3_debug = EWRK3_DEBUG;
162 #else
163 static int ewrk3_debug = 1;
164 #endif
165
166 #ifndef PROBE_LENGTH
167 #define PROBE_LENGTH 32
168 #endif
169
170 #ifndef PROBE_SEQUENCE
171 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
172 #endif
173
174 #ifndef EWRK3_SIGNATURE
175 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
176 #define EWRK3_NAME_LENGTH 8
177 #endif
178
179 #ifndef EWRK3_RAM_BASE_ADDRESSES
180 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
181 #endif
182
183
184
185
186
187
188
189
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193
194
195
196
197 #define EWRK3_IO_BASE 0x100
198 #define EWRK3_IOP_INC 0x20
199 #define EWRK3_TOTAL_SIZE 0x20
200 #define EWRK3_IO_SEARCH 0x007dff7f
201 static long mem_chkd = EWRK3_IO_SEARCH;
202
203
204 #ifndef MAX_NUM_EWRK3S
205 #define MAX_NUM_EWRK3S 21
206 #endif
207
208 #ifndef EWRK3_EISA_IO_PORTS
209 #define EWRK3_EISA_IO_PORTS 0x0c00
210 #endif
211
212 #ifndef MAX_EISA_SLOTS
213 #define MAX_EISA_SLOTS 8
214 #define EISA_SLOT_INC 0x1000
215 #endif
216
217 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
218 #define CRC_POLYNOMIAL_LE 0xedb88320UL
219
220
221
222
223 #define IO_ONLY 0x00
224 #define SHMEM_2K 0x800
225 #define SHMEM_32K 0x8000
226 #define SHMEM_64K 0x10000
227
228
229
230
231 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
232
233 #define ENABLE_IRQs \
234 icr |= irq_mask;\
235 outb(icr, EWRK3_ICR)
236
237 #define DISABLE_IRQs \
238 icr = inb(EWRK3_ICR);\
239 icr &= ~irq_mask;\
240 outb(icr, EWRK3_ICR)
241
242
243
244
245 #define START_EWRK3 \
246 csr = inb(EWRK3_CSR);\
247 csr &= ~(TXD|RXD);\
248 outb(csr, EWRK3_CSR)
249
250 #define STOP_EWRK3 \
251 csr = (TXD|RXD);\
252 outb(csr, EWRK3_CSR)
253
254
255
256
257 #define EWRK3_PKT_STAT_SZ 16
258 #define EWRK3_PKT_BIN_SZ 128
259
260
261 struct ewrk3_private {
262 long shmem_base;
263 long shmem_length;
264 struct enet_statistics stats;
265 struct {
266 unsigned long bins[EWRK3_PKT_STAT_SZ];
267 unsigned long unicast;
268 unsigned long multicast;
269 unsigned long broadcast;
270 unsigned long excessive_collisions;
271 unsigned long tx_underruns;
272 unsigned long excessive_underruns;
273 } pktStats;
274 short mPage;
275 unsigned char lemac;
276 unsigned char hard_strapped;
277 unsigned char lock;
278 unsigned char txc;
279 };
280
281
282
283
284 #define FORCE_2K_MODE \
285 shmem_length = SHMEM_2K;\
286 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
287
288
289
290
291 static int ewrk3_open(struct device *dev);
292 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
293 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
294 static int ewrk3_close(struct device *dev);
295 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
296 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
297 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
298
299
300
301
302 static int ewrk3_hw_init(struct device *dev, short iobase);
303 static void ewrk3_init(struct device *dev);
304 static int ewrk3_rx(struct device *dev);
305 static int ewrk3_tx(struct device *dev);
306
307 static void EthwrkSignature(char * name, char *eeprom_image);
308 static int DevicePresent(short iobase);
309 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
310
311 static int Read_EEPROM(short iobase, unsigned char eaddr);
312 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
313 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
314
315 #ifndef MODULE
316 static struct device *isa_probe(struct device *dev);
317 static struct device *eisa_probe(struct device *dev);
318 static struct device *alloc_device(struct device *dev, int iobase);
319
320 static int num_ewrk3s = 0, num_eth = 0;
321 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
322
323 #else
324 int init_module(void);
325 void cleanup_module(void);
326
327 #endif
328
329 static int autoprobed = 0;
330
331
332
333
334 #define INIT_EWRK3 {\
335 int i;\
336 outb(EEPROM_INIT, EWRK3_IOPR);\
337 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
338 }
339
340
341
342
343 int ewrk3_probe(struct device *dev)
344 {
345 int base_addr = dev->base_addr;
346 int status = -ENODEV;
347 #ifndef MODULE
348 struct device *eth0;
349 #endif
350
351 if (base_addr > 0x0ff) {
352 if (!autoprobed) {
353 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
354 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
355 if (DevicePresent(base_addr) == 0) {
356
357 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
358 status = ewrk3_hw_init(dev, base_addr);
359 } else {
360 printk("ewrk3_probe(): No device found\n");
361 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
362 }
363 }
364 } else {
365 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
366 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
367 }
368 } else {
369 status = ewrk3_hw_init(dev, base_addr);
370 }
371 } else if (base_addr > 0) {
372 status = -ENXIO;
373
374 #ifdef MODULE
375 } else {
376 printk("Autoprobing is not supported when loading a module based driver.\n");
377 status = -EIO;
378 #else
379 } else if (!autoprobed) {
380
381 eth0=isa_probe(dev);
382 eth0=eisa_probe(eth0);
383 if (dev->priv) status=0;
384 autoprobed = 1;
385 } else {
386 status = -ENXIO;
387 #endif
388
389 }
390
391 if (status) dev->base_addr = base_addr;
392
393 return status;
394 }
395
396 static int
397 ewrk3_hw_init(struct device *dev, short iobase)
398 {
399 struct ewrk3_private *lp;
400 int i, status=0;
401 unsigned long mem_start, shmem_length;
402 char name[EWRK3_NAME_LENGTH + 1];
403 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
404 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
405
406
407
408
409
410 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
411 INIT_EWRK3;
412
413 nicsr = inb(EWRK3_CSR);
414
415
416
417
418 DISABLE_IRQs;
419
420 if (nicsr == TXD|RXD) {
421
422
423
424
425 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
426 union {
427 short val;
428 char c[2];
429 } tmp;
430
431 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
432 eeprom_image[i] = tmp.c[0];
433 eeprom_image[i+1] = tmp.c[1];
434
435 chksum += eeprom_image[i] + eeprom_image[i+1];
436 }
437
438 if (chksum != 0) {
439 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
440 status = -ENXIO;
441 } else {
442
443
444
445 EthwrkSignature(name, eeprom_image);
446
447 if (*name != '\0') {
448 dev->base_addr = iobase;
449
450 if (iobase > 0x400) {
451 outb(eisa_cr, EISA_CR);
452 }
453
454 lemac = eeprom_image[EEPROM_CHIPVER];
455 cmr = inb(EWRK3_CMR);
456
457 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
458 ((lemac == LeMAC2) && !(cmr & HS))) {
459 printk("%s: %s at %#3x", dev->name, name, iobase);
460 hard_strapped = 1;
461 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
462
463 printk("%s: %s at %#3x (EISA slot %d)",
464 dev->name, name, iobase, ((iobase>>12)&0x0f));
465 } else {
466 printk("%s: %s at %#3x", dev->name, name, iobase);
467 }
468
469 if (!status) {
470 printk(", h/w address ");
471 if (lemac == LeMAC2) {
472 for (i = 0;i < ETH_ALEN - 1;i++) {
473 printk("%2.2x:", dev->dev_addr[i] =
474 eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 }
477 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
478 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
479 } else {
480 DevicePresent(iobase);
481 for (i = 0; i < ETH_ALEN - 1; i++) {
482 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
486 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
487 }
488
489 if (aprom_crc(dev, eeprom_image, lemac)) {
490 printk(" which has an EEPROM CRC error.\n");
491 status = -ENXIO;
492 } else {
493 if (lemac == LeMAC2) {
494 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
495 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
496 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
497 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
498 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
499 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
500 }
501 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
502 outb(cmr, EWRK3_CMR);
503
504 cr = inb(EWRK3_CR);
505 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
506 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
507 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
508 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
509 outb(cr, EWRK3_CR);
510
511
512
513
514
515 mem_start = inb(EWRK3_MBR);
516 shmem_length = 0;
517 if (mem_start != 0) {
518 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
519 mem_start *= SHMEM_64K;
520 shmem_length = SHMEM_64K;
521 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
522 mem_start *= SHMEM_32K;
523 shmem_length = SHMEM_32K;
524 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
525 mem_start = mem_start * SHMEM_2K + 0x80000;
526 shmem_length = SHMEM_2K;
527 } else {
528 status = -ENXIO;
529 }
530 }
531
532
533
534
535
536
537
538 if (!status) {
539 if (hard_strapped) {
540 printk(" is hard strapped.\n");
541 } else if (mem_start) {
542 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
543 printk(" at 0x%.5lx", mem_start);
544 } else {
545 printk(" is in I/O only mode");
546 }
547
548
549 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
550 GFP_KERNEL);
551 lp = (struct ewrk3_private *)dev->priv;
552 memset(dev->priv, 0, sizeof(struct ewrk3_private));
553 lp->shmem_base = mem_start;
554 lp->shmem_length = shmem_length;
555 lp->lemac = lemac;
556 lp->hard_strapped = hard_strapped;
557
558 lp->mPage = 64;
559 if (cmr & DRAM) lp->mPage <<= 1 ;
560
561 if (!hard_strapped) {
562
563
564
565 icr |= IE;
566 outb(icr, EWRK3_ICR);
567
568
569 dev->dma = 0;
570
571
572
573 if (dev->irq < 2) {
574 #ifndef MODULE
575 unsigned char irqnum;
576
577 autoirq_setup(0);
578
579
580
581
582 icr |=TNEM;
583 outb(1,EWRK3_TDQ);
584 outb(icr, EWRK3_ICR);
585
586 irqnum = irq[((icr & IRQ_SEL) >> 4)];
587
588 dev->irq = autoirq_report(1);
589 if ((dev->irq) && (irqnum == dev->irq)) {
590 printk(" and uses IRQ%d.\n", dev->irq);
591 } else {
592 if (!dev->irq) {
593 printk(" and failed to detect IRQ line.\n");
594 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
595 printk(" and an illegal IRQ line detected.\n");
596 } else {
597 printk(", but incorrect IRQ line detected.\n");
598 }
599 status = -ENXIO;
600 }
601
602 DISABLE_IRQs;
603
604 #endif
605 } else {
606 printk(" and requires IRQ%d.\n", dev->irq);
607 }
608 }
609 } else {
610 status = -ENXIO;
611 }
612 }
613 }
614 } else {
615 status = -ENXIO;
616 }
617 }
618
619 if (!status) {
620 if (ewrk3_debug > 0) {
621 printk(version);
622 }
623
624
625 dev->open = &ewrk3_open;
626 dev->hard_start_xmit = &ewrk3_queue_pkt;
627 dev->stop = &ewrk3_close;
628 dev->get_stats = &ewrk3_get_stats;
629 #ifdef HAVE_MULTICAST
630 dev->set_multicast_list = &set_multicast_list;
631 #endif
632 dev->do_ioctl = &ewrk3_ioctl;
633
634 dev->mem_start = 0;
635
636
637 ether_setup(dev);
638 }
639 } else {
640 status = -ENXIO;
641 }
642
643 return status;
644 }
645
646
647 static int
648 ewrk3_open(struct device *dev)
649 {
650 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
651 int i, iobase = dev->base_addr;
652 int status = 0;
653 unsigned char icr, csr;
654
655
656
657
658 STOP_EWRK3;
659
660 if (!lp->hard_strapped) {
661 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
662 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
663 status = -EAGAIN;
664 } else {
665
666 irq2dev_map[dev->irq] = dev;
667
668
669
670
671 ewrk3_init(dev);
672
673 if (ewrk3_debug > 1){
674 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
675 printk("\tphysical address: ");
676 for (i=0;i<6;i++){
677 printk("%2.2x:",(short)dev->dev_addr[i]);
678 }
679 printk("\n");
680 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
681 if (lp->shmem_length == 0) {
682 printk("\tno shared memory, I/O only mode\n");
683 } else {
684 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
685 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
686 }
687 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
688 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
689 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
690 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
691 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
692 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
693 }
694
695 dev->tbusy = 0;
696 dev->start = 1;
697 dev->interrupt = UNMASK_INTERRUPTS;
698
699
700
701
702 icr = inb(EWRK3_ICR);
703 ENABLE_IRQs;
704
705 }
706 } else {
707 dev->start = 0;
708 dev->tbusy = 1;
709 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
710 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
711 }
712
713 #ifdef MODULE
714 MOD_INC_USE_COUNT;
715 #endif
716
717
718 return status;
719 }
720
721
722
723
724 static void
725 ewrk3_init(struct device *dev)
726 {
727 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
728 char csr, page;
729 short iobase = dev->base_addr;
730
731
732
733
734 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
735
736
737
738
739 while (inb(EWRK3_TQ));
740 while (inb(EWRK3_TDQ));
741 while (inb(EWRK3_RQ));
742 while (inb(EWRK3_FMQ));
743
744
745
746
747 for (page=1;page<lp->mPage;page++) {
748 outb(page, EWRK3_FMQ);
749 }
750
751 lp->lock = 0;
752
753 START_EWRK3;
754 }
755
756
757
758
759 static int
760 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
761 {
762 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
763 int iobase = dev->base_addr;
764 int status = 0;
765 unsigned char icr, csr;
766
767
768 if (dev->tbusy || lp->lock) {
769 int tickssofar = jiffies - dev->trans_start;
770 if (tickssofar < 10) {
771 status = -1;
772 } else if (!lp->hard_strapped) {
773 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
774 dev->name, inb(EWRK3_CSR));
775
776
777
778
779 DISABLE_IRQs;
780
781
782
783
784 STOP_EWRK3;
785
786 ewrk3_init(dev);
787
788
789
790
791 ENABLE_IRQs;
792
793 dev->tbusy=0;
794 dev->trans_start = jiffies;
795 }
796 } else if (skb == NULL) {
797 dev_tint(dev);
798 } else if (skb->len > 0) {
799
800
801
802
803
804 if (set_bit(0, (void*)&dev->tbusy) != 0)
805 printk("%s: Transmitter access conflict.\n", dev->name);
806
807 DISABLE_IRQs;
808
809
810
811
812 if (inb(EWRK3_FMQC) > 0) {
813 unsigned char *buf;
814 unsigned char page;
815
816 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
817 buf = NULL;
818
819
820
821
822 while (set_bit(0, (void *)&lp->lock) != 0);
823 if (lp->shmem_length == IO_ONLY) {
824 outb(page, EWRK3_IOPR);
825 } else if (lp->shmem_length == SHMEM_2K) {
826 buf = (char *) lp->shmem_base;
827 outb(page, EWRK3_MPR);
828 } else if (lp->shmem_length == SHMEM_32K) {
829 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
830 outb((page >> 4), EWRK3_MPR);
831 } else if (lp->shmem_length == SHMEM_64K) {
832 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
833 outb((page >> 5), EWRK3_MPR);
834 } else {
835 status = -1;
836 printk("%s: Oops - your private data area is hosed!\n",dev->name);
837 }
838
839 if (!status) {
840
841
842
843
844
845
846 if (lp->shmem_length == IO_ONLY) {
847 int i;
848 unsigned char *p = skb->data;
849
850 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
851 outb((char)(skb->len & 0xff), EWRK3_DATA);
852 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
853 outb((char)0x04, EWRK3_DATA);
854 for (i=0; i<skb->len; i++) {
855 outb(*p++, EWRK3_DATA);
856 }
857 outb(page, EWRK3_TQ);
858 } else {
859 *buf++ = (char)(QMODE | PAD | IFC);
860 *buf++ = (char)(skb->len & 0xff);
861 if (lp->txc) {
862 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
863 *buf++ = 0x04;
864 *(buf + skb->len) = 0x00;
865 memcpy(buf, skb->data, PRELOAD);
866 outb(page, EWRK3_TQ);
867 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
868 *(buf + skb->len) = 0xff;
869 } else {
870 *buf++ = (char)((skb->len >> 8) & 0xff);
871 *buf++ = 0x04;
872 memcpy(buf, skb->data, skb->len);
873 outb(page, EWRK3_TQ);
874 }
875 }
876
877 dev->trans_start = jiffies;
878
879 dev_kfree_skb (skb, FREE_WRITE);
880
881 } else {
882 outb(page, EWRK3_FMQ);
883 }
884 lp->lock = 0;
885 } else {
886 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
887 (unsigned char) page);
888 }
889 } else {
890 printk("ewrk3_queue_pkt(): No free resources...\n");
891 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
892 }
893
894
895 if (inb(EWRK3_FMQC) > 0) {
896 dev->tbusy = 0;
897 }
898
899 ENABLE_IRQs;
900 }
901
902 return status;
903 }
904
905
906
907
908 static void
909 ewrk3_interrupt(int irq, struct pt_regs * regs)
910 {
911 struct device *dev = (struct device *)(irq2dev_map[irq]);
912 struct ewrk3_private *lp;
913 int iobase;
914 unsigned char icr, cr, csr;
915
916 if (dev == NULL) {
917 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
918 } else {
919 lp = (struct ewrk3_private *)dev->priv;
920 iobase = dev->base_addr;
921
922 if (dev->interrupt)
923 printk("%s: Re-entering the interrupt handler.\n", dev->name);
924
925 dev->interrupt = MASK_INTERRUPTS;
926
927
928 csr = inb(EWRK3_CSR);
929
930
931
932
933 DISABLE_IRQs;
934
935 cr = inb(EWRK3_CR);
936 cr |= LED;
937 outb(cr, EWRK3_CR);
938
939 if (csr & RNE)
940 ewrk3_rx(dev);
941
942 if (csr & TNE)
943 ewrk3_tx(dev);
944
945
946
947
948
949
950
951 if (inb(EWRK3_FMQC)) {
952 irq_mask |= TXDM|RXDM;
953 csr &= ~(TXD|RXD);
954 outb(csr, EWRK3_CSR);
955 dev->tbusy = 0;
956 mark_bh(NET_BH);
957 } else {
958 irq_mask &= ~(TXDM|RXDM);
959 }
960
961
962 cr &= ~LED;
963 outb(cr, EWRK3_CR);
964
965 dev->interrupt = UNMASK_INTERRUPTS;
966
967 ENABLE_IRQs;
968 }
969
970 return;
971 }
972
973 static int
974 ewrk3_rx(struct device *dev)
975 {
976 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
977 int i, iobase = dev->base_addr;
978 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
979 int status = 0;
980
981 while (inb(EWRK3_RQC) && !status) {
982 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
983 buf = NULL;
984
985
986
987
988
989 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
990 if (lp->shmem_length == IO_ONLY) {
991 tmpPage = inb(EWRK3_IOPR);
992 } else {
993 tmpPage = inb(EWRK3_MPR);
994 }
995 }
996
997
998
999
1000 if (lp->shmem_length == IO_ONLY) {
1001 outb(page, EWRK3_IOPR);
1002 } else if (lp->shmem_length == SHMEM_2K) {
1003 buf = (char *) lp->shmem_base;
1004 outb(page, EWRK3_MPR);
1005 } else if (lp->shmem_length == SHMEM_32K) {
1006 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1007 outb((page >> 4), EWRK3_MPR);
1008 } else if (lp->shmem_length == SHMEM_64K) {
1009 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1010 outb((page >> 5), EWRK3_MPR);
1011 } else {
1012 status = -1;
1013 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1014 }
1015
1016 if (!status) {
1017 char rx_status;
1018 int pkt_len;
1019
1020 if (lp->shmem_length == IO_ONLY) {
1021 rx_status = inb(EWRK3_DATA);
1022 pkt_len = inb(EWRK3_DATA);
1023 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1024 } else {
1025 rx_status = (char)(*buf++);
1026 pkt_len = (short)(*buf+((*(buf+1))<<8));
1027 buf+=3;
1028 }
1029
1030 if (!(rx_status & ROK)) {
1031 lp->stats.rx_errors++;
1032 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1033 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1034 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1035 } else {
1036 struct sk_buff *skb;
1037
1038 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1039 skb->len = pkt_len;
1040 skb->dev = dev;
1041
1042 if (lp->shmem_length == IO_ONLY) {
1043 unsigned char *p = skb->data;
1044
1045 *p = inb(EWRK3_DATA);
1046 for (i=0; i<skb->len; i++) {
1047 *p++ = inb(EWRK3_DATA);
1048 }
1049 } else {
1050 memcpy(skb->data, buf, pkt_len);
1051 }
1052
1053
1054
1055
1056
1057
1058 skb->protocol=eth_type_trans(skb,dev);
1059 netif_rx(skb);
1060
1061
1062
1063
1064 lp->stats.rx_packets++;
1065 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1066 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1067 lp->pktStats.bins[i]++;
1068 i = EWRK3_PKT_STAT_SZ;
1069 }
1070 }
1071 buf = skb->data;
1072 if (buf[0] & 0x01) {
1073 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1074 lp->pktStats.broadcast++;
1075 } else {
1076 lp->pktStats.multicast++;
1077 }
1078 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1079 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1080 lp->pktStats.unicast++;
1081 }
1082
1083 lp->pktStats.bins[0]++;
1084 if (lp->pktStats.bins[0] == 0) {
1085 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1086 }
1087 } else {
1088 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1089 lp->stats.rx_dropped++;
1090 break;
1091 }
1092 }
1093 }
1094
1095
1096
1097 outb(page, EWRK3_FMQ);
1098
1099 if (tmpLock) {
1100 if (lp->shmem_length == IO_ONLY) {
1101 outb(tmpPage, EWRK3_IOPR);
1102 } else {
1103 outb(tmpPage, EWRK3_MPR);
1104 }
1105 }
1106 lp->lock = 0;
1107 } else {
1108 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1109 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1110 }
1111 }
1112 return status;
1113 }
1114
1115
1116
1117
1118 static int
1119 ewrk3_tx(struct device *dev)
1120 {
1121 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1122 int iobase = dev->base_addr;
1123 unsigned char tx_status;
1124
1125 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1126 if (tx_status & VSTS) {
1127 if (tx_status & MAC_TXE) {
1128 lp->stats.tx_errors++;
1129 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1130 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1131 if (tx_status & MAC_CTU) {
1132 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1133 lp->pktStats.tx_underruns++;
1134 } else {
1135 lp->pktStats.excessive_underruns++;
1136 }
1137 } else if (tx_status & MAC_COLL) {
1138 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1139 lp->stats.collisions++;
1140 } else {
1141 lp->pktStats.excessive_collisions++;
1142 }
1143 }
1144 } else {
1145 lp->stats.tx_packets++;
1146 }
1147 }
1148 }
1149
1150 return 0;
1151 }
1152
1153 static int
1154 ewrk3_close(struct device *dev)
1155 {
1156 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1157 int iobase = dev->base_addr;
1158 unsigned char icr, csr;
1159
1160 dev->start = 0;
1161 dev->tbusy = 1;
1162
1163 if (ewrk3_debug > 1) {
1164 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1165 dev->name, inb(EWRK3_CSR));
1166 }
1167
1168
1169
1170
1171 DISABLE_IRQs;
1172
1173 STOP_EWRK3;
1174
1175
1176
1177
1178
1179
1180
1181 while (inb(EWRK3_TQ));
1182 while (inb(EWRK3_TDQ));
1183 while (inb(EWRK3_RQ));
1184
1185 if (!lp->hard_strapped) {
1186 free_irq(dev->irq);
1187
1188 irq2dev_map[dev->irq] = 0;
1189 }
1190
1191 #ifdef MODULE
1192 MOD_DEC_USE_COUNT;
1193 #endif
1194
1195 return 0;
1196 }
1197
1198 static struct enet_statistics *
1199 ewrk3_get_stats(struct device *dev)
1200 {
1201 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1202
1203
1204
1205 return &lp->stats;
1206 }
1207
1208
1209
1210
1211
1212
1213
1214
1215 static void
1216 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1217 {
1218 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1219 int iobase = dev->base_addr;
1220 char *multicast_table;
1221 unsigned char csr;
1222
1223 csr = inb(EWRK3_CSR);
1224
1225 if (lp->shmem_length == IO_ONLY) {
1226 multicast_table = (char *) PAGE0_HTE;
1227 } else {
1228 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1229 }
1230
1231 if (num_addrs >= 0) {
1232 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1233 csr &= ~PME;
1234 csr |= MCE;
1235 outb(csr, EWRK3_CSR);
1236 } else {
1237 csr |= PME;
1238 csr &= ~MCE;
1239 outb(csr, EWRK3_CSR);
1240 }
1241 }
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1252 {
1253 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1254 int i, iobase = dev->base_addr;
1255 char j, bit, byte;
1256 short *p = (short *) multicast_table;
1257 u_short hashcode;
1258 u_long crc, poly = CRC_POLYNOMIAL_LE;
1259
1260 while (set_bit(0, (void *)&lp->lock) != 0);
1261
1262 if (lp->shmem_length == IO_ONLY) {
1263 outb(0, EWRK3_IOPR);
1264 outw((short)((long)multicast_table), EWRK3_PIR1);
1265 } else {
1266 outb(0, EWRK3_MPR);
1267 }
1268
1269 if (num_addrs == HASH_TABLE_LEN) {
1270 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1271 if (lp->shmem_length == IO_ONLY) {
1272 outb(0xff, EWRK3_DATA);
1273 } else {
1274 *p++ = 0xffff;
1275 i++;
1276 }
1277 }
1278 } else {
1279
1280 if (lp->shmem_length == IO_ONLY) {
1281 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1282 outb(0x00, EWRK3_DATA);
1283 }
1284 outb(0x80, EWRK3_DATA); i++;
1285 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1286 outb(0x00, EWRK3_DATA);
1287 }
1288 } else {
1289 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1290 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1291 }
1292
1293
1294 for (i=0;i<num_addrs;i++) {
1295 if ((*addrs & 0x01) == 1) {
1296 crc = 0xffffffff;
1297 for (byte=0;byte<ETH_ALEN;byte++) {
1298
1299 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1300 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1301 }
1302 }
1303 hashcode = crc & ((1 << 9) - 1);
1304
1305 byte = hashcode >> 3;
1306 bit = 1 << (hashcode & 0x07);
1307
1308 if (lp->shmem_length == IO_ONLY) {
1309 unsigned char tmp;
1310
1311 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1312 tmp = inb(EWRK3_DATA);
1313 tmp |= bit;
1314 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1315 outb(tmp, EWRK3_DATA);
1316 } else {
1317 multicast_table[byte] |= bit;
1318 }
1319 } else {
1320 addrs += ETH_ALEN;
1321 }
1322 }
1323 }
1324
1325 lp->lock = 0;
1326
1327 return;
1328 }
1329
1330 #ifndef MODULE
1331
1332
1333
1334 static struct device *isa_probe(struct device *dev)
1335 {
1336 int i, iobase, status;
1337 unsigned long int tmp = mem_chkd;
1338
1339 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1340 i < 24;
1341 iobase += EWRK3_IOP_INC, i++) {
1342 if (tmp & 0x01) {
1343
1344 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1345 if (DevicePresent(iobase) == 0) {
1346
1347
1348
1349
1350 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1351 if (num_ewrk3s > 0) {
1352 dev = alloc_device(dev, iobase);
1353 } else {
1354 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1355 num_ewrk3s++;
1356 }
1357 }
1358 num_eth++;
1359 } else {
1360 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1361 }
1362 } else {
1363 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1364 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1365 }
1366 }
1367 tmp >>= 1;
1368 }
1369
1370 return dev;
1371 }
1372
1373
1374
1375
1376
1377 static struct device *eisa_probe(struct device *dev)
1378 {
1379 int i, iobase = EWRK3_EISA_IO_PORTS;
1380 int status;
1381
1382 iobase+=EISA_SLOT_INC;
1383 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1384
1385
1386 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1387 if (DevicePresent(iobase) == 0) {
1388
1389
1390
1391
1392 mem_chkd |= (0x01 << (i + 24));
1393 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1394 if (num_ewrk3s > 0) {
1395 dev = alloc_device(dev, iobase);
1396 } else {
1397 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1398 num_ewrk3s++;
1399 }
1400 }
1401 num_eth++;
1402 }
1403 }
1404 }
1405 return dev;
1406 }
1407
1408
1409
1410
1411
1412 static struct device *alloc_device(struct device *dev, int iobase)
1413 {
1414
1415
1416
1417 while (dev->next != NULL) {
1418 if (dev->next->base_addr == 0xffe0) break;
1419 dev = dev->next;
1420 num_eth++;
1421 }
1422
1423
1424
1425
1426
1427 if (dev->next == NULL) {
1428 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1429 GFP_KERNEL);
1430 if (dev->next == NULL) {
1431 printk("eth%d: Device not initialised, insufficient memory\n",
1432 num_eth);
1433 }
1434 }
1435
1436
1437
1438
1439
1440
1441 if ((dev->next != NULL) &&
1442 (num_eth > 0) && (num_eth < 9999)) {
1443 dev = dev->next;
1444 dev->name = (char *)(dev + sizeof(struct device));
1445 sprintf(dev->name,"eth%d", num_eth);
1446 dev->base_addr = iobase;
1447 dev->next = NULL;
1448 dev->init = &ewrk3_probe;
1449 num_ewrk3s++;
1450 }
1451
1452 return dev;
1453 }
1454 #endif
1455
1456
1457
1458
1459 static int Read_EEPROM(short iobase, unsigned char eaddr)
1460 {
1461 int i;
1462
1463 outb((eaddr & 0x3f), EWRK3_PIR1);
1464 outb(EEPROM_RD, EWRK3_IOPR);
1465 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1466
1467 return inw(EWRK3_EPROM1);
1468 }
1469
1470
1471
1472
1473 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1474 {
1475 int i;
1476
1477 outb(EEPROM_WR_EN, EWRK3_IOPR);
1478 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1479 outw(data, EWRK3_EPROM1);
1480 outb((eaddr & 0x3f), EWRK3_PIR1);
1481 outb(EEPROM_WR, EWRK3_IOPR);
1482 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1483 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1484 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1485
1486 return 0;
1487 }
1488
1489
1490
1491
1492 static void EthwrkSignature(char *name, char *eeprom_image)
1493 {
1494 unsigned long i,j,k;
1495 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1496
1497 strcpy(name, "");
1498 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1499 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1500 if (signatures[i][k] == eeprom_image[j]) {
1501 k++;
1502 } else {
1503 k=0;
1504 }
1505 }
1506 if (k == strlen(signatures[i])) {
1507 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1508 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1509 name[EWRK3_NAME_LENGTH] = '\0';
1510 }
1511 }
1512 }
1513
1514 return;
1515 }
1516
1517
1518
1519
1520
1521
1522 static int DevicePresent(short iobase)
1523 {
1524 static short fp=1,sigLength=0;
1525 static char devSig[] = PROBE_SEQUENCE;
1526 char data;
1527 int i, j, status = 0;
1528 static char asc2hex(char value);
1529
1530
1531
1532
1533 if (fp) {
1534 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1535 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1536 devSig[i]<<=4;
1537 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1538 devSig[j]=devSig[i]+devSig[i+1];
1539 } else {
1540 status= -1;
1541 }
1542 } else {
1543 status= -1;
1544 }
1545 }
1546 sigLength=j;
1547 fp = 0;
1548 }
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558 if (!status) {
1559 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1560 data = inb(EWRK3_APROM);
1561 if (devSig[j] == data) {
1562 j++;
1563 } else {
1564 j=0;
1565 }
1566 }
1567
1568 if (j!=sigLength) {
1569 status = -ENODEV;
1570 }
1571 }
1572
1573 return status;
1574 }
1575
1576 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1577 {
1578 long k;
1579 unsigned short j,chksum;
1580 unsigned char crc, lfsr, sd, status = 0;
1581 int iobase = dev->base_addr;
1582
1583 if (chipType == LeMAC2) {
1584 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1585 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1586 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1587 crc = (crc >> 1) + lfsr;
1588 }
1589 }
1590 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1591 } else {
1592 for (k=0,j=0;j<3;j++) {
1593 k <<= 1 ;
1594 if (k > 0xffff) k-=0xffff;
1595 k += inw(EWRK3_PAR0 + (j<<1));
1596 if (k > 0xffff) k-=0xffff;
1597 }
1598 if (k == 0xffff) k=0;
1599 chksum = inb(EWRK3_APROM);
1600 chksum |= (inb(EWRK3_APROM)<<8);
1601 if (k != chksum) status = -1;
1602 }
1603
1604 return status;
1605 }
1606
1607
1608
1609
1610
1611 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1612 {
1613 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1614 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1615 int i, j, iobase = dev->base_addr, status = 0;
1616 unsigned char csr;
1617 union {
1618 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1619 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1620 } tmp;
1621
1622 switch(ioc->cmd) {
1623 case EWRK3_GET_HWADDR:
1624 for (i=0; i<ETH_ALEN; i++) {
1625 tmp.addr[i] = dev->dev_addr[i];
1626 }
1627 ioc->len = ETH_ALEN;
1628 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1629
1630 break;
1631 case EWRK3_SET_HWADDR:
1632 if (suser()) {
1633 csr = inb(EWRK3_CSR);
1634 csr |= (TXD|RXD);
1635 outb(csr, EWRK3_CSR);
1636
1637 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1638 for (i=0; i<ETH_ALEN; i++) {
1639 dev->dev_addr[i] = tmp.addr[i];
1640 outb(tmp.addr[i], EWRK3_PAR0 + i);
1641 }
1642
1643 csr &= ~(TXD|RXD);
1644 outb(csr, EWRK3_CSR);
1645 } else {
1646 status = -EPERM;
1647 }
1648
1649 break;
1650 case EWRK3_SET_PROM:
1651 if (suser()) {
1652 csr = inb(EWRK3_CSR);
1653 csr |= PME;
1654 csr &= ~MCE;
1655 outb(csr, EWRK3_CSR);
1656 } else {
1657 status = -EPERM;
1658 }
1659
1660 break;
1661 case EWRK3_CLR_PROM:
1662 if (suser()) {
1663 csr = inb(EWRK3_CSR);
1664 csr &= ~PME;
1665 outb(csr, EWRK3_CSR);
1666 } else {
1667 status = -EPERM;
1668 }
1669
1670 break;
1671 case EWRK3_SAY_BOO:
1672 printk("%s: Boo!\n", dev->name);
1673
1674 break;
1675 case EWRK3_GET_MCA:
1676 while (set_bit(0, (void *)&lp->lock) != 0);
1677 if (lp->shmem_length == IO_ONLY) {
1678 outb(0, EWRK3_IOPR);
1679 outw(PAGE0_HTE, EWRK3_PIR1);
1680 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1681 tmp.addr[i] = inb(EWRK3_DATA);
1682 }
1683 } else {
1684 outb(0, EWRK3_MPR);
1685 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1686 }
1687 ioc->len = (HASH_TABLE_LEN >> 3);
1688 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1689 lp->lock = 0;
1690
1691 break;
1692 case EWRK3_SET_MCA:
1693 if (suser()) {
1694 if (ioc->len != HASH_TABLE_LEN) {
1695 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1696 }
1697 set_multicast_list(dev, ioc->len, tmp.addr);
1698 } else {
1699 status = -EPERM;
1700 }
1701
1702 break;
1703 case EWRK3_CLR_MCA:
1704 if (suser()) {
1705 set_multicast_list(dev, 0, NULL);
1706 } else {
1707 status = -EPERM;
1708 }
1709
1710 break;
1711 case EWRK3_MCA_EN:
1712 if (suser()) {
1713 csr = inb(EWRK3_CSR);
1714 csr |= MCE;
1715 csr &= ~PME;
1716 outb(csr, EWRK3_CSR);
1717 } else {
1718 status = -EPERM;
1719 }
1720
1721 break;
1722 case EWRK3_GET_STATS:
1723 cli();
1724 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1725 ioc->len = EWRK3_PKT_STAT_SZ;
1726 sti();
1727
1728 break;
1729 case EWRK3_CLR_STATS:
1730 if (suser()) {
1731 cli();
1732 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1733 sti();
1734 } else {
1735 status = -EPERM;
1736 }
1737
1738 break;
1739 case EWRK3_GET_CSR:
1740 tmp.addr[0] = inb(EWRK3_CSR);
1741 memcpy_tofs(ioc->data, tmp.addr, 1);
1742
1743 break;
1744 case EWRK3_SET_CSR:
1745 if (suser()) {
1746 memcpy_fromfs(tmp.addr, ioc->data, 1);
1747 outb(tmp.addr[0], EWRK3_CSR);
1748 } else {
1749 status = -EPERM;
1750 }
1751
1752 break;
1753 case EWRK3_GET_EEPROM:
1754 if (suser()) {
1755 for (i=0; i<(EEPROM_MAX>>1); i++) {
1756 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1757 }
1758 i = EEPROM_MAX;
1759 tmp.addr[i++] = inb(EWRK3_CMR);
1760 for (j=0;j<ETH_ALEN;j++) {
1761 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1762 }
1763 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1764 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1765 } else {
1766 status = -EPERM;
1767 }
1768
1769 break;
1770 case EWRK3_SET_EEPROM:
1771 if (suser()) {
1772 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1773 for (i=0; i<(EEPROM_MAX>>1); i++) {
1774 Write_EEPROM(tmp.val[i], iobase, i);
1775 }
1776 } else {
1777 status = -EPERM;
1778 }
1779
1780 break;
1781 case EWRK3_GET_CMR:
1782 tmp.addr[0] = inb(EWRK3_CMR);
1783 memcpy_tofs(ioc->data, tmp.addr, 1);
1784
1785 break;
1786 case EWRK3_SET_TX_CUT_THRU:
1787 if (suser()) {
1788 lp->txc = 1;
1789 } else {
1790 status = -EPERM;
1791 }
1792
1793 break;
1794 case EWRK3_CLR_TX_CUT_THRU:
1795 if (suser()) {
1796 lp->txc = 0;
1797 } else {
1798 status = -EPERM;
1799 }
1800
1801 break;
1802 default:
1803 status = -EOPNOTSUPP;
1804 }
1805
1806 return status;
1807 }
1808
1809 static char asc2hex(char value)
1810 {
1811 value -= 0x30;
1812 if (value >= 0) {
1813 if (value > 9) {
1814 value &= 0x1f;
1815 value -= 0x07;
1816 if ((value < 0x0a) || (value > 0x0f)) {
1817 value = -1;
1818 }
1819 }
1820 } else {
1821 value = -1;
1822 }
1823 return value;
1824 }
1825
1826 #ifdef MODULE
1827 char kernel_version[] = UTS_RELEASE;
1828 static struct device thisEthwrk = {
1829 " ",
1830 0, 0, 0, 0,
1831 0x300, 5,
1832 0, 0, 0, NULL, ewrk3_probe };
1833
1834 int io=0x300;
1835 int irq=5;
1836
1837 int
1838 init_module(void)
1839 {
1840 thisEthwrk.base_addr=io;
1841 thisEthwrk.irq=irq;
1842 if (register_netdev(&thisEthwrk) != 0)
1843 return -EIO;
1844 return 0;
1845 }
1846
1847 void
1848 cleanup_module(void)
1849 {
1850 if (MOD_IN_USE) {
1851 printk("%s: device busy, remove delayed\n",thisEthwrk.name);
1852 } else {
1853 unregister_netdev(&thisEthwrk);
1854 }
1855 }
1856 #endif
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868