root/drivers/net/pi2.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. pi0_preprobe
  2. random
  3. wrtscc
  4. rdscc
  5. switchbuffers
  6. hardware_send_packet
  7. setup_rx_dma
  8. setup_tx_dma
  9. tdelay
  10. free_p
  11. a_txint
  12. a_exint
  13. a_rxint
  14. b_rxint
  15. b_txint
  16. b_exint
  17. hw_probe
  18. rts
  19. pi_header
  20. pi_rebuild_header
  21. scc_init
  22. chipset_init
  23. pi_init
  24. valid_dma_page
  25. pi_set_mac_address
  26. get_dma_buffer
  27. pi_probe
  28. pi_open
  29. pi_send_packet
  30. pi_interrupt
  31. pi_close
  32. pi_ioctl
  33. pi_get_stats

   1 /*
   2    pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
   3    Copyright (c) 1994 David Perry
   4 
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License version 2, as
   7    published by the Free Software Foundation.
   8 
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12    General Public License for more details.
  13 
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software Foundation,
  16    Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  17 
  18    The file skeleton.c by Donald Becker was used as a starting point
  19    for this driver.
  20 
  21    Revision History
  22 
  23    April 6, 1994  (dp) Created
  24                        version 0.0 ALPHA
  25    April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
  26                        version 0.1 ALPHA
  27    April 13, 1994 (dp) Included address probing from JPM, autoirq
  28                        version 0.2 ALPHA
  29    April 14, 1994 (ac) Sketched in the NET3 changes.
  30    April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
  31                        instead of kmalloc() to ensure that DMA buffers will
  32                        reside under the 16 meg line.
  33                        version 0.4 ALPHA
  34    April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
  35                        Fixed a nasty problem with DMA.
  36                        version 0.5 ALPHA
  37    June 6, 1994 (ac)   Fixed to match the buffer locking changes. Added a hack to
  38                        fix a funny I see (search for HACK) and fixed the calls in
  39                        init() so it doesn't migrate module based ethernet cards up
  40                        to eth2 Took out the old module ideas as they are no longer
  41                        relevant to the PI driver.
  42    July 16, 1994 (dp)  Fixed the B channel rx overrun problem ac referred to 
  43                        above. Also added a bit of a hack to improve the maximum
  44                        baud rate on the B channel (Search for STUFF2). Included
  45                        ioctl stuff from John Paul Morrison. version 0.6 ALPHA
  46    Feb 9, 1995 (dp)    Updated for 1.1.90 kernel
  47                        version 0.7 ALPHA
  48    Apr 6, 1995 (ac)    Tweaks for NET3 pre snapshot 002 AX.25
  49    April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
  50                        when changing the baud rate or clock mode.
  51                        version 0.8 ALPHA
  52          
  53 */
  54 
  55 /* The following #define invokes a hack that will improve performance (baud)
  56    for the B port. The up side is it makes 9600 baud work ok on the B port.
  57    It may do 38400, depending on the host. The down side is it burns up
  58    CPU cycles with ints locked for up to 1 character time, at the beginning
  59    of each transmitted packet. If this causes you to lose sleep, #undefine it.
  60 */
  61 
  62 #define STUFF2 1
  63 
  64 /* The default configuration */
  65 #define PI_DMA 3
  66 
  67 #define DEF_A_SPEED 0           /* 0 means external clock */
  68 #define DEF_A_TXDELAY 15        /* 15 mS transmit delay */
  69 #define DEF_A_PERSIST 128       /* 50% persistence */
  70 #define DEF_A_SLOTIME 15        /* 15 mS slot time */
  71 #define DEF_A_SQUELDELAY 1      /* 1 mS squelch delay - allows fcs and flag */
  72 #define DEF_A_CLOCKMODE 0       /* clock mode - 0 is normal */
  73 
  74 #define DEF_B_SPEED 1200        /* 1200 baud */
  75 #define DEF_B_TXDELAY 40        /* 400 mS */
  76 #define DEF_B_PERSIST 128       /* 50% */
  77 #define DEF_B_SLOTIME 30        /* 300 mS */
  78 #define DEF_B_SQUELDELAY 3      /* 30 mS */
  79 #define DEF_B_CLOCKMODE 0       /* Normal clock mode */
  80 
  81 struct device *init_etherdev(struct device *dev, int sizeof_private,
  82                              unsigned long *mem_startp);
  83 
  84 static char *version =
  85 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
  86 
  87 /* The following #define is only really required for the PI card, not
  88    the PI2 - but it's safer to leave it in. */
  89 #define REALLY_SLOW_IO 1
  90 
  91 #define PI2_MODULE 0
  92 
  93 #if PI2_MODULE > 0
  94 #include <linux/modules.h>
  95 #endif
  96 
  97 #include <linux/config.h>
  98 #include <linux/kernel.h>
  99 #include <linux/sched.h>
 100 #include <linux/types.h>
 101 #include <linux/fcntl.h>
 102 #include <linux/interrupt.h>
 103 #include <linux/ptrace.h>
 104 #include <linux/ioport.h>
 105 #include <linux/in.h>
 106 #include <linux/malloc.h>
 107 #include <linux/string.h>
 108 #include <linux/errno.h>
 109 #include <asm/system.h>
 110 #include <asm/bitops.h>
 111 #include <asm/io.h>
 112 #include <asm/dma.h>
 113 #include <asm/segment.h>
 114 #include <linux/inet.h>
 115 #include <linux/netdevice.h>
 116 #include <linux/etherdevice.h>
 117 #include <linux/skbuff.h>
 118 #include <linux/timer.h>
 119 #include "pi2.h"
 120 #include "z8530.h"
 121 #include "ax25.h"
 122 
 123 
 124 struct mbuf {
 125     struct mbuf *next;
 126     int cnt;
 127     char data[0];
 128 };
 129 
 130 /*
 131  *      The actual devices we will use
 132  */
 133  
 134 /*
 135  *      PI device declarations.
 136  */
 137  
 138 static int pi0_preprobe(struct device *dev){return 0;}  /* Dummy probe function */
     /* [previous][next][first][last][top][bottom][index][help] */
 139 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 140 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 141 
 142  
 143 /* The number of low I/O ports used by the card. */
 144 #define PI_TOTAL_SIZE   8
 145 
 146 
 147 /* Index to functions, as function prototypes. */
 148 
 149 static int pi_probe(struct device *dev, int card_type);
 150 static int pi_open(struct device *dev);
 151 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
 152 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
 153 static int pi_close(struct device *dev);
 154 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 155 static struct enet_statistics *pi_get_stats(struct device *dev);
 156 static void rts(struct pi_local *lp, int x);
 157 static void b_rxint(struct device *dev, struct pi_local *lp);
 158 static void b_txint(struct pi_local *lp);
 159 static void b_exint(struct pi_local *lp);
 160 static void a_rxint(struct device *dev, struct pi_local *lp);
 161 static void a_txint(struct pi_local *lp);
 162 static void a_exint(struct pi_local *lp);
 163 static char *get_dma_buffer(unsigned long *mem_ptr);
 164 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 165 
 166 static char ax25_bcast[7] =
 167 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 168 static char ax25_test[7] =
 169 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 170 
 171 static int ext2_secrm_seed = 152;       /* Random generator base */
 172 
 173 static inline unsigned char random(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 174 {
 175     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
 176                             * 69069l + 1);
 177 }
 178 
 179 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
     /* [previous][next][first][last][top][bottom][index][help] */
 180 {
 181     /* assume caller disables interrupts! */
 182     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 183     outb_p(sccreg, ctl);        /* Select register */
 184     outb_p(val, ctl);           /* Output value */
 185     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 186 }
 187 
 188 static inline int rdscc(int cbase, int ctl, int sccreg)
     /* [previous][next][first][last][top][bottom][index][help] */
 189 {
 190     int retval;
 191 
 192     /* assume caller disables interrupts! */
 193     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 194     outb_p(sccreg, ctl);        /* Select register */
 195     retval = inb_p(ctl);
 196     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 197     return retval;
 198 }
 199 
 200 static void switchbuffers(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 201 {
 202     if (lp->rcvbuf == lp->rxdmabuf1)
 203         lp->rcvbuf = lp->rxdmabuf2;
 204     else
 205         lp->rcvbuf = lp->rxdmabuf1;
 206 }
 207 
 208 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 209 {
 210     char kickflag;
 211     unsigned long flags;
 212 
 213     lp->stats.tx_packets++;
 214 
 215     save_flags(flags);
 216     cli();
 217     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 218     restore_flags(flags);
 219 
 220     skb_queue_tail(&lp->sndq, skb);
 221     if (kickflag) {
 222         /* simulate interrupt to xmit */
 223         switch (lp->base & 2) {
 224         case 2:
 225             a_txint(lp);        /* process interrupt */
 226             break;
 227         case 0:
 228             save_flags(flags);
 229             cli();
 230             if (lp->tstate == IDLE)
 231                 b_txint(lp);
 232             restore_flags(flags);
 233             break;
 234         }
 235     }
 236 }
 237 
 238 static void setup_rx_dma(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 239 {
 240     unsigned long flags;
 241     int cmd;
 242     unsigned long dma_abs;
 243     unsigned dmachan;
 244 
 245     save_flags(flags);
 246     cli();
 247 
 248     dma_abs = (unsigned long) (lp->rcvbuf->data);
 249     dmachan = lp->dmachan;
 250     cmd = lp->base + CTL;
 251 
 252     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 253         panic("PI: RX buffer violates DMA boundary!");
 254 
 255     /* Get ready for RX DMA */
 256     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 257 
 258     disable_dma(dmachan);
 259     clear_dma_ff(dmachan);
 260 
 261     /* Set DMA mode register to single transfers, incrementing address,
 262      *  auto init, writes
 263      */
 264     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 265     set_dma_addr(dmachan, dma_abs);
 266     set_dma_count(dmachan, lp->bufsiz);
 267     enable_dma(dmachan);
 268 
 269     /* If a packet is already coming in, this line is supposed to
 270            avoid receiving a partial packet.
 271      */
 272     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 273 
 274     /* Enable RX dma */
 275     wrtscc(lp->cardbase, cmd, R1,
 276       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 277 
 278     restore_flags(flags);
 279 }
 280 
 281 static void setup_tx_dma(struct pi_local *lp, int length)
     /* [previous][next][first][last][top][bottom][index][help] */
 282 {
 283     unsigned long dma_abs;
 284     unsigned long flags;
 285     unsigned long dmachan;
 286 
 287     save_flags(flags);
 288     cli();
 289 
 290     dmachan = lp->dmachan;
 291     dma_abs = (unsigned long) (lp->txdmabuf);
 292 
 293     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 294         panic("PI: TX buffer violates DMA boundary!");
 295 
 296     disable_dma(dmachan);
 297     /* Set DMA mode register to single transfers, incrementing address,
 298      *  no auto init, reads
 299      */
 300     set_dma_mode(dmachan, DMA_MODE_WRITE);
 301     clear_dma_ff(dmachan);
 302     set_dma_addr(dmachan, dma_abs);
 303     /* output byte count */
 304     set_dma_count(dmachan, length);
 305 
 306     restore_flags(flags);
 307 }
 308 
 309 static void tdelay(struct pi_local *lp, int time)
     /* [previous][next][first][last][top][bottom][index][help] */
 310 {
 311     int port;
 312     unsigned int t1;
 313     unsigned char sc;
 314 
 315     if (lp->base & 2) {         /* If A channel */
 316         sc = SC1;
 317         t1 = time;
 318         port = lp->cardbase + TMR1;
 319     } else {
 320         sc = SC2;
 321         t1 = 10 * time;         /* 10s of milliseconds for the B channel */
 322         port = lp->cardbase + TMR2;
 323         wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
 324     }
 325 
 326     /* Setup timer sc */
 327     outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
 328 
 329     /* times 2 to make millisecs */
 330     outb_p((t1 << 1) & 0xFF, port);
 331     outb_p((t1 >> 7) & 0xFF, port);
 332 
 333     /* Enable correct int for timeout */
 334     wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
 335     wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
 336 }
 337 
 338 static void free_p(struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 339 {
 340         dev_kfree_skb(skb, FREE_WRITE);
 341 }
 342 
 343 static void a_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 344 {
 345     int cmd;
 346     unsigned long flags;
 347 
 348     save_flags(flags);
 349     cli();
 350 
 351     cmd = CTL + lp->base;
 352 
 353     switch (lp->tstate) {
 354     case IDLE:
 355         /* Transmitter idle. Find a frame for transmission */
 356         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 357             rts(lp, OFF);
 358             restore_flags(flags);
 359             return;
 360         }
 361         /* If a buffer to send, we drop thru here */
 362     case DEFER:
 363         /* we may have deferred prev xmit attempt */
 364         /* Check DCD - debounce it
 365          * See Intel Microcommunications Handbook, p2-308
 366          */
 367         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 368         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 369         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 370             lp->tstate = DEFER;
 371             tdelay(lp, 100);
 372             /* defer until DCD transition or timeout */
 373             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 374             restore_flags(flags);
 375             return;
 376         }
 377         if (random() > lp->persist) {
 378             lp->tstate = DEFER;
 379             tdelay(lp, lp->slotime);
 380             restore_flags(flags);
 381             return;
 382         }
 383         /* Assert RTS early minimize collision window */
 384         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 385         rts(lp, ON);            /* Transmitter on */
 386         lp->tstate = ST_TXDELAY;
 387         tdelay(lp, lp->txdelay);
 388         restore_flags(flags);
 389         return;
 390     default:
 391         break;
 392     }                           /* end switch(lp->state) */
 393 
 394     restore_flags(flags);
 395 }                               /*a_txint */
 396 
 397 static void a_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 398 {
 399     unsigned long flags;
 400     int cmd;
 401     char st;
 402     int length;
 403 
 404     save_flags(flags);
 405     cli();                      /* disable interrupts */
 406 
 407     st = rdscc(lp->cardbase, lp->base + CTL, R0);       /* Fetch status */
 408 
 409     /* reset external status latch */
 410     wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
 411     cmd = lp->base + CTL;
 412 
 413     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
 414         setup_rx_dma(lp);
 415         lp->rstate = ACTIVE;
 416     }
 417     switch (lp->tstate) {
 418     case ACTIVE:
 419         free_p(lp->sndbuf);
 420         lp->sndbuf = NULL;
 421         lp->tstate = FLAGOUT;
 422         tdelay(lp, lp->squeldelay);
 423         break;
 424     case FLAGOUT:
 425         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 426             /* Nothing to send - return to receive mode */
 427             lp->tstate = IDLE;
 428             rts(lp, OFF);
 429             restore_flags(flags);
 430             return;
 431         }
 432         /* NOTE - fall through if more to send */
 433     case ST_TXDELAY:
 434         /* Disable DMA chan */
 435         disable_dma(lp->dmachan);
 436 
 437         /* Set up for TX dma */
 438         wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 439 
 440 
 441         /* Get all chars */
 442         /* Strip KISS control byte */
 443         length = lp->sndbuf->len - 1;
 444         memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
 445 
 446 
 447         /* Setup DMA controller for tx */
 448         setup_tx_dma(lp, length);
 449 
 450         /* select transmit interrupts to enable */
 451         /* Allow DMA on chan */
 452         enable_dma(lp->dmachan);
 453 
 454         /* reset CRC, Txint pend*/
 455         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
 456 
 457         /* allow Underrun int only */
 458         wrtscc(lp->cardbase, cmd, R15, TxUIE);
 459 
 460         /* Enable TX DMA */
 461         wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
 462 
 463         /* Send CRC on underrun */
 464         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
 465 
 466 
 467         /* packet going out now */
 468         lp->tstate = ACTIVE;
 469         break;
 470     case DEFER:
 471         /* we have deferred prev xmit attempt
 472          * See Intel Microcommunications Handbook, p2-308
 473          */
 474         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 475         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 476         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 477             lp->tstate = DEFER;
 478             tdelay(lp, 100);
 479             /* Defer until dcd transition or 100mS timeout */
 480             wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
 481             restore_flags(flags);
 482             return;
 483         }
 484         if (random() > lp->persist) {
 485             lp->tstate = DEFER;
 486             tdelay(lp, lp->slotime);
 487             restore_flags(flags);
 488             return;
 489         }
 490         /* Assert RTS early minimize collision window */
 491         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 492         rts(lp, ON);            /* Transmitter on */
 493         lp->tstate = ST_TXDELAY;
 494         tdelay(lp, lp->txdelay);
 495         restore_flags(flags);
 496         return;
 497     }                           /* switch(lp->tstate) */
 498 
 499     restore_flags(flags);
 500 }                               /* a_exint() */
 501 
 502 /* Receive interrupt handler for the A channel
 503  */
 504 static void a_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 505 {
 506     unsigned long flags;
 507     int cmd;
 508     int bytecount;
 509     char rse;
 510     struct sk_buff *skb;
 511     int sksize, pkt_len;
 512     struct mbuf *cur_buf;
 513 
 514     save_flags(flags);
 515     cli();                      /* disable interrupts */
 516     cmd = lp->base + CTL;
 517 
 518     rse = rdscc(lp->cardbase, cmd, R1); /* Get special condition bits from R1 */
 519     if (rse & Rx_OVR)
 520         lp->rstate = RXERROR;
 521 
 522     if (rse & END_FR) {
 523         /* If end of frame */
 524         /* figure length of frame from 8237 */
 525         clear_dma_ff(lp->dmachan);
 526         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
 527 
 528         if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
 529             if ((bytecount >= 10) && (rse & CRC_ERR)) {
 530                 lp->stats.rx_crc_errors++;
 531             }
 532             if (lp->rstate == RXERROR) {
 533                 lp->stats.rx_errors++;
 534                 lp->stats.rx_over_errors++;
 535             }
 536             /* Reset buffer pointers */
 537             lp->rstate = ACTIVE;
 538             setup_rx_dma(lp);
 539         } else {
 540             /* Here we have a valid frame */
 541             /* Toss 2 crc bytes , add one for KISS */
 542             pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
 543 
 544             /* Get buffer for next frame */
 545             cur_buf = lp->rcvbuf;
 546             switchbuffers(lp);
 547             setup_rx_dma(lp);
 548 
 549 
 550             /* Malloc up new buffer. */
 551             sksize = pkt_len;
 552 
 553             skb = alloc_skb(sksize, GFP_ATOMIC);
 554             if (skb == NULL) {
 555                 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 556                 lp->stats.rx_dropped++;
 557                 restore_flags(flags);
 558                 return;
 559             }
 560             skb->len = (unsigned long) pkt_len;
 561             skb->dev = dev;
 562 
 563             /* KISS kludge -  prefix with a 0 byte */
 564             skb->data[0] = 0;
 565             /* 'skb->data' points to the start of sk_buff data area. */
 566             memcpy(&skb->data[1], (char *) cur_buf->data,
 567                    pkt_len - 1);
 568             skb->protocol=ntohs(ETH_P_AX25);
 569             netif_rx(skb);
 570             lp->stats.rx_packets++;
 571         }                       /* end good frame */
 572     }                           /* end EOF check */
 573     wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
 574     restore_flags(flags);
 575 }
 576 
 577 static void b_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 578 {
 579     unsigned long flags;
 580     int cmd;
 581     char rse;
 582     struct sk_buff *skb;
 583     int sksize;
 584     int pkt_len;
 585 
 586     save_flags(flags);
 587     cli();                      /* disable interrupts */
 588     cmd = CTL + lp->base;
 589 
 590     rse = rdscc(lp->cardbase, cmd, R1); /* get status byte from R1 */
 591 
 592     if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
 593         /* there is a char to be stored
 594          * read special condition bits before reading the data char
 595          */
 596         if (rse & Rx_OVR) {
 597             /* Rx overrun - toss buffer */
 598             /* reset buffer pointers */
 599             lp->rcp = lp->rcvbuf->data;
 600             lp->rcvbuf->cnt = 0;
 601 
 602             lp->rstate = RXERROR;       /* set error flag */
 603             lp->stats.rx_errors++;
 604             lp->stats.rx_over_errors++;
 605         } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
 606             /* Too large -- toss buffer */
 607             /* reset buffer pointers */
 608             lp->rcp = lp->rcvbuf->data;
 609             lp->rcvbuf->cnt = 0;
 610             lp->rstate = TOOBIG;/* when set, chars are not stored */
 611         }
 612         /* ok, we can store the received character now */
 613         if (lp->rstate == ACTIVE) {     /* If no errors... */
 614             *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
 615             lp->rcvbuf->cnt++;  /* bump count */
 616         } else {
 617             /* got to empty FIFO */
 618             (void) rdscc(lp->cardbase, cmd, R8);
 619             wrtscc(lp->cardbase, cmd, R0, ERR_RES);     /* reset err latch */
 620             lp->rstate = ACTIVE;
 621         }
 622     }
 623     if (rse & END_FR) {
 624         /* END OF FRAME -- Make sure Rx was active */
 625         if (lp->rcvbuf->cnt > 0) {
 626             if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
 627                 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
 628                     lp->stats.rx_crc_errors++;
 629                 }
 630                 lp->rcp = lp->rcvbuf->data;
 631                 lp->rcvbuf->cnt = 0;
 632             } else {
 633                 /* Here we have a valid frame */
 634                 pkt_len = lp->rcvbuf->cnt -= 2; /* Toss 2 crc bytes */
 635                 pkt_len += 1;   /* Make room for KISS control byte */
 636 
 637                 /* Malloc up new buffer. */
 638                 sksize = pkt_len;
 639                 skb = alloc_skb(sksize, GFP_ATOMIC);
 640                 if (skb == NULL) {
 641                     printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 642                     lp->stats.rx_dropped++;
 643                     restore_flags(flags);
 644                     return;
 645                 }
 646                 skb->len = pkt_len;
 647                 skb->dev = dev;
 648 
 649                 /* KISS kludge -  prefix with a 0 byte */
 650                 skb->data[0] = 0;
 651                 /* 'skb->data' points to the start of sk_buff data area. */
 652                 memcpy(&skb->data[1], lp->rcvbuf->data, pkt_len - 1);
 653                 skb->protocol=ntohs(ETH_P_AX25);
 654                 netif_rx(skb);
 655                 lp->stats.rx_packets++;
 656                 /* packet queued - initialize buffer for next frame */
 657                 lp->rcp = lp->rcvbuf->data;
 658                 lp->rcvbuf->cnt = 0;
 659 
 660             }                   /* end good frame queued */
 661         }                       /* end check for active receive upon EOF */
 662         lp->rstate = ACTIVE;    /* and clear error status */
 663     }                           /* end EOF check */
 664     restore_flags(flags);
 665 }
 666 
 667 
 668 static void b_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 669 {
 670     unsigned long flags;
 671     int cmd;
 672     unsigned char c;
 673 
 674     save_flags(flags);
 675     cli();
 676     cmd = CTL + lp->base;
 677 
 678     switch (lp->tstate) {
 679     case CRCOUT:
 680         lp->tstate = FLAGOUT;
 681         tdelay(lp, lp->squeldelay);
 682         restore_flags(flags);
 683         return;
 684     case IDLE:
 685         /* Transmitter idle. Find a frame for transmission */
 686         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 687             /* Nothing to send - return to receive mode
 688              * Tx OFF now - flag should have gone
 689              */
 690             rts(lp, OFF);
 691          
 692             restore_flags(flags);
 693             return;
 694         }
 695         lp->txptr = lp->sndbuf->data;
 696         lp->txptr++;            /* Ignore KISS control byte */
 697         lp->txcnt = (int) lp->sndbuf->len - 1;
 698         /* If a buffer to send, we drop thru here */
 699     case DEFER:         /* we may have deferred prev xmit attempt */
 700         /* Check DCD - debounce it */
 701         /* See Intel Microcommunications Handbook, p2-308 */
 702         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 703         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 704         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 705             lp->tstate = DEFER;
 706             tdelay(lp, 100);
 707             /* defer until DCD transition or timeout */
 708             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 709             restore_flags(flags);
 710             return;
 711         }
 712         if (random() > lp->persist) {
 713             lp->tstate = DEFER;
 714             tdelay(lp, lp->slotime);
 715             restore_flags(flags);
 716             return;
 717         }
 718         rts(lp, ON);            /* Transmitter on */
 719         lp->tstate = ST_TXDELAY;
 720         tdelay(lp, lp->txdelay);
 721         restore_flags(flags);
 722         return;
 723 
 724     case ACTIVE:
 725         /* Here we are actively sending a frame */
 726         if (lp->txcnt--) {
 727             c = *lp->txptr++;
 728             /* next char is gone */
 729             wrtscc(lp->cardbase, cmd, R8, c);
 730             /* stuffing a char satisfies Interrupt condition */
 731         } else {
 732             /* No more to send */
 733             free_p(lp->sndbuf);
 734             lp->sndbuf = NULL;
 735             if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
 736                 /* Did we underrun? */
 737                 /* unexpected underrun */
 738                 lp->stats.tx_errors++;
 739                 lp->stats.tx_fifo_errors++;
 740                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 741                 lp->tstate = FLAGOUT;
 742                 tdelay(lp, lp->squeldelay);
 743                 restore_flags(flags);
 744                 return;
 745             }
 746             lp->tstate = UNDERRUN;      /* Now we expect to underrun */
 747             /* Send flags on underrun */
 748             if (lp->speed) {    /* If internally clocked */
 749                 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
 750             } else {
 751                 wrtscc(lp->cardbase, cmd, R10, CRCPS);
 752             }
 753             wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);    /* reset Tx Int Pend */
 754         }
 755         restore_flags(flags);
 756         return;                 /* back to wait for interrupt */
 757     }                           /* end switch */
 758     restore_flags(flags);
 759 }
 760 
 761 /* Pi SIO External/Status interrupts (for the B channel)
 762  * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
 763  * Receiver automatically goes to Hunt on an abort.
 764  *
 765  * If the Tx Underrun interrupt hits, change state and
 766  * issue a reset command for it, and return.
 767  */
 768 static void b_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 769 {
 770     unsigned long flags;
 771     char st;
 772     int cmd;
 773     char c;
 774 
 775     cmd = CTL + lp->base;
 776     save_flags(flags);
 777     cli();                      /* disable interrupts */
 778     st = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
 779     /* reset external status latch */
 780     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 781 
 782 
 783     switch (lp->tstate) {
 784     case ACTIVE:                /* Unexpected underrun */
 785         free_p(lp->sndbuf);
 786         lp->sndbuf = NULL;
 787         wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 788         lp->tstate = FLAGOUT;
 789         lp->stats.tx_errors++;
 790         lp->stats.tx_fifo_errors++;
 791         tdelay(lp, lp->squeldelay);
 792         restore_flags(flags);
 793         return;
 794     case UNDERRUN:
 795         lp->tstate = CRCOUT;
 796         restore_flags(flags);
 797         return;
 798     case FLAGOUT:
 799         /* Find a frame for transmission */
 800         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 801             /* Nothing to send - return to receive mode
 802              * Tx OFF now - flag should have gone
 803              */
 804             rts(lp, OFF);
 805             lp->tstate = IDLE;
 806             restore_flags(flags);
 807             return;
 808         }
 809         lp->txptr = lp->sndbuf->data;
 810         lp->txptr++;            /* Ignore KISS control byte */
 811         lp->txcnt = (int) lp->sndbuf->len - 1;
 812         /* Get first char to send */
 813         lp->txcnt--;
 814         c = *lp->txptr++;
 815         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 816 
 817         /* Send abort on underrun */
 818         if (lp->speed) {        /* If internally clocked */
 819             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 820         } else {
 821             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 822         }
 823 
 824         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 825         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 826 
 827 #ifdef STUFF2
 828         /* stuff an extra one if we can */
 829         if (lp->txcnt) {
 830             lp->txcnt--;
 831             c = *lp->txptr++;
 832             /* Wait for tx buffer empty */
 833             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 834                 ;   
 835             wrtscc(lp->cardbase, cmd, R8, c);
 836         }
 837 #endif
 838 
 839         /* select transmit interrupts to enable */
 840 
 841         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 842         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 843         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);       /* Tx/Ext ints */
 844 
 845         lp->tstate = ACTIVE;    /* char going out now */
 846         restore_flags(flags);
 847         return;
 848 
 849     case DEFER:
 850         /* Check DCD - debounce it
 851          * See Intel Microcommunications Handbook, p2-308
 852          */
 853         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 854         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 855         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 856             lp->tstate = DEFER;
 857             tdelay(lp, 100);
 858             /* defer until DCD transition or timeout */
 859             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 860             restore_flags(flags);
 861             return;
 862         }
 863         if (random() > lp->persist) {
 864             lp->tstate = DEFER;
 865             tdelay(lp, lp->slotime);
 866             restore_flags(flags);
 867             return;
 868         }
 869         rts(lp, ON);            /* Transmitter on */
 870         lp->tstate = ST_TXDELAY;
 871         tdelay(lp, lp->txdelay);
 872         restore_flags(flags);
 873         return;
 874 
 875     case ST_TXDELAY:
 876 
 877         /* Get first char to send */
 878         lp->txcnt--;
 879         c = *lp->txptr++;
 880         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 881 
 882         /* Send abort on underrun */
 883         if (lp->speed) {        /* If internally clocked */
 884             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 885         } else {
 886             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 887         }
 888 
 889         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 890         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 891 
 892 #ifdef STUFF2
 893         /* stuff an extra one if we can */
 894         if (lp->txcnt) {
 895             lp->txcnt--;
 896             c = *lp->txptr++;
 897             /* Wait for tx buffer empty */
 898             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 899                 ;   
 900             wrtscc(lp->cardbase, cmd, R8, c);
 901         }
 902 #endif
 903 
 904         /* select transmit interrupts to enable */
 905 
 906         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 907         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 908         /* Tx/Extern ints on */
 909         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
 910 
 911         lp->tstate = ACTIVE;    /* char going out now */
 912         restore_flags(flags);
 913         return;
 914     }
 915 
 916     /* Receive Mode only
 917      * This triggers when hunt mode is entered, & since an ABORT
 918      * automatically enters hunt mode, we use that to clean up
 919      * any waiting garbage
 920      */
 921     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
 922         (void) rdscc(lp->cardbase, cmd, R8);
 923         (void) rdscc(lp->cardbase, cmd, R8);
 924         (void) rdscc(lp->cardbase, cmd, R8);
 925         lp->rcp = lp->rcvbuf->data;
 926         lp->rcvbuf->cnt = 0;    /* rewind on DCD transition */
 927     }
 928     restore_flags(flags);
 929 }
 930 
 931 /* Probe for a PI card. */
 932 /* This routine also initializes the timer chip */
 933 
 934 static int hw_probe(int ioaddr)
     /* [previous][next][first][last][top][bottom][index][help] */
 935 {
 936     int time = 1000;            /* Number of milliseconds for test */
 937     unsigned long start_time, end_time;
 938 
 939     int base, tmr0, tmr1, tmrcmd;
 940     int a = 1;
 941     int b = 1;
 942 
 943     base = ioaddr & 0x3f0;
 944     tmr0 = TMR0 + base;
 945     tmr1 = TMR1 + base;
 946     tmrcmd = TMRCMD + base;
 947 
 948     /* Set up counter chip timer 0 for 500 uS period square wave */
 949     /* assuming a 3.68 mhz clock for now */
 950     outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 951     outb_p(922 & 0xFF, tmr0);
 952     outb_p(922 >> 8, tmr0);
 953 
 954     /* Setup timer control word for timer 1*/
 955     outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
 956     outb_p((time << 1) & 0xFF, tmr1);
 957     outb_p((time >> 7) & 0XFF, tmr1);
 958 
 959     /* wait until counter reg is loaded */
 960     do {
 961         /* Latch count for reading */
 962         outb_p(SC1, tmrcmd);
 963         a = inb_p(tmr1);
 964         b = inb_p(tmr1);
 965     } while (b == 0);
 966     start_time = jiffies;
 967     while (b != 0) {
 968         /* Latch count for reading */
 969         outb_p(SC1, tmrcmd);
 970         a = inb_p(tmr1);
 971         b = inb_p(tmr1);
 972         end_time = jiffies;
 973         /* Don't wait forever - there may be no card here */
 974         if ((end_time - start_time) > 200)
 975             return 0;           /* No card found */
 976     }
 977     end_time = jiffies;
 978     /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
 979     if ((end_time - start_time) > 65) {
 980         return (1);             /* PI card found */
 981     } else {
 982         /* Faster crystal - tmr0 needs adjusting */
 983         /* Set up counter chip */
 984         /* 500 uS square wave */
 985         outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 986         outb_p(1844 & 0xFF, tmr0);
 987         outb_p(1844 >> 8, tmr0);
 988         return (2);             /* PI2 card found */
 989     }
 990 }
 991 
 992 static void rts(struct pi_local *lp, int x)
     /* [previous][next][first][last][top][bottom][index][help] */
 993 {
 994     int tc;
 995     long br;
 996     int cmd;
 997     int dummy;
 998 
 999     /* assumes interrupts are off */
1000     cmd = CTL + lp->base;
1001 
1002     /* Reprogram BRG and turn on transmitter to send flags */
1003     if (x == ON) {              /* Turn Tx ON and Receive OFF */
1004         /* Exints off first to avoid abort int */
1005         wrtscc(lp->cardbase, cmd, R15, 0);
1006         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Rx off */
1007         lp->rstate = IDLE;
1008         if (cmd & 2) {          /* if channel a */
1009             /* Set up for TX dma */
1010             wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1011         } else {
1012             wrtscc(lp->cardbase, cmd, R1, 0);   /* No interrupts */
1013         }
1014 
1015         if (!lp->clockmode) {
1016             if (lp->speed) {    /* if internally clocked */
1017                 br = lp->speed; /* get desired speed */
1018                 tc = (lp->xtal / br) - 2;       /* calc 1X BRG divisor */
1019                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1020                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1021             }
1022         }
1023         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1024         /* Transmitter now on */
1025     } else {                    /* Tx OFF and Rx ON */
1026         lp->tstate = IDLE;
1027         wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);       /*  TX off */
1028 
1029         if (!lp->clockmode) {
1030             if (lp->speed) {    /* if internally clocked */
1031                 /* Reprogram BRG for 32x clock for receive DPLL */
1032                 /* BRG off, keep Pclk source */
1033                 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1034                 br = lp->speed; /* get desired speed */
1035                 /* calc 32X BRG divisor */
1036                 tc = ((lp->xtal / 32) / br) - 2;
1037                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1038                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1039                 /* SEARCH mode, BRG source */
1040                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1041                 /* Enable the BRG */
1042                 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1043             }
1044         }
1045         /* Flush rx fifo */
1046         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Make sure rx is off */
1047         wrtscc(lp->cardbase, cmd, R0, ERR_RES); /* reset err latch */
1048         dummy = rdscc(lp->cardbase, cmd, R1);   /* get status byte from R1 */
1049         (void) rdscc(lp->cardbase, cmd, R8);
1050         (void) rdscc(lp->cardbase, cmd, R8);
1051 
1052         (void) rdscc(lp->cardbase, cmd, R8);
1053 
1054         /* Now, turn on the receiver and hunt for a flag */
1055         wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1056         lp->rstate = ACTIVE;    /* Normal state */
1057 
1058         if (cmd & 2) {          /* if channel a */
1059             setup_rx_dma(lp);
1060         } else {
1061             /* reset buffer pointers */
1062             lp->rcp = lp->rcvbuf->data;
1063             lp->rcvbuf->cnt = 0;
1064             wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1065         }
1066         wrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
1067     }
1068 }
1069 
1070 /* Fill in the MAC-level header. */
1071 static int pi_header(unsigned char *buff, struct device *dev, unsigned short type,
     /* [previous][next][first][last][top][bottom][index][help] */
1072              void *daddr, void *saddr, unsigned len, struct sk_buff *skb)
1073 {
1074     return ax25_encapsulate(buff, dev, type, daddr, saddr, len, skb);
1075 }
1076 
1077 /* Rebuild the MAC-level header. */
1078 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /* [previous][next][first][last][top][bottom][index][help] */
1079                              struct sk_buff *skb)
1080 {
1081     return ax25_rebuild_header(buff, dev, raddr, skb);
1082 }
1083 
1084 static void scc_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1085 {
1086     unsigned long flags;
1087     struct pi_local *lp = (struct pi_local *) dev->priv;
1088 
1089     int tc;
1090     long br;
1091     register int cmd;
1092 
1093     /* Initialize 8530 channel for SDLC operation */
1094 
1095     cmd = CTL + lp->base;
1096     save_flags(flags);
1097     cli();
1098 
1099     switch (cmd & CHANA) {
1100     case CHANA:
1101         wrtscc(lp->cardbase, cmd, R9, CHRA);    /* Reset channel A */
1102         wrtscc(lp->cardbase, cmd, R2, 0xff);    /* Initialize interrupt vector */
1103         break;
1104     default:
1105         wrtscc(lp->cardbase, cmd, R9, CHRB);    /* Reset channel B */
1106         break;
1107     }
1108 
1109     /* Deselect all Rx and Tx interrupts */
1110     wrtscc(lp->cardbase, cmd, R1, 0);
1111 
1112     /* Turn off external interrupts (like CTS/CD) */
1113     wrtscc(lp->cardbase, cmd, R15, 0);
1114 
1115     /* X1 clock, SDLC mode */
1116     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1117 
1118     /* Tx/Rx parameters */
1119     if (lp->speed) {            /* Use internal clocking */
1120         wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1121         if (!lp->clockmode)
1122             /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1123             wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1124         else
1125             /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1126             wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1127     } else {                    /* Use external clocking */
1128         wrtscc(lp->cardbase, cmd, R10, CRCPS);
1129         /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1130         wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1131     }
1132 
1133     /* Null out SDLC start address */
1134     wrtscc(lp->cardbase, cmd, R6, 0);
1135 
1136     /* SDLC flag */
1137     wrtscc(lp->cardbase, cmd, R7, FLAG);
1138 
1139     /* Set up the Transmitter but don't enable it
1140      *  DTR, 8 bit TX chars only
1141      */
1142     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1143 
1144     /* Receiver initial setup */
1145     wrtscc(lp->cardbase, cmd, R3, Rx8); /* 8 bits/char */
1146 
1147     /* Setting up BRG now - turn it off first */
1148     wrtscc(lp->cardbase, cmd, R14, BRSRC);      /* BRG off, keep Pclk source */
1149 
1150     /* set the 32x time constant for the BRG in Receive mode */
1151 
1152     if (lp->speed) {
1153         br = lp->speed;         /* get desired speed */
1154         tc = ((lp->xtal / 32) / br) - 2;        /* calc 32X BRG divisor */
1155     } else {
1156         tc = 14;
1157     }
1158 
1159     wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
1160     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);   /* upper byte */
1161 
1162     /* Following subroutine sets up and ENABLES the receiver */
1163     rts(lp, OFF);               /* TX OFF and RX ON */
1164 
1165     if (lp->speed) {
1166         /* DPLL frm BRG, BRG src PCLK */
1167         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1168     } else {
1169         /* DPLL frm rtxc,BRG src PCLK */
1170         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1171     }
1172     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);     /* SEARCH mode, keep BRG src */
1173     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
1174 
1175     if (!(cmd & 2))             /* if channel b */
1176         wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1177 
1178     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
1179 
1180     /* Now, turn on the receiver and hunt for a flag */
1181     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1182 
1183     restore_flags(flags);
1184 }
1185 
1186 static void chipset_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1187 {
1188     int cardbase;
1189     unsigned long flags;
1190 
1191     cardbase = dev->base_addr & 0x3f0;
1192 
1193     save_flags(flags);
1194     cli();
1195     wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES); /* Hardware reset */
1196     /* Disable interrupts with master interrupt ctrl reg */
1197     wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1198     restore_flags(flags);
1199 
1200 }
1201 
1202 
1203 unsigned long pi_init(unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
1204 {
1205     int *port;
1206     int ioaddr = 0;
1207     int card_type = 0;
1208     int ports[] =
1209     {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1210 
1211     printk(version);
1212 
1213     /* Only one card supported for now */
1214     for (port = &ports[0]; *port && !card_type; port++) {
1215         ioaddr = *port;
1216 
1217         if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1218             printk("PI: Probing for card at address %#3x\n",ioaddr);
1219             card_type = hw_probe(ioaddr);
1220         }
1221     }
1222 
1223     switch (card_type) {
1224     case 1:
1225         printk("PI: Found a PI card at address %#3x\n", ioaddr);
1226         break;
1227     case 2:
1228         printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1229         break;
1230     default:
1231         printk("PI: ERROR: No card found\n");
1232         return mem_start;
1233     }
1234 
1235     /* Link a couple of device structures into the chain */
1236     /* For the A port */
1237     /* Allocate space for 4 buffers even though we only need 3,
1238        because one of them may cross a DMA page boundary and
1239        be rejected by get_dma_buffer().
1240     */
1241     register_netdev(&pi0a);
1242     
1243     pi0a.priv=(void *)mem_start;
1244     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1245                          + 8;   /* for alignment */
1246                         
1247     pi0a.dma = PI_DMA;
1248     pi0a.base_addr = ioaddr + 2;
1249     pi0a.irq = 0;
1250 
1251     /* And the B port */
1252     register_netdev(&pi0b);
1253     pi0b.base_addr = ioaddr;
1254     pi0b.irq = 0;
1255     pi0b.priv=(void *)mem_start;
1256     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1257                          + 8;   /* for alignment */
1258 
1259     /* Now initialize them */
1260     pi_probe(&pi0a, card_type);
1261     pi_probe(&pi0b, card_type);
1262 
1263     pi0b.irq = pi0a.irq;        /* IRQ is shared */
1264     
1265     return mem_start;
1266 }
1267 
1268 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
     /* [previous][next][first][last][top][bottom][index][help] */
1269 {
1270     if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1271         return 1;
1272     else
1273         return 0;
1274 }
1275 
1276 static int pi_set_mac_address(struct device *dev, void *addr)
     /* [previous][next][first][last][top][bottom][index][help] */
1277 {
1278     memcpy(dev->dev_addr, addr, 7);     /* addr is an AX.25 shifted ASCII */
1279     return 0;                   /* mac address */
1280 }
1281 
1282 /* Allocate a buffer which does not cross a DMA page boundary */
1283 static char *
1284 get_dma_buffer(unsigned long *mem_ptr)
     /* [previous][next][first][last][top][bottom][index][help] */
1285 {
1286     char *ret;
1287 
1288     ret = (char *)*mem_ptr;
1289 
1290     if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1291         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1292         ret = (char *)*mem_ptr;
1293     }
1294     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1295     return (ret);
1296 }
1297 
1298 static int pi_probe(struct device *dev, int card_type)
     /* [previous][next][first][last][top][bottom][index][help] */
1299 {
1300     short ioaddr;
1301     struct pi_local *lp;
1302     int i;
1303     unsigned long flags;
1304     unsigned long mem_ptr;
1305 
1306     ioaddr = dev->base_addr;
1307 
1308     /* Initialize the device structure. */
1309     /* Must be done before chipset_init */
1310     /* Make certain the data structures used by the PI2 are aligned. */
1311     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1312     lp = (struct pi_local *) dev->priv;
1313 
1314     memset(dev->priv, 0, sizeof(struct pi_local));
1315 
1316     /* Allocate some buffers which do not cross DMA page boundaries */
1317     mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1318     lp->txdmabuf = get_dma_buffer(&mem_ptr);
1319     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1320     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1321 
1322     /* Initialize rx buffer */
1323     lp->rcvbuf = lp->rxdmabuf1;
1324     lp->rcp = lp->rcvbuf->data;
1325     lp->rcvbuf->cnt = 0;
1326 
1327     /* Initialize the transmit queue head structure */
1328     skb_queue_head_init(&lp->sndq);
1329 
1330     /* These need to be initialized before scc_init is called. */
1331     if (card_type == 1)
1332         lp->xtal = (unsigned long) SINGLE / 2;
1333     else
1334         lp->xtal = (unsigned long) DOUBLE / 2;
1335     lp->base = dev->base_addr;
1336     lp->cardbase = dev->base_addr & 0x3f0;
1337     if (dev->base_addr & CHANA) {
1338         lp->speed = DEF_A_SPEED;
1339         /* default channel access Params */
1340         lp->txdelay = DEF_A_TXDELAY;
1341         lp->persist = DEF_A_PERSIST;
1342         lp->slotime = DEF_A_SLOTIME;
1343         lp->squeldelay = DEF_A_SQUELDELAY;
1344         lp->clockmode = DEF_A_CLOCKMODE;
1345 
1346     } else {
1347         lp->speed = DEF_B_SPEED;
1348         /* default channel access Params */
1349         lp->txdelay = DEF_B_TXDELAY;
1350         lp->persist = DEF_B_PERSIST;
1351         lp->slotime = DEF_B_SLOTIME;
1352         lp->squeldelay = DEF_B_SQUELDELAY;
1353         lp->clockmode = DEF_B_CLOCKMODE;
1354     }
1355     lp->bufsiz = DMA_BUFF_SIZE;
1356     lp->tstate = IDLE;
1357 
1358     chipset_init(dev);
1359 
1360     if (dev->base_addr & CHANA) {       /* Do these things only for the A port */
1361         /* Note that a single IRQ services 2 devices (A and B channels) */
1362 
1363         lp->dmachan = dev->dma;
1364         if (lp->dmachan < 1 || lp->dmachan > 3)
1365             printk("PI: DMA channel %d out of range\n", lp->dmachan);
1366 
1367         /* chipset_init() was already called */
1368 
1369         if (dev->irq < 2) {
1370             autoirq_setup(0);
1371             save_flags(flags);
1372             cli();
1373             wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1374             /* enable PI card interrupts */
1375             wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1376             restore_flags(flags);
1377             /* request a timer interrupt for 1 mS hence */
1378             tdelay(lp, 1);
1379             /* 20 "jiffies" should be plenty of time... */
1380             dev->irq = autoirq_report(20);
1381             if (!dev->irq) {
1382                 printk(". Failed to detect IRQ line.\n");
1383             }
1384             save_flags(flags);
1385             cli();
1386             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);     /* Hardware reset */
1387             /* Disable interrupts with master interrupt ctrl reg */
1388             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1389             restore_flags(flags);
1390         }
1391 
1392         printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1393                dev->irq, dev->dma);
1394 
1395         /* This board has jumpered interrupts. Snarf the interrupt vector
1396                    now.  There is no point in waiting since no other device can use
1397                    the interrupt, and this marks the 'irqaction' as busy. */
1398         {
1399             int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1400             if (irqval) {
1401                 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1402                        dev->irq, irqval);
1403                 return EAGAIN;
1404             }
1405         }
1406 
1407         /* Grab the region */
1408         snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1409 
1410 
1411     }                           /* Only for A port */
1412     dev->open = pi_open;
1413     dev->stop = pi_close;
1414     dev->do_ioctl = pi_ioctl;
1415     dev->hard_start_xmit = pi_send_packet;
1416     dev->get_stats = pi_get_stats;
1417 
1418     /* Fill in the fields of the device structure */
1419     for (i = 0; i < DEV_NUMBUFFS; i++)
1420         skb_queue_head_init(&dev->buffs[i]);
1421 
1422 
1423     dev->hard_header = pi_header;
1424     dev->rebuild_header = pi_rebuild_header;
1425     dev->set_mac_address = pi_set_mac_address;
1426 
1427     dev->type = AF_AX25;        /* AF_AX25 device */
1428     dev->hard_header_len = 17;  /* We don't do digipeaters */
1429     dev->mtu = 1500;            /* eth_mtu is the default */
1430     dev->addr_len = 7;          /* sizeof an ax.25 address */
1431     for (i = 0; i < ETH_ALEN; i++) {
1432         dev->broadcast[i] = 0xff;
1433     }
1434     memcpy(dev->broadcast, ax25_bcast, 7);
1435     memcpy(dev->dev_addr, ax25_test, 7);
1436 
1437     /* New-style flags. */
1438     dev->flags = 0;
1439     dev->family = AF_INET;
1440     dev->pa_addr = 0;
1441     dev->pa_brdaddr = 0;
1442     dev->pa_mask = 0;
1443     dev->pa_alen = sizeof(unsigned long);
1444 
1445     return 0;
1446 }
1447 
1448 /* Open/initialize the board.  This is called (in the current kernel)
1449    sometime after booting when the 'ifconfig' program is run.
1450 
1451    This routine should set everything up anew at each open, even
1452    registers that "should" only need to be set once at boot, so that
1453    there is non-reboot way to recover if something goes wrong.
1454    */
1455 static int pi_open(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1456 {
1457     unsigned long flags;
1458     static first_time = 1;
1459 
1460     struct pi_local *lp = (struct pi_local *) dev->priv;
1461 
1462     if (dev->base_addr & 2) {   /* if A channel */
1463         if (first_time) {
1464             if (request_dma(dev->dma,"pi2")) {
1465                 free_irq(dev->irq);
1466                 return -EAGAIN;
1467             }
1468             irq2dev_map[dev->irq] = dev;
1469         }
1470         /* Reset the hardware here. */
1471         chipset_init(dev);
1472     }
1473     lp->tstate = IDLE;
1474 
1475     if (dev->base_addr & 2) {   /* if A channel */
1476         scc_init(dev);          /* Called once for each channel */
1477         scc_init(dev->next);
1478     }
1479     /* master interrupt enable */
1480     save_flags(flags);
1481     cli();
1482     wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1483     restore_flags(flags);
1484 
1485     lp->open_time = jiffies;
1486 
1487     dev->tbusy = 0;
1488     dev->interrupt = 0;
1489     dev->start = 1;
1490     first_time = 0;
1491     return 0;
1492 }
1493 
1494 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1495 {
1496     struct pi_local *lp = (struct pi_local *) dev->priv;
1497 
1498     /* If some higher layer thinks we've missed an tx-done interrupt
1499            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
1500            itself. */
1501     if (skb == NULL) {
1502         dev_tint(dev);
1503         return 0;
1504     }
1505     hardware_send_packet(lp, skb);
1506     dev->trans_start = jiffies;
1507 
1508     return 0;
1509 }
1510 
1511 /* The typical workload of the driver:
1512    Handle the network interface interrupts. */
1513 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
1514 {
1515 /*    int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1516     struct pi_local *lp;
1517     int st;
1518     unsigned long flags;
1519 
1520 /*    dev_b = dev_a->next;       Relies on the order defined in Space.c */
1521 
1522 #if 0
1523     if (dev_a == NULL) {
1524         printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1525         return;
1526     }
1527 #endif    
1528     /* Read interrupt status register (only valid from channel A)
1529      * Process all pending interrupts in while loop
1530      */
1531     lp = (struct pi_local *) pi0a.priv; /* Assume channel A */
1532     while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1533         if (st & CHBTxIP) {
1534             /* Channel B Transmit Int Pending */
1535             lp = (struct pi_local *) pi0b.priv;
1536             b_txint(lp);
1537         } else if (st & CHARxIP) {
1538             /* Channel A Rcv Interrupt Pending */
1539             lp = (struct pi_local *) pi0a.priv;
1540             a_rxint(&pi0a, lp);
1541         } else if (st & CHATxIP) {
1542             /* Channel A Transmit Int Pending */
1543             lp = (struct pi_local *) pi0a.priv;
1544             a_txint(lp);
1545         } else if (st & CHAEXT) {
1546             /* Channel A External Status Int */
1547             lp = (struct pi_local *) pi0a.priv;
1548             a_exint(lp);
1549         } else if (st & CHBRxIP) {
1550             /* Channel B Rcv Interrupt Pending */
1551             lp = (struct pi_local *) pi0b.priv;
1552             b_rxint(&pi0b, lp);
1553         } else if (st & CHBEXT) {
1554             /* Channel B External Status Int */
1555             lp = (struct pi_local *) pi0b.priv;
1556             b_exint(lp);
1557         }
1558         /* Reset highest interrupt under service */
1559         save_flags(flags);
1560         cli();
1561         wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1562         restore_flags(flags);
1563     }                           /* End of while loop on int processing */
1564     return;
1565 }
1566 
1567 /* The inverse routine to pi_open(). */
1568 static int pi_close(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1569 {
1570     unsigned long flags;
1571     struct pi_local *lp;
1572     struct sk_buff *ptr;
1573 
1574     save_flags(flags);
1575     cli();
1576 
1577     lp = (struct pi_local *) dev->priv;
1578     ptr = NULL;
1579 
1580     chipset_init(dev);          /* reset the scc */
1581     disable_dma(lp->dmachan);
1582 
1583     lp->open_time = 0;
1584 
1585     dev->tbusy = 1;
1586     dev->start = 0;
1587 
1588     /* Free any buffers left in the hardware transmit queue */
1589     while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1590         free_p(ptr);
1591 
1592     restore_flags(flags);
1593     return 0;
1594 }
1595 
1596 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /* [previous][next][first][last][top][bottom][index][help] */
1597 {
1598     unsigned long flags;
1599     struct pi_req rq;
1600     struct pi_local *lp = (struct pi_local *) dev->priv;
1601 
1602     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1603     if (ret)
1604         return ret;
1605         
1606     if(cmd!=SIOCDEVPRIVATE)
1607         return -EINVAL;
1608 
1609     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1610 
1611     switch (rq.cmd) {
1612     case SIOCSPIPARAM:
1613 
1614         if (!suser())
1615             return -EPERM;
1616         save_flags(flags);
1617         cli();
1618         lp->txdelay = rq.txdelay;
1619         lp->persist = rq.persist;
1620         lp->slotime = rq.slotime;
1621         lp->squeldelay = rq.squeldelay;
1622         lp->clockmode = rq.clockmode;
1623         lp->speed = rq.speed;
1624         pi_open(&pi0a); /* both channels get reset %%% */
1625         restore_flags(flags);
1626         ret = 0;
1627         break;
1628 
1629     case SIOCSPIDMA:
1630 
1631         if (!suser())
1632             return -EPERM;
1633         ret = 0;
1634         if (dev->base_addr & 2) {   /* if A channel */
1635            if (rq.dmachan < 1 || rq.dmachan > 3)
1636                 return -EINVAL;
1637            save_flags(flags);
1638            cli();
1639            pi_close(dev);
1640            free_dma(lp->dmachan);
1641            dev->dma = lp->dmachan = rq.dmachan;
1642            if (request_dma(lp->dmachan,"pi2")) 
1643                 ret = -EAGAIN;
1644            pi_open(dev);
1645            restore_flags(flags);
1646         }
1647         break;
1648 
1649     case SIOCSPIIRQ:
1650         ret = -EINVAL;      /* add this later */
1651         break;
1652 
1653     case SIOCGPIPARAM:
1654     case SIOCGPIDMA:
1655     case SIOCGPIIRQ:
1656 
1657         rq.speed = lp->speed;
1658         rq.txdelay = lp->txdelay;
1659         rq.persist = lp->persist;
1660         rq.slotime = lp->slotime;
1661         rq.squeldelay = lp->squeldelay;
1662         rq.clockmode = lp->clockmode;
1663         rq.dmachan = lp->dmachan;
1664         rq.irq = dev->irq;
1665         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1666         ret = 0;
1667         break;
1668 
1669     default:
1670         ret = -EINVAL;
1671     }
1672     return ret;
1673 }
1674 
1675 /* Get the current statistics.  This may be called with the card open or
1676    closed. */
1677 static struct netstats *
1678  pi_get_stats(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1679 {
1680     struct pi_local *lp = (struct pi_local *) dev->priv;
1681 
1682     return &lp->stats;
1683 }
1684 
1685 
1686 /*
1687  * Local variables:
1688  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1689  *  version-control: t
1690  *  kept-new-versions: 5
1691  *  tab-width: 4
1692  * End:
1693  */

/* [previous][next][first][last][top][bottom][index][help] */