taglinefilesource code
ctrl1471drivers/block/sjcd.cu_char ctrl;
ctrl1482drivers/block/sjcd.cctrl = ISP16_IN( ISP16_CTRL_PORT ) & 0xFC;
ctrl1483drivers/block/sjcd.cISP16_OUT( ISP16_CTRL_PORT, ctrl );
ctrl1503drivers/block/sjcd.cISP16_OUT( ISP16_CTRL_PORT, ctrl );
ctrl1512drivers/block/sjcd.cISP16_OUT( ISP16_CTRL_PORT, ctrl );
ctrl1520drivers/block/sjcd.cu_char ctrl;
ctrl1529drivers/block/sjcd.cctrl = ISP16_IN( ISP16_CTRL_PORT );
ctrl1539drivers/block/sjcd.cISP16_OUT( ISP16_CTRL_PORT, ctrl );
ctrl193drivers/char/scc.cOutReg(scc->ctrl, reg, (scc->wreg[reg] = val));
ctrl199drivers/char/scc.cOutReg(scc->ctrl, reg, (scc->wreg[reg] |= val));
ctrl205drivers/char/scc.cOutReg(scc->ctrl, reg, (scc->wreg[reg] &= ~val));
ctrl494drivers/char/scc.cdefault    : printk("scc_isr(): unknown interrupt status (addr %4.4x, state %2.2x)\n",scc->ctrl,vector);
ctrl541drivers/char/scc.cOutb(scc->ctrl,0x38);              /* Reset Highest IUS" opcode to WR0 */
ctrl631drivers/char/scc.cOutb(scc->ctrl,RES_Tx_P);       /* reset pending int */          
ctrl639drivers/char/scc.cOutb(scc->ctrl, RES_Tx_CRC);  /* reset CRC generator */
ctrl644drivers/char/scc.cOutb(scc->ctrl, RES_EOM_L);
ctrl681drivers/char/scc.cstatus = InReg(scc->ctrl,R0);
ctrl699drivers/char/scc.cOutReg(scc->ctrl,R14,SEARCH|scc->wreg[R14]); /* DPLL: enter search mode */
ctrl721drivers/char/scc.cOutb(scc->ctrl, RES_Tx_P);
ctrl722drivers/char/scc.cOutb(scc->ctrl, RES_EXT_INT);  /* reset ext/status interrupts */
ctrl733drivers/char/scc.cOutb(scc->ctrl, RES_Tx_P); /* just to be sure */
ctrl742drivers/char/scc.cOutb(scc->ctrl,RES_EXT_INT);
ctrl807drivers/char/scc.cstatus = InReg(scc->ctrl,R1);    /* read Special Receive Condition status */
ctrl875drivers/char/scc.cOutb(scc->ctrl,ERR_RES);
ctrl911drivers/char/scc.cOutReg(scc->ctrl, R14, SSBR|scc->wreg[R14]);  /* DPLL source = BRG */
ctrl912drivers/char/scc.cOutReg(scc->ctrl, R14, SNRZI|scc->wreg[R14]);  /* DPLL NRZI mode */
ctrl973drivers/char/scc.cOutReg(scc->ctrl, R14, DISDPLL);
ctrl987drivers/char/scc.cif((InReg(scc->ctrl,R0)) & DCD)    /* DCD is now ON */
ctrl995drivers/char/scc.cOutb(scc->ctrl,RES_EXT_INT);  /* reset ext/status interrupts */
ctrl996drivers/char/scc.cOutb(scc->ctrl,RES_EXT_INT);  /* must be done twice */
ctrl998drivers/char/scc.cscc->status = InReg(scc->ctrl,R0);  /* read initial status */
ctrl1028drivers/char/scc.cOutb(scc->ctrl + 4, Option | (tx? 0x80 : 0));
ctrl1481drivers/char/scc.cif (!scc->ctrl) continue;
ctrl1485drivers/char/scc.cOutReg(scc->ctrl,R9,FHWRES);  /* force hardware reset */
ctrl1486drivers/char/scc.cOutReg(scc->ctrl,R9,0);    /* end hardware reset */
ctrl1487drivers/char/scc.cOutReg(scc->ctrl,R9,CHRA);  /* reset channel A */
ctrl1488drivers/char/scc.cOutReg(scc->ctrl,R9,CHRB);  /* reset channel B */
ctrl1489drivers/char/scc.cOutReg(scc->ctrl,R1, 0);  /* No Rx irq from channel A */
ctrl1491drivers/char/scc.cOutReg(scc->ctrl,R1, 0);  /* No Rx irq from channel B */
ctrl1493drivers/char/scc.cOutReg(scc->ctrl,R2, chip*16);  /* Set Interrupt vector */
ctrl1630drivers/char/scc.cOutb(scc->ctrl,0);    /* Make sure pointer is written */
ctrl1777drivers/char/scc.c| ((InReg(scc->ctrl,R0) & DCD)  ? TIOCM_CAR : 0)
ctrl1778drivers/char/scc.c| ((InReg(scc->ctrl,R0) & CTS)  ? TIOCM_CTS : 0);
ctrl2175drivers/char/scc.cregister io_port ctrl;
ctrl2226drivers/char/scc.cctrl = SCC_ctrl[chip * 2];
ctrl2227drivers/char/scc.cif (!ctrl) continue;
ctrl2237drivers/char/scc.ccheck_region(ctrl, 1);
ctrl2239drivers/char/scc.cOutb(ctrl, 0);
ctrl2240drivers/char/scc.cOutReg(ctrl,R13,0x55);    /* is this chip realy there? */
ctrl2242drivers/char/scc.cif (InReg(ctrl,R13) != 0x55 )
ctrl2250drivers/char/scc.cSCC_Info[2*chip  ].ctrl     = SCC_ctrl[2*chip];
ctrl2255drivers/char/scc.cSCC_Info[2*chip+1].ctrl     = SCC_ctrl[2*chip+1];
ctrl2271drivers/char/scc.cSCC_Info[chan].ctrl? "found"   : "missing");
ctrl2273drivers/char/scc.cif (SCC_Info[chan].ctrl == 0) 
ctrl56drivers/sound/pas2_midi.cunsigned char   ctrl;
ctrl80drivers/sound/pas2_midi.cctrl = 0;
ctrl86drivers/sound/pas2_midi.cctrl |= M_C_ENA_INPUT_IRQ;  /*
ctrl94drivers/sound/pas2_midi.cctrl |= M_C_ENA_OUTPUT_IRQ |  /*
ctrl100drivers/sound/pas2_midi.cpas_write (ctrl,
ctrl229include/linux/scc.hio_port ctrl;    /* I/O address of CONTROL register */