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*/
1 /*
2 * bios32.c - PCI BIOS functions for Alpha systems not using BIOS
3 * emulation code.
4 *
5 * Written by Dave Rusling (david.rusling@reo.mts.dec.com)
6 *
7 * Adapted to 64-bit kernel and then rewritten by David Mosberger
8 * (davidm@cs.arizona.edu)
9 *
10 * For more information, please consult
11 *
12 * PCI BIOS Specification Revision
13 * PCI Local Bus Specification
14 * PCI System Design Guide
15 *
16 * PCI Special Interest Group
17 * M/S HF3-15A
18 * 5200 N.E. Elam Young Parkway
19 * Hillsboro, Oregon 97124-6497
20 * +1 (503) 696-2000
21 * +1 (800) 433-5177
22 *
23 * Manuals are $25 each or $50 for all three, plus $7 shipping
24 * within the United States, $35 abroad.
25 */
26 #include <linux/config.h>
27
28 #ifndef CONFIG_PCI
29
30 int pcibios_present(void)
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*/
31 {
32 return 0;
33 }
34
35 #else /* CONFIG_PCI */
36
37 #include <linux/kernel.h>
38 #include <linux/bios32.h>
39 #include <linux/pci.h>
40 #include <linux/malloc.h>
41 #include <linux/mm.h>
42
43 #include <asm/hwrpb.h>
44 #include <asm/io.h>
45
46
47 #define KB 1024
48 #define MB (1024*KB)
49 #define GB (1024*MB)
50
51 #define MAJOR_REV 0
52 #define MINOR_REV 2
53
54 /*
55 * Align VAL to ALIGN, which must be a power of two.
56 */
57 #define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
58
59
60 /*
61 * Temporary internal macro. If this 0, then do not write to any of
62 * the PCI registers, merely read them (i.e., use configuration as
63 * determined by SRM). The SRM seem do be doing a less than perfect
64 * job in configuring PCI devices, so for now we do it ourselves.
65 * Reconfiguring PCI devices breaks console (RPB) callbacks, but
66 * those don't work properly with 64 bit addresses anyways.
67 *
68 * The accepted convention seems to be that the console (POST
69 * software) should fully configure boot devices and configure the
70 * interrupt routing of *all* devices. In particular, the base
71 * addresses of non-boot devices need not be initialized. For
72 * example, on the AXPpci33 board, the base address a #9 GXE PCI
73 * graphics card reads as zero (this may, however, be due to a bug in
74 * the graphics card---there have been some rumor that the #9 BIOS
75 * incorrectly resets that address to 0...).
76 */
77 #define PCI_MODIFY 1
78
79
80 extern struct hwrpb_struct *hwrpb;
81
82
83 #if PCI_MODIFY
84
85 static unsigned int io_base = 64*KB; /* <64KB are (E)ISA ports */
86 static unsigned int mem_base = 16*MB; /* <16MB is ISA memory */
87
88
89 /*
90 * Layout memory and I/O for a device:
91 */
92 static void layout_dev(struct pci_dev *dev)
/* ![[previous]](../icons/left.png)
*/
93 {
94 struct pci_bus *bus;
95 unsigned short cmd;
96 unsigned int base, mask, size, reg;
97
98 bus = dev->bus;
99 pcibios_read_config_word(bus->number, dev->devfn, PCI_COMMAND, &cmd);
100
101 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
102 /*
103 * Figure out how much space and of what type this
104 * device wants.
105 */
106 pcibios_write_config_dword(bus->number, dev->devfn, reg,
107 0xffffffff);
108 pcibios_read_config_dword(bus->number, dev->devfn, reg, &base);
109 if (!base) {
110 /* this base-address register is unused */
111 continue;
112 }
113 /*
114 * We've read the base address register back after
115 * writing all ones and so now we must decode it.
116 */
117 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
118 /*
119 * I/O space base address register.
120 */
121 cmd |= PCI_COMMAND_IO;
122
123 base &= PCI_BASE_ADDRESS_IO_MASK;
124 mask = (~base << 1) | 0x1;
125 size = (mask & base) & 0xffffffff;
126 base = ALIGN(io_base, size);
127 io_base = base + size;
128 pcibios_write_config_dword(bus->number, dev->devfn,
129 reg, base | 0x1);
130 } else {
131 unsigned int type;
132 /*
133 * Memory space base address register.
134 */
135 cmd |= PCI_COMMAND_MEMORY;
136
137 type = base & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
138 base &= PCI_BASE_ADDRESS_MEM_MASK;
139 mask = (~base << 1) | 0x1;
140 size = (mask & base) & 0xffffffff;
141 switch (type) {
142 case PCI_BASE_ADDRESS_MEM_TYPE_32:
143 break;
144
145 case PCI_BASE_ADDRESS_MEM_TYPE_64:
146 printk("bios32 WARNING: "
147 "ignoring 64-bit device in "
148 "slot %d, function %d: \n",
149 PCI_SLOT(dev->devfn),
150 PCI_FUNC(dev->devfn));
151 reg += 4; /* skip extra 4 bytes */
152 continue;
153
154 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
155 /*
156 * Allocating memory below 1MB is *very*
157 * tricky, as there may be all kinds of
158 * ISA devices lurking that we don't know
159 * about. For now, we just cross fingers
160 * and hope nobody tries to do this on an
161 * Alpha (or that the console has set it
162 * up properly).
163 */
164 printk("bios32 WARNING: slot %d, function %d "
165 "requests memory below 1MB---don't "
166 "know how to do that.\n",
167 PCI_SLOT(dev->devfn),
168 PCI_FUNC(dev->devfn));
169 continue;
170 }
171 /*
172 * The following holds at least for the Low Cost
173 * Alpha implementation of the PCI interface:
174 *
175 * In sparse memory address space, the first
176 * octant (16MB) of every 128MB segment is
177 * aliased to the the very first 16MB of the
178 * address space (i.e., it aliases the ISA
179 * memory address space). Thus, we try to
180 * avoid allocating PCI devices in that range.
181 * Can be allocated in 2nd-7th octant only.
182 * Devices that need more than 112MB of
183 * address space must be accessed through
184 * dense memory space only!
185 */
186 base = ALIGN(mem_base, size);
187 if (size > 7 * 16*MB) {
188 printk("bios32 WARNING: slot %d, function %d "
189 "requests %dB of contiguous address "
190 " space---don't use sparse memory "
191 " accesses on this device!!\n",
192 PCI_SLOT(dev->devfn),
193 PCI_FUNC(dev->devfn), size);
194 } else {
195 if (((base / 16*MB) & 0x7) == 0) {
196 base &= ~(128*MB - 1);
197 base += 16*MB;
198 base = ALIGN(base, size);
199 }
200 if (base / 128*MB != (base + size) / 128*MB) {
201 base &= ~(128*MB - 1);
202 base += (128 + 16)*MB;
203 base = ALIGN(base, size);
204 }
205 }
206 mem_base = base + size;
207 pcibios_write_config_dword(bus->number, dev->devfn,
208 reg, base);
209 }
210 }
211 /* enable device: */
212 pcibios_write_config_word(bus->number, dev->devfn, PCI_COMMAND,
213 cmd | PCI_COMMAND_MASTER);
214 }
215
216
217 static void layout_bus(struct pci_bus *bus)
/* */
218 {
219 unsigned int l, tio, bio, tmem, bmem;
220 struct pci_bus *child;
221 struct pci_dev *dev;
222
223 if (!bus->devices && !bus->children)
224 return;
225
226 /*
227 * Align the current bases on appropriate boundaries (4K for
228 * IO and 1MB for memory).
229 */
230 bio = io_base = ALIGN(io_base, 4*KB);
231 bmem = mem_base = ALIGN(mem_base, 1*MB);
232
233 /*
234 * Allocate space to each device:
235 */
236 for (dev = bus->devices; dev; dev = dev->sibling) {
237 if (dev->class >> 16 != PCI_BASE_CLASS_BRIDGE) {
238 layout_dev(dev);
239 }
240 }
241 /*
242 * Recursively allocate space for all of the sub-buses:
243 */
244 for (child = bus->children; child; child = child->next) {
245 layout_bus(child);
246 }
247 /*
248 * Align the current bases on 4K and 1MB boundaries:
249 */
250 tio = io_base = ALIGN(io_base, 4*KB);
251 tmem = mem_base = ALIGN(mem_base, 1*MB);
252
253 if (bus->self) {
254 struct pci_dev *bridge = bus->self;
255 /*
256 * Set up the top and bottom of the I/O memory segment
257 * for this bus.
258 */
259 pcibios_read_config_dword(bridge->bus->number, bridge->devfn,
260 0x1c, &l);
261 l = l | (bio >> 8) | ((tio - 1) & 0xf000);
262 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
263 0x1c, l);
264
265 l = ((bmem & 0xfff00000) >> 16) | ((tmem - 1) & 0xfff00000);
266 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
267 0x20, l);
268 /*
269 * Turn off downstream PF memory address range:
270 */
271 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
272 0x24, 0x0000ffff);
273 /*
274 * Tell bridge that there is an ISA bus in the system:
275 */
276 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
277 0x3c, 0x00040000);
278 /*
279 * Clear status bits, enable I/O (for downstream I/O),
280 * turn on master enable (for upstream I/O), turn on
281 * memory enable (for downstream memory), turn on
282 * master enable (for upstream memory and I/O).
283 */
284 pcibios_write_config_dword(bridge->bus->number, bridge->devfn,
285 0x4, 0xffff0007);
286 }
287 }
288
289 #endif /* !PCI_MODIFY */
290
291
292 /*
293 * Given the vendor and device ids, find the n'th instance of that device
294 * in the system.
295 */
296 int pcibios_find_device (unsigned short vendor, unsigned short device_id,
/* */
297 unsigned short index, unsigned char *bus,
298 unsigned char *devfn)
299 {
300 unsigned int current = 0;
301 struct pci_dev *dev;
302
303 for (dev = pci_devices; dev; dev = dev->next) {
304 if (dev->vendor == vendor && dev->device == device_id) {
305 if (current == index) {
306 *devfn = dev->devfn;
307 *bus = dev->bus->number;
308 return PCIBIOS_SUCCESSFUL;
309 }
310 ++current;
311 }
312 }
313 return PCIBIOS_DEVICE_NOT_FOUND;
314 }
315
316
317 /*
318 * Given the class, find the n'th instance of that device
319 * in the system.
320 */
321 int pcibios_find_class (unsigned int class_code, unsigned short index,
/* */
322 unsigned char *bus, unsigned char *devfn)
323 {
324 unsigned int current = 0;
325 struct pci_dev *dev;
326
327 for (dev = pci_devices; dev; dev = dev->next) {
328 if (dev->class == class_code) {
329 if (current == index) {
330 *devfn = dev->devfn;
331 *bus = dev->bus->number;
332 return PCIBIOS_SUCCESSFUL;
333 }
334 ++current;
335 }
336 }
337 return PCIBIOS_DEVICE_NOT_FOUND;
338 }
339
340
341 int pcibios_present(void)
/* */
342 {
343 return 1;
344 }
345
346
347 unsigned long pcibios_init(unsigned long mem_start,
/* */
348 unsigned long mem_end)
349 {
350 printk("Alpha PCI BIOS32 revision %x.%02x\n", MAJOR_REV, MINOR_REV);
351
352 #if !PCI_MODIFY
353 printk("...NOT modifying existing (SRM) PCI configuration\n");
354 #endif
355 return mem_start;
356 }
357
358
359 /*
360 * Fixup configuration for Noname boards (AXPpci33).
361 */
362 static void noname_fixup(void)
/* */
363 {
364 struct pci_dev *dev;
365
366 /*
367 * The Noname board has 5 PCI slots with each of the 4
368 * interrupt pins routed to different pins on the PCI/ISA
369 * bridge (PIRQ0-PIRQ3). I don't have any information yet as
370 * to how INTB, INTC, and INTD get routed (4/12/95,
371 * davidm@cs.arizona.edu).
372 */
373 static const char pirq_tab[5][4] = {
374 { 3, -1, -1, -1}, /* slot 6 (53c810) */
375 {-1, -1, -1, -1}, /* slot 7 (PCI/ISA bridge) */
376 { 2, -1, -1, -1}, /* slot 8 (slot closest to ISA) */
377 { 1, -1, -1, -1}, /* slot 9 (middle slot) */
378 { 0, -1, -1, -1}, /* slot 10 (slot furthest from ISA) */
379 };
380 /*
381 * route_tab selects irq routing in PCI/ISA bridge so that:
382 * PIRQ0 -> irq 15
383 * PIRQ1 -> irq 9
384 * PIRQ2 -> irq 10
385 * PIRQ3 -> irq 11
386 */
387 const unsigned int route_tab = 0x0b0a090f;
388 unsigned char pin;
389 int pirq;
390
391 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60, route_tab);
392
393 /* ensure irq 9, 10, 11, and 15 are level sensitive: */
394 outb((1<<(9-8)) | (1<<(10-8)) | (1<<(11-8)) | (1<<(15-8)), 0x4d1);
395
396 /*
397 * Go through all devices, fixing up irqs as we see fit:
398 */
399 for (dev = pci_devices; dev; dev = dev->next) {
400 dev->irq = 0;
401 if (dev->bus->number != 0 ||
402 PCI_SLOT(dev->devfn) < 6 || PCI_SLOT(dev->devfn) > 10)
403 {
404 printk("noname_set_irq: no dev on bus %d, slot %d!!\n",
405 dev->bus->number, PCI_SLOT(dev->devfn));
406 continue;
407 }
408
409 pcibios_read_config_byte(dev->bus->number, dev->devfn,
410 PCI_INTERRUPT_PIN, &pin);
411 if (!pin) {
412 if (dev->vendor == PCI_VENDOR_ID_S3 &&
413 (dev->device == PCI_DEVICE_ID_S3_864_1 ||
414 dev->device == PCI_DEVICE_ID_S3_864_2))
415 {
416 pin = 1;
417 } else {
418 continue; /* no interrupt line */
419 }
420 }
421 pirq = pirq_tab[PCI_SLOT(dev->devfn) - 6][pin - 1];
422 if (pirq < 0) {
423 continue;
424 }
425 dev->irq = (route_tab >> (8 * pirq)) & 0xff;
426 #if PCI_MODIFY
427 /* tell the device: */
428 pcibios_write_config_byte(dev->bus->number, dev->devfn,
429 PCI_INTERRUPT_LINE, dev->irq);
430 #endif
431 }
432
433 #if PCI_MODIFY
434 {
435 unsigned char hostid;
436 /*
437 * SRM console version X3.9 seems to reset the SCSI
438 * host-id to 0 no matter what console environment
439 * variable pka0_host_id is set to. Thus, if the
440 * host-id reads out as a zero, we set it to 7. The
441 * SCSI controller is on the motherboard on bus 0,
442 * slot 6
443 */
444 if (pcibios_read_config_byte(0, PCI_DEVFN(6, 0), 0x84, &hostid)
445 == PCIBIOS_SUCCESSFUL && (hostid == 0))
446 {
447 pcibios_write_config_byte(0, PCI_DEVFN(6, 0),
448 0x84, 7);
449 }
450 }
451 #endif /* !PCI_MODIFY */
452
453 /*
454 * The SRM console *disables* the IDE interface, this code *
455 * enables it. With the miniloader, this may not be necessary
456 * but it shouldn't hurt either.
457 *
458 * This code bangs on a control register of the 87312 Super
459 * I/O chip that implements parallel port/serial
460 * ports/IDE/FDI. Depending on the motherboard, the Super I/O
461 * chip can be configured through a pair of registers that are
462 * located either at I/O ports 0x26e/0x26f or 0x398/0x399.
463 * Unfortunately, autodetecting which base address is in use
464 * works only once (right after a reset). On the other hand,
465 * the Noname board hardwires the I/O ports to 0x26e/0x26f so
466 * we just use those. The Super I/O chip has the additional
467 * quirk that configuration register data must be written
468 * twice (I believe this is a saftey feature to prevent
469 * accidental modification---happy PC world...).
470 */
471 {
472 long flags;
473 int data;
474
475 /* update needs to be atomic: */
476
477 save_flags(flags);
478 cli();
479
480 outb(0, 0x26e); /* set the index register for reg #0 */
481 data = inb(0x26f); /* read the current contents */
482 #ifdef DEBUG
483 printk("base @ 0x26e: reg#0 0x%x\n", data);
484 #endif
485 outb(0, 0x26e); /* set the index register for reg #0 */
486 outb(data | 0x40, 0x26f); /* turn on IDE */
487 outb(data | 0x40, 0x26f); /* yes, we really mean it... */
488 #ifdef DEBUG
489 outb(0, 0x26e); data = inb(0x26f);
490 printk("base @ 0x26e: reg#0 0x%x\n", data);
491 #endif
492 restore_flags(flags);
493 }
494 }
495
496
497 unsigned long pcibios_fixup(unsigned long mem_start, unsigned long mem_end)
/* */
498 {
499 #if PCI_MODIFY
500 /*
501 * Scan the tree, allocating PCI memory and I/O space.
502 */
503 layout_bus(&pci_root);
504 #endif
505
506 /*
507 * Now is the time to do all those dirty little deeds...
508 */
509 switch (hwrpb->sys_type) {
510 case ST_DEC_AXPPCI_33: noname_fixup(); break;
511
512 default:
513 printk("pcibios_fixup: don't know how to fixup sys type %ld\n",
514 hwrpb->sys_type);
515 break;
516 }
517 return mem_start;
518 }
519
520
521 char *pcibios_strerror (int error)
/* ![[last]](../icons/n_last.png)
*/
522 {
523 static char buf[80];
524
525 switch (error) {
526 case PCIBIOS_SUCCESSFUL:
527 return "SUCCESSFUL";
528
529 case PCIBIOS_FUNC_NOT_SUPPORTED:
530 return "FUNC_NOT_SUPPORTED";
531
532 case PCIBIOS_BAD_VENDOR_ID:
533 return "SUCCESSFUL";
534
535 case PCIBIOS_DEVICE_NOT_FOUND:
536 return "DEVICE_NOT_FOUND";
537
538 case PCIBIOS_BAD_REGISTER_NUMBER:
539 return "BAD_REGISTER_NUMBER";
540
541 default:
542 sprintf (buf, "UNKNOWN RETURN 0x%x", error);
543 return buf;
544 }
545 }
546
547 #endif /* CONFIG_PCI */
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*/