This source file includes following definitions.
- virt_to_bus
- bus_to_virt
- __inb
- __outb
- __inw
- __outw
- __inl
- __outl
- __readb
- __readw
- __readl
- __writeb
- __writew
- __writel
- readl
- writel
1 #ifndef __ALPHA_LCA__H
2 #define __ALPHA_LCA__H
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55 #define LCA_DMA_WIN_BASE (1024*1024*1024)
56 #define LCA_DMA_WIN_SIZE (1024*1024*1024)
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60
61 #define LCA_MEM_BCR0 (IDENT_ADDR + 0x120000000UL)
62 #define LCA_MEM_BCR1 (IDENT_ADDR + 0x120000008UL)
63 #define LCA_MEM_BCR2 (IDENT_ADDR + 0x120000010UL)
64 #define LCA_MEM_BCR3 (IDENT_ADDR + 0x120000018UL)
65 #define LCA_MEM_BMR0 (IDENT_ADDR + 0x120000020UL)
66 #define LCA_MEM_BMR1 (IDENT_ADDR + 0x120000028UL)
67 #define LCA_MEM_BMR2 (IDENT_ADDR + 0x120000030UL)
68 #define LCA_MEM_BMR3 (IDENT_ADDR + 0x120000038UL)
69 #define LCA_MEM_BTR0 (IDENT_ADDR + 0x120000040UL)
70 #define LCA_MEM_BTR1 (IDENT_ADDR + 0x120000048UL)
71 #define LCA_MEM_BTR2 (IDENT_ADDR + 0x120000050UL)
72 #define LCA_MEM_BTR3 (IDENT_ADDR + 0x120000058UL)
73 #define LCA_MEM_GTR (IDENT_ADDR + 0x120000060UL)
74 #define LCA_MEM_ESR (IDENT_ADDR + 0x120000068UL)
75 #define LCA_MEM_EAR (IDENT_ADDR + 0x120000070UL)
76 #define LCA_MEM_CAR (IDENT_ADDR + 0x120000078UL)
77 #define LCA_MEM_VGR (IDENT_ADDR + 0x120000080UL)
78 #define LCA_MEM_PLM (IDENT_ADDR + 0x120000088UL)
79 #define LCA_MEM_FOR (IDENT_ADDR + 0x120000090UL)
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84 #define LCA_IOC_HAE (IDENT_ADDR + 0x180000000UL)
85 #define LCA_IOC_CONF (IDENT_ADDR + 0x180000020UL)
86 #define LCA_IOC_STAT0 (IDENT_ADDR + 0x180000040UL)
87 #define LCA_IOC_STAT1 (IDENT_ADDR + 0x180000060UL)
88 #define LCA_IOC_TBIA (IDENT_ADDR + 0x180000080UL)
89 #define LCA_IOC_TB_ENA (IDENT_ADDR + 0x1800000a0UL)
90 #define LCA_IOC_SFT_RST (IDENT_ADDR + 0x1800000c0UL)
91 #define LCA_IOC_PAR_DIS (IDENT_ADDR + 0x1800000e0UL)
92 #define LCA_IOC_W_BASE0 (IDENT_ADDR + 0x180000100UL)
93 #define LCA_IOC_W_BASE1 (IDENT_ADDR + 0x180000120UL)
94 #define LCA_IOC_W_MASK0 (IDENT_ADDR + 0x180000140UL)
95 #define LCA_IOC_W_MASK1 (IDENT_ADDR + 0x180000160UL)
96 #define LCA_IOC_T_BASE0 (IDENT_ADDR + 0x180000180UL)
97 #define LCA_IOC_T_BASE1 (IDENT_ADDR + 0x1800001a0UL)
98 #define LCA_IOC_TB_TAG0 (IDENT_ADDR + 0x188000000UL)
99 #define LCA_IOC_TB_TAG1 (IDENT_ADDR + 0x188000020UL)
100 #define LCA_IOC_TB_TAG2 (IDENT_ADDR + 0x188000040UL)
101 #define LCA_IOC_TB_TAG3 (IDENT_ADDR + 0x188000060UL)
102 #define LCA_IOC_TB_TAG4 (IDENT_ADDR + 0x188000070UL)
103 #define LCA_IOC_TB_TAG5 (IDENT_ADDR + 0x1880000a0UL)
104 #define LCA_IOC_TB_TAG6 (IDENT_ADDR + 0x1880000c0UL)
105 #define LCA_IOC_TB_TAG7 (IDENT_ADDR + 0x1880000e0UL)
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110 #define LCA_IACK_SC (IDENT_ADDR + 0x1a0000000UL)
111 #define LCA_CONF (IDENT_ADDR + 0x1e0000000UL)
112 #define LCA_IO (IDENT_ADDR + 0x1c0000000UL)
113 #define LCA_SPARSE_MEM (IDENT_ADDR + 0x200000000UL)
114 #define LCA_DENSE_MEM (IDENT_ADDR + 0x300000000UL)
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119 #define LCA_IOC_STAT0_CMD 0xf
120 #define LCA_IOC_STAT0_ERR (1<<4)
121 #define LCA_IOC_STAT0_LOST (1<<5)
122 #define LCA_IOC_STAT0_THIT (1<<6)
123 #define LCA_IOC_STAT0_TREF (1<<7)
124 #define LCA_IOC_STAT0_CODE_SHIFT 8
125 #define LCA_IOC_STAT0_CODE_MASK 0x7
126 #define LCA_IOC_STAT0_P_NBR_SHIFT 13
127 #define LCA_IOC_STAT0_P_NBR_MASK 0x7ffff
128
129 #define HAE_ADDRESS LCA_IOC_HAE
130
131 #ifdef __KERNEL__
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137 extern inline unsigned long virt_to_bus(void * address)
138 {
139 return virt_to_phys(address) + LCA_DMA_WIN_BASE;
140 }
141
142 extern inline void * bus_to_virt(unsigned long address)
143 {
144 return phys_to_virt(address - LCA_DMA_WIN_BASE);
145 }
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157
158 #define vuip volatile unsigned int *
159
160 extern inline unsigned int __inb(unsigned long addr)
161 {
162 long result = *(vuip) ((addr << 5) + LCA_IO + 0x00);
163 result >>= (addr & 3) * 8;
164 return 0xffUL & result;
165 }
166
167 extern inline void __outb(unsigned char b, unsigned long addr)
168 {
169 unsigned int w;
170
171 asm ("insbl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
172 *(vuip) ((addr << 5) + LCA_IO + 0x00) = w;
173 mb();
174 }
175
176 extern inline unsigned int __inw(unsigned long addr)
177 {
178 long result = *(vuip) ((addr << 5) + LCA_IO + 0x08);
179 result >>= (addr & 3) * 8;
180 return 0xffffUL & result;
181 }
182
183 extern inline void __outw(unsigned short b, unsigned long addr)
184 {
185 unsigned int w;
186
187 asm ("inswl %2,%1,%0" : "r="(w) : "ri"(addr & 0x3), "r"(b));
188 *(vuip) ((addr << 5) + LCA_IO + 0x08) = w;
189 mb();
190 }
191
192 extern inline unsigned int __inl(unsigned long addr)
193 {
194 return *(vuip) ((addr << 5) + LCA_IO + 0x18);
195 }
196
197 extern inline void __outl(unsigned int b, unsigned long addr)
198 {
199 *(vuip) ((addr << 5) + LCA_IO + 0x18) = b;
200 mb();
201 }
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207
208 extern inline unsigned long __readb(unsigned long addr)
209 {
210 unsigned long result, shift, msb;
211
212 shift = (addr & 0x3) * 8;
213 if (addr >= (1UL << 24)) {
214 msb = addr & 0xf8000000;
215 addr -= msb;
216 if (msb != hae.cache) {
217 set_hae(msb);
218 }
219 }
220 result = *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x00);
221 result >>= shift;
222 return 0xffUL & result;
223 }
224
225 extern inline unsigned long __readw(unsigned long addr)
226 {
227 unsigned long result, shift, msb;
228
229 shift = (addr & 0x3) * 8;
230 if (addr >= (1UL << 24)) {
231 msb = addr & 0xf8000000;
232 addr -= msb;
233 if (msb != hae.cache) {
234 set_hae(msb);
235 }
236 }
237 result = *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x08);
238 result >>= shift;
239 return 0xffffUL & result;
240 }
241
242 extern inline unsigned long __readl(unsigned long addr)
243 {
244 return *(vuip) (addr + LCA_DENSE_MEM);
245 }
246
247 extern inline void __writeb(unsigned char b, unsigned long addr)
248 {
249 unsigned long msb;
250
251 if (addr >= (1UL << 24)) {
252 msb = addr & 0xf8000000;
253 addr -= msb;
254 if (msb != hae.cache) {
255 set_hae(msb);
256 }
257 }
258 *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x00) = b * 0x01010101;
259 }
260
261 extern inline void __writew(unsigned short b, unsigned long addr)
262 {
263 unsigned long msb;
264
265 if (addr >= (1UL << 24)) {
266 msb = addr & 0xf8000000;
267 addr -= msb;
268 if (msb != hae.cache) {
269 set_hae(msb);
270 }
271 }
272 *(vuip) ((addr << 5) + LCA_SPARSE_MEM + 0x08) = b * 0x00010001;
273 }
274
275 extern inline void __writel(unsigned int b, unsigned long addr)
276 {
277 *(vuip) (addr + LCA_DENSE_MEM) = b;
278 }
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284 extern unsigned int inb(unsigned long addr);
285 extern unsigned int inw(unsigned long addr);
286 extern unsigned int inl(unsigned long addr);
287
288 extern void outb(unsigned char b, unsigned long addr);
289 extern void outw(unsigned short b, unsigned long addr);
290 extern void outl(unsigned int b, unsigned long addr);
291
292 extern unsigned long readb(unsigned long addr);
293 extern unsigned long readw(unsigned long addr);
294
295 extern void writeb(unsigned char b, unsigned long addr);
296 extern void writew(unsigned short b, unsigned long addr);
297
298 #define inb(port) \
299 (__builtin_constant_p((port))?__inb(port):(inb)(port))
300
301 #define outb(x, port) \
302 (__builtin_constant_p((port))?__outb((x),(port)):(outb)((x),(port)))
303
304 #define inb_p inb
305 #define outb_p outb
306
307 extern inline unsigned long readl(unsigned long addr)
308 {
309 return __readl(addr);
310 }
311
312 extern inline void writel(unsigned int b, unsigned long addr)
313 {
314 __writel(b, addr);
315 }
316
317 #undef vuip
318
319 extern unsigned long lca_init (unsigned long mem_start, unsigned long mem_end);
320
321 #endif
322
323 #define RTC_PORT(x) (0x70 + (x))
324 #define RTC_ADDR(x) (0x80 | (x))
325 #define RTC_ALWAYS_BCD 0
326
327 #endif