This source file includes following definitions.
- pi0_preprobe
- random
- wrtscc
- rdscc
- switchbuffers
- hardware_send_packet
- setup_rx_dma
- setup_tx_dma
- tdelay
- free_p
- a_txint
- a_exint
- a_rxint
- b_rxint
- b_txint
- b_exint
- hw_probe
- rts
- pi_header
- pi_rebuild_header
- scc_init
- chipset_init
- pi_init
- valid_dma_page
- pi_set_mac_address
- get_dma_buffer
- pi_probe
- pi_open
- pi_send_packet
- pi_interrupt
- pi_close
- pi_ioctl
- pi_get_stats
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66 #define PI_DMA 3
67
68 #define DEF_A_SPEED 0
69 #define DEF_A_TXDELAY 15
70 #define DEF_A_PERSIST 128
71 #define DEF_A_SLOTIME 15
72 #define DEF_A_SQUELDELAY 1
73 #define DEF_A_CLOCKMODE 0
74
75 #define DEF_B_SPEED 1200
76 #define DEF_B_TXDELAY 40
77 #define DEF_B_PERSIST 128
78 #define DEF_B_SLOTIME 30
79 #define DEF_B_SQUELDELAY 3
80 #define DEF_B_CLOCKMODE 0
81
82 struct device *init_etherdev(struct device *dev, int sizeof_private,
83 unsigned long *mem_startp);
84
85 static char *version =
86 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
87
88
89
90 #define REALLY_SLOW_IO 1
91
92 #define PI2_MODULE 0
93
94 #if PI2_MODULE > 0
95 #include <linux/modules.h>
96 #endif
97
98 #include <linux/config.h>
99 #include <linux/kernel.h>
100 #include <linux/sched.h>
101 #include <linux/types.h>
102 #include <linux/fcntl.h>
103 #include <linux/interrupt.h>
104 #include <linux/ptrace.h>
105 #include <linux/ioport.h>
106 #include <linux/in.h>
107 #include <linux/malloc.h>
108 #include <linux/string.h>
109 #include <linux/errno.h>
110 #include <asm/system.h>
111 #include <asm/bitops.h>
112 #include <asm/io.h>
113 #include <asm/dma.h>
114 #include <asm/segment.h>
115 #include <linux/inet.h>
116 #include <linux/netdevice.h>
117 #include <linux/etherdevice.h>
118 #include <linux/skbuff.h>
119 #include <linux/timer.h>
120 #include "pi2.h"
121 #include "z8530.h"
122 #include <net/ax25.h>
123
124
125 struct mbuf {
126 struct mbuf *next;
127 int cnt;
128 char data[0];
129 };
130
131
132
133
134
135
136
137
138
139 static int pi0_preprobe(struct device *dev){return 0;}
140 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
141 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
142
143
144
145 #define PI_TOTAL_SIZE 8
146
147
148
149
150 static int pi_probe(struct device *dev, int card_type);
151 static int pi_open(struct device *dev);
152 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
153 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
154 static int pi_close(struct device *dev);
155 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
156 static struct enet_statistics *pi_get_stats(struct device *dev);
157 static void rts(struct pi_local *lp, int x);
158 static void b_rxint(struct device *dev, struct pi_local *lp);
159 static void b_txint(struct pi_local *lp);
160 static void b_exint(struct pi_local *lp);
161 static void a_rxint(struct device *dev, struct pi_local *lp);
162 static void a_txint(struct pi_local *lp);
163 static void a_exint(struct pi_local *lp);
164 static char *get_dma_buffer(unsigned long *mem_ptr);
165 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
166
167 static char ax25_bcast[7] =
168 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
169 static char ax25_test[7] =
170 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
171
172 static int ext2_secrm_seed = 152;
173
174 static inline unsigned char random(void)
175 {
176 return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
177 * 69069l + 1);
178 }
179
180 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
181 {
182
183 outb_p(0, cbase + DMAEN);
184 outb_p(sccreg, ctl);
185 outb_p(val, ctl);
186 outb_p(1, cbase + DMAEN);
187 }
188
189 static inline int rdscc(int cbase, int ctl, int sccreg)
190 {
191 int retval;
192
193
194 outb_p(0, cbase + DMAEN);
195 outb_p(sccreg, ctl);
196 retval = inb_p(ctl);
197 outb_p(1, cbase + DMAEN);
198 return retval;
199 }
200
201 static void switchbuffers(struct pi_local *lp)
202 {
203 if (lp->rcvbuf == lp->rxdmabuf1)
204 lp->rcvbuf = lp->rxdmabuf2;
205 else
206 lp->rcvbuf = lp->rxdmabuf1;
207 }
208
209 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
210 {
211 char kickflag;
212 unsigned long flags;
213
214 lp->stats.tx_packets++;
215
216 save_flags(flags);
217 cli();
218 kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
219 restore_flags(flags);
220
221 skb_queue_tail(&lp->sndq, skb);
222 if (kickflag) {
223
224 switch (lp->base & 2) {
225 case 2:
226 a_txint(lp);
227 break;
228 case 0:
229 save_flags(flags);
230 cli();
231 if (lp->tstate == IDLE)
232 b_txint(lp);
233 restore_flags(flags);
234 break;
235 }
236 }
237 }
238
239 static void setup_rx_dma(struct pi_local *lp)
240 {
241 unsigned long flags;
242 int cmd;
243 unsigned long dma_abs;
244 unsigned dmachan;
245
246 save_flags(flags);
247 cli();
248
249 dma_abs = (unsigned long) (lp->rcvbuf->data);
250 dmachan = lp->dmachan;
251 cmd = lp->base + CTL;
252
253 if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
254 panic("PI: RX buffer violates DMA boundary!");
255
256
257 wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
258
259 disable_dma(dmachan);
260 clear_dma_ff(dmachan);
261
262
263
264
265 set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
266 set_dma_addr(dmachan, dma_abs);
267 set_dma_count(dmachan, lp->bufsiz);
268 enable_dma(dmachan);
269
270
271
272
273 wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
274
275
276 wrtscc(lp->cardbase, cmd, R1,
277 WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
278
279 restore_flags(flags);
280 }
281
282 static void setup_tx_dma(struct pi_local *lp, int length)
283 {
284 unsigned long dma_abs;
285 unsigned long flags;
286 unsigned long dmachan;
287
288 save_flags(flags);
289 cli();
290
291 dmachan = lp->dmachan;
292 dma_abs = (unsigned long) (lp->txdmabuf);
293
294 if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
295 panic("PI: TX buffer violates DMA boundary!");
296
297 disable_dma(dmachan);
298
299
300
301 set_dma_mode(dmachan, DMA_MODE_WRITE);
302 clear_dma_ff(dmachan);
303 set_dma_addr(dmachan, dma_abs);
304
305 set_dma_count(dmachan, length);
306
307 restore_flags(flags);
308 }
309
310 static void tdelay(struct pi_local *lp, int time)
311 {
312 int port;
313 unsigned int t1;
314 unsigned char sc;
315
316 if (lp->base & 2) {
317 sc = SC1;
318 t1 = time;
319 port = lp->cardbase + TMR1;
320 } else {
321 sc = SC2;
322 t1 = 10 * time;
323 port = lp->cardbase + TMR2;
324 wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
325 }
326
327
328 outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
329
330
331 outb_p((t1 << 1) & 0xFF, port);
332 outb_p((t1 >> 7) & 0xFF, port);
333
334
335 wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
336 wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
337 }
338
339 static void free_p(struct sk_buff *skb)
340 {
341 dev_kfree_skb(skb, FREE_WRITE);
342 }
343
344 static void a_txint(struct pi_local *lp)
345 {
346 int cmd;
347 unsigned long flags;
348
349 save_flags(flags);
350 cli();
351
352 cmd = CTL + lp->base;
353
354 switch (lp->tstate) {
355 case IDLE:
356
357 if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
358 rts(lp, OFF);
359 restore_flags(flags);
360 return;
361 }
362
363 case DEFER:
364
365
366
367
368 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
369 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
370 if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
371 lp->tstate = DEFER;
372 tdelay(lp, 100);
373
374 wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
375 restore_flags(flags);
376 return;
377 }
378 if (random() > lp->persist) {
379 lp->tstate = DEFER;
380 tdelay(lp, lp->slotime);
381 restore_flags(flags);
382 return;
383 }
384
385 wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
386 rts(lp, ON);
387 lp->tstate = ST_TXDELAY;
388 tdelay(lp, lp->txdelay);
389 restore_flags(flags);
390 return;
391 default:
392 break;
393 }
394
395 restore_flags(flags);
396 }
397
398 static void a_exint(struct pi_local *lp)
399 {
400 unsigned long flags;
401 int cmd;
402 char st;
403 int length;
404
405 save_flags(flags);
406 cli();
407
408 st = rdscc(lp->cardbase, lp->base + CTL, R0);
409
410
411 wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
412 cmd = lp->base + CTL;
413
414 if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
415 setup_rx_dma(lp);
416 lp->rstate = ACTIVE;
417 }
418 switch (lp->tstate) {
419 case ACTIVE:
420 free_p(lp->sndbuf);
421 lp->sndbuf = NULL;
422 lp->tstate = FLAGOUT;
423 tdelay(lp, lp->squeldelay);
424 break;
425 case FLAGOUT:
426 if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
427
428 lp->tstate = IDLE;
429 rts(lp, OFF);
430 restore_flags(flags);
431 return;
432 }
433
434 case ST_TXDELAY:
435
436 disable_dma(lp->dmachan);
437
438
439 wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
440
441
442
443
444 length = lp->sndbuf->len - 1;
445 memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
446
447
448
449 setup_tx_dma(lp, length);
450
451
452
453 enable_dma(lp->dmachan);
454
455
456 wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
457
458
459 wrtscc(lp->cardbase, cmd, R15, TxUIE);
460
461
462 wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
463
464
465 wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
466
467
468
469 lp->tstate = ACTIVE;
470 break;
471 case DEFER:
472
473
474
475 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
476 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
477 if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
478 lp->tstate = DEFER;
479 tdelay(lp, 100);
480
481 wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
482 restore_flags(flags);
483 return;
484 }
485 if (random() > lp->persist) {
486 lp->tstate = DEFER;
487 tdelay(lp, lp->slotime);
488 restore_flags(flags);
489 return;
490 }
491
492 wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
493 rts(lp, ON);
494 lp->tstate = ST_TXDELAY;
495 tdelay(lp, lp->txdelay);
496 restore_flags(flags);
497 return;
498 }
499
500 restore_flags(flags);
501 }
502
503
504
505 static void a_rxint(struct device *dev, struct pi_local *lp)
506 {
507 unsigned long flags;
508 int cmd;
509 int bytecount;
510 char rse;
511 struct sk_buff *skb;
512 int sksize, pkt_len;
513 struct mbuf *cur_buf;
514 unsigned char *cfix;
515
516 save_flags(flags);
517 cli();
518 cmd = lp->base + CTL;
519
520 rse = rdscc(lp->cardbase, cmd, R1);
521 if (rse & Rx_OVR)
522 lp->rstate = RXERROR;
523
524 if (rse & END_FR) {
525
526
527 clear_dma_ff(lp->dmachan);
528 bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
529
530 if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
531 if ((bytecount >= 10) && (rse & CRC_ERR)) {
532 lp->stats.rx_crc_errors++;
533 }
534 if (lp->rstate == RXERROR) {
535 lp->stats.rx_errors++;
536 lp->stats.rx_over_errors++;
537 }
538
539 lp->rstate = ACTIVE;
540 setup_rx_dma(lp);
541 } else {
542
543
544 pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
545
546
547 cur_buf = lp->rcvbuf;
548 switchbuffers(lp);
549 setup_rx_dma(lp);
550
551
552
553 sksize = pkt_len;
554
555 skb = dev_alloc_skb(sksize);
556 if (skb == NULL) {
557 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
558 lp->stats.rx_dropped++;
559 restore_flags(flags);
560 return;
561 }
562 skb->dev = dev;
563
564
565 cfix=skb_put(skb,pkt_len);
566 *cfix++=0;
567
568 memcpy(cfix, (char *) cur_buf->data,
569 pkt_len - 1);
570 skb->protocol=htons(ETH_P_AX25);
571 skb->mac.raw=skb->data;
572 IS_SKB(skb);
573 netif_rx(skb);
574 lp->stats.rx_packets++;
575 }
576 }
577 wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);
578 restore_flags(flags);
579 }
580
581 static void b_rxint(struct device *dev, struct pi_local *lp)
582 {
583 unsigned long flags;
584 int cmd;
585 char rse;
586 struct sk_buff *skb;
587 int sksize;
588 int pkt_len;
589 unsigned char *cfix;
590
591 save_flags(flags);
592 cli();
593 cmd = CTL + lp->base;
594
595 rse = rdscc(lp->cardbase, cmd, R1);
596
597 if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
598
599
600
601 if (rse & Rx_OVR) {
602
603
604 lp->rcp = lp->rcvbuf->data;
605 lp->rcvbuf->cnt = 0;
606
607 lp->rstate = RXERROR;
608 lp->stats.rx_errors++;
609 lp->stats.rx_over_errors++;
610 } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
611
612
613 lp->rcp = lp->rcvbuf->data;
614 lp->rcvbuf->cnt = 0;
615 lp->rstate = TOOBIG;
616 }
617
618 if (lp->rstate == ACTIVE) {
619 *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);
620 lp->rcvbuf->cnt++;
621 } else {
622
623 (void) rdscc(lp->cardbase, cmd, R8);
624 wrtscc(lp->cardbase, cmd, R0, ERR_RES);
625 lp->rstate = ACTIVE;
626 }
627 }
628 if (rse & END_FR) {
629
630 if (lp->rcvbuf->cnt > 0) {
631 if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
632 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
633 lp->stats.rx_crc_errors++;
634 }
635 lp->rcp = lp->rcvbuf->data;
636 lp->rcvbuf->cnt = 0;
637 } else {
638
639 pkt_len = lp->rcvbuf->cnt -= 2;
640 pkt_len += 1;
641
642
643 sksize = pkt_len;
644 skb = dev_alloc_skb(sksize);
645 if (skb == NULL) {
646 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
647 lp->stats.rx_dropped++;
648 restore_flags(flags);
649 return;
650 }
651 skb->dev = dev;
652
653
654 cfix=skb_put(skb,pkt_len);
655 *cfix++=0;
656
657 memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
658 skb->protocol=ntohs(ETH_P_AX25);
659 IS_SKB(skb);
660 netif_rx(skb);
661 lp->stats.rx_packets++;
662
663 lp->rcp = lp->rcvbuf->data;
664 lp->rcvbuf->cnt = 0;
665
666 }
667 }
668 lp->rstate = ACTIVE;
669 }
670 restore_flags(flags);
671 }
672
673
674 static void b_txint(struct pi_local *lp)
675 {
676 unsigned long flags;
677 int cmd;
678 unsigned char c;
679
680 save_flags(flags);
681 cli();
682 cmd = CTL + lp->base;
683
684 switch (lp->tstate) {
685 case CRCOUT:
686 lp->tstate = FLAGOUT;
687 tdelay(lp, lp->squeldelay);
688 restore_flags(flags);
689 return;
690 case IDLE:
691
692 if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
693
694
695
696 rts(lp, OFF);
697
698 restore_flags(flags);
699 return;
700 }
701 lp->txptr = lp->sndbuf->data;
702 lp->txptr++;
703 lp->txcnt = (int) lp->sndbuf->len - 1;
704
705 case DEFER:
706
707
708 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
709 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
710 if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
711 lp->tstate = DEFER;
712 tdelay(lp, 100);
713
714 wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
715 restore_flags(flags);
716 return;
717 }
718 if (random() > lp->persist) {
719 lp->tstate = DEFER;
720 tdelay(lp, lp->slotime);
721 restore_flags(flags);
722 return;
723 }
724 rts(lp, ON);
725 lp->tstate = ST_TXDELAY;
726 tdelay(lp, lp->txdelay);
727 restore_flags(flags);
728 return;
729
730 case ACTIVE:
731
732 if (lp->txcnt--) {
733 c = *lp->txptr++;
734
735 wrtscc(lp->cardbase, cmd, R8, c);
736
737 } else {
738
739 free_p(lp->sndbuf);
740 lp->sndbuf = NULL;
741 if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
742
743
744 lp->stats.tx_errors++;
745 lp->stats.tx_fifo_errors++;
746 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
747 lp->tstate = FLAGOUT;
748 tdelay(lp, lp->squeldelay);
749 restore_flags(flags);
750 return;
751 }
752 lp->tstate = UNDERRUN;
753
754 if (lp->speed) {
755 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
756 } else {
757 wrtscc(lp->cardbase, cmd, R10, CRCPS);
758 }
759 wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);
760 }
761 restore_flags(flags);
762 return;
763 }
764 restore_flags(flags);
765 }
766
767
768
769
770
771
772
773
774 static void b_exint(struct pi_local *lp)
775 {
776 unsigned long flags;
777 char st;
778 int cmd;
779 char c;
780
781 cmd = CTL + lp->base;
782 save_flags(flags);
783 cli();
784 st = rdscc(lp->cardbase, cmd, R0);
785
786 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
787
788
789 switch (lp->tstate) {
790 case ACTIVE:
791 free_p(lp->sndbuf);
792 lp->sndbuf = NULL;
793 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
794 lp->tstate = FLAGOUT;
795 lp->stats.tx_errors++;
796 lp->stats.tx_fifo_errors++;
797 tdelay(lp, lp->squeldelay);
798 restore_flags(flags);
799 return;
800 case UNDERRUN:
801 lp->tstate = CRCOUT;
802 restore_flags(flags);
803 return;
804 case FLAGOUT:
805
806 if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
807
808
809
810 rts(lp, OFF);
811 lp->tstate = IDLE;
812 restore_flags(flags);
813 return;
814 }
815 lp->txptr = lp->sndbuf->data;
816 lp->txptr++;
817 lp->txcnt = (int) lp->sndbuf->len - 1;
818
819 lp->txcnt--;
820 c = *lp->txptr++;
821 wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);
822
823
824 if (lp->speed) {
825 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
826 } else {
827 wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
828 }
829
830 wrtscc(lp->cardbase, cmd, R8, c);
831 wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
832
833 #ifdef STUFF2
834
835 if (lp->txcnt) {
836 lp->txcnt--;
837 c = *lp->txptr++;
838
839 while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
840 ;
841 wrtscc(lp->cardbase, cmd, R8, c);
842 }
843 #endif
844
845
846
847 wrtscc(lp->cardbase, cmd, R15, TxUIE);
848 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
849 wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
850
851 lp->tstate = ACTIVE;
852 restore_flags(flags);
853 return;
854
855 case DEFER:
856
857
858
859 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
860 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
861 if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
862 lp->tstate = DEFER;
863 tdelay(lp, 100);
864
865 wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
866 restore_flags(flags);
867 return;
868 }
869 if (random() > lp->persist) {
870 lp->tstate = DEFER;
871 tdelay(lp, lp->slotime);
872 restore_flags(flags);
873 return;
874 }
875 rts(lp, ON);
876 lp->tstate = ST_TXDELAY;
877 tdelay(lp, lp->txdelay);
878 restore_flags(flags);
879 return;
880
881 case ST_TXDELAY:
882
883
884 lp->txcnt--;
885 c = *lp->txptr++;
886 wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);
887
888
889 if (lp->speed) {
890 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
891 } else {
892 wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
893 }
894
895 wrtscc(lp->cardbase, cmd, R8, c);
896 wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
897
898 #ifdef STUFF2
899
900 if (lp->txcnt) {
901 lp->txcnt--;
902 c = *lp->txptr++;
903
904 while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
905 ;
906 wrtscc(lp->cardbase, cmd, R8, c);
907 }
908 #endif
909
910
911
912 wrtscc(lp->cardbase, cmd, R15, TxUIE);
913 wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
914
915 wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
916
917 lp->tstate = ACTIVE;
918 restore_flags(flags);
919 return;
920 }
921
922
923
924
925
926
927 if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
928 (void) rdscc(lp->cardbase, cmd, R8);
929 (void) rdscc(lp->cardbase, cmd, R8);
930 (void) rdscc(lp->cardbase, cmd, R8);
931 lp->rcp = lp->rcvbuf->data;
932 lp->rcvbuf->cnt = 0;
933 }
934 restore_flags(flags);
935 }
936
937
938
939
940 static int hw_probe(int ioaddr)
941 {
942 int time = 1000;
943 unsigned long start_time, end_time;
944
945 int base, tmr0, tmr1, tmrcmd;
946 int a = 1;
947 int b = 1;
948
949 base = ioaddr & 0x3f0;
950 tmr0 = TMR0 + base;
951 tmr1 = TMR1 + base;
952 tmrcmd = TMRCMD + base;
953
954
955
956 outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
957 outb_p(922 & 0xFF, tmr0);
958 outb_p(922 >> 8, tmr0);
959
960
961 outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
962 outb_p((time << 1) & 0xFF, tmr1);
963 outb_p((time >> 7) & 0XFF, tmr1);
964
965
966 do {
967
968 outb_p(SC1, tmrcmd);
969 a = inb_p(tmr1);
970 b = inb_p(tmr1);
971 } while (b == 0);
972 start_time = jiffies;
973 while (b != 0) {
974
975 outb_p(SC1, tmrcmd);
976 a = inb_p(tmr1);
977 b = inb_p(tmr1);
978 end_time = jiffies;
979
980 if ((end_time - start_time) > 200)
981 return 0;
982 }
983 end_time = jiffies;
984
985 if ((end_time - start_time) > 65) {
986 return (1);
987 } else {
988
989
990
991 outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
992 outb_p(1844 & 0xFF, tmr0);
993 outb_p(1844 >> 8, tmr0);
994 return (2);
995 }
996 }
997
998 static void rts(struct pi_local *lp, int x)
999 {
1000 int tc;
1001 long br;
1002 int cmd;
1003 int dummy;
1004
1005
1006 cmd = CTL + lp->base;
1007
1008
1009 if (x == ON) {
1010
1011 wrtscc(lp->cardbase, cmd, R15, 0);
1012 wrtscc(lp->cardbase, cmd, R3, Rx8);
1013 lp->rstate = IDLE;
1014 if (cmd & 2) {
1015
1016 wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1017 } else {
1018 wrtscc(lp->cardbase, cmd, R1, 0);
1019 }
1020
1021 if (!lp->clockmode) {
1022 if (lp->speed) {
1023 br = lp->speed;
1024 tc = (lp->xtal / br) - 2;
1025 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);
1026 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);
1027 }
1028 }
1029 wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1030
1031 } else {
1032 lp->tstate = IDLE;
1033 wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1034
1035 if (!lp->clockmode) {
1036 if (lp->speed) {
1037
1038
1039 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1040 br = lp->speed;
1041
1042 tc = ((lp->xtal / 32) / br) - 2;
1043 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);
1044 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);
1045
1046 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1047
1048 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1049 }
1050 }
1051
1052 wrtscc(lp->cardbase, cmd, R3, Rx8);
1053 wrtscc(lp->cardbase, cmd, R0, ERR_RES);
1054 dummy = rdscc(lp->cardbase, cmd, R1);
1055 (void) rdscc(lp->cardbase, cmd, R8);
1056 (void) rdscc(lp->cardbase, cmd, R8);
1057
1058 (void) rdscc(lp->cardbase, cmd, R8);
1059
1060
1061 wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1062 lp->rstate = ACTIVE;
1063
1064 if (cmd & 2) {
1065 setup_rx_dma(lp);
1066 } else {
1067
1068 lp->rcp = lp->rcvbuf->data;
1069 lp->rcvbuf->cnt = 0;
1070 wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1071 }
1072 wrtscc(lp->cardbase, cmd, R15, BRKIE);
1073 }
1074 }
1075
1076
1077 static int pi_header(struct sk_buff *skb, struct device *dev, unsigned short type,
1078 void *daddr, void *saddr, unsigned len)
1079 {
1080 return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
1081 }
1082
1083
1084 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
1085 struct sk_buff *skb)
1086 {
1087 return ax25_rebuild_header(buff, dev, raddr, skb);
1088 }
1089
1090 static void scc_init(struct device *dev)
1091 {
1092 unsigned long flags;
1093 struct pi_local *lp = (struct pi_local *) dev->priv;
1094
1095 int tc;
1096 long br;
1097 register int cmd;
1098
1099
1100
1101 cmd = CTL + lp->base;
1102 save_flags(flags);
1103 cli();
1104
1105 switch (cmd & CHANA) {
1106 case CHANA:
1107 wrtscc(lp->cardbase, cmd, R9, CHRA);
1108 wrtscc(lp->cardbase, cmd, R2, 0xff);
1109 break;
1110 default:
1111 wrtscc(lp->cardbase, cmd, R9, CHRB);
1112 break;
1113 }
1114
1115
1116 wrtscc(lp->cardbase, cmd, R1, 0);
1117
1118
1119 wrtscc(lp->cardbase, cmd, R15, 0);
1120
1121
1122 wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1123
1124
1125 if (lp->speed) {
1126 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1127 if (!lp->clockmode)
1128
1129 wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1130 else
1131
1132 wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1133 } else {
1134 wrtscc(lp->cardbase, cmd, R10, CRCPS);
1135
1136 wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1137 }
1138
1139
1140 wrtscc(lp->cardbase, cmd, R6, 0);
1141
1142
1143 wrtscc(lp->cardbase, cmd, R7, FLAG);
1144
1145
1146
1147
1148 wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1149
1150
1151 wrtscc(lp->cardbase, cmd, R3, Rx8);
1152
1153
1154 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1155
1156
1157
1158 if (lp->speed) {
1159 br = lp->speed;
1160 tc = ((lp->xtal / 32) / br) - 2;
1161 } else {
1162 tc = 14;
1163 }
1164
1165 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);
1166 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);
1167
1168
1169 rts(lp, OFF);
1170
1171 if (lp->speed) {
1172
1173 wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1174 } else {
1175
1176 wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1177 }
1178 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1179 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1180
1181 if (!(cmd & 2))
1182 wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1183
1184 wrtscc(lp->cardbase, cmd, R15, BRKIE);
1185
1186
1187 wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1188
1189 restore_flags(flags);
1190 }
1191
1192 static void chipset_init(struct device *dev)
1193 {
1194 int cardbase;
1195 unsigned long flags;
1196
1197 cardbase = dev->base_addr & 0x3f0;
1198
1199 save_flags(flags);
1200 cli();
1201 wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES);
1202
1203 wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1204 restore_flags(flags);
1205
1206 }
1207
1208
1209 unsigned long pi_init(unsigned long mem_start, unsigned long mem_end)
1210 {
1211 int *port;
1212 int ioaddr = 0;
1213 int card_type = 0;
1214 int ports[] =
1215 {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1216
1217 printk(version);
1218
1219
1220 for (port = &ports[0]; *port && !card_type; port++) {
1221 ioaddr = *port;
1222
1223 if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1224 printk("PI: Probing for card at address %#3x\n",ioaddr);
1225 card_type = hw_probe(ioaddr);
1226 }
1227 }
1228
1229 switch (card_type) {
1230 case 1:
1231 printk("PI: Found a PI card at address %#3x\n", ioaddr);
1232 break;
1233 case 2:
1234 printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1235 break;
1236 default:
1237 printk("PI: ERROR: No card found\n");
1238 return mem_start;
1239 }
1240
1241
1242
1243
1244
1245
1246
1247 register_netdev(&pi0a);
1248
1249 pi0a.priv=(void *)mem_start;
1250 mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1251 + 8;
1252
1253 pi0a.dma = PI_DMA;
1254 pi0a.base_addr = ioaddr + 2;
1255 pi0a.irq = 0;
1256
1257
1258 register_netdev(&pi0b);
1259 pi0b.base_addr = ioaddr;
1260 pi0b.irq = 0;
1261 pi0b.priv=(void *)mem_start;
1262 mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1263 + 8;
1264
1265
1266 pi_probe(&pi0a, card_type);
1267 pi_probe(&pi0b, card_type);
1268
1269 pi0b.irq = pi0a.irq;
1270
1271 return mem_start;
1272 }
1273
1274 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
1275 {
1276 if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1277 return 1;
1278 else
1279 return 0;
1280 }
1281
1282 static int pi_set_mac_address(struct device *dev, void *addr)
1283 {
1284 memcpy(dev->dev_addr, addr, 7);
1285 return 0;
1286 }
1287
1288
1289 static char *
1290 get_dma_buffer(unsigned long *mem_ptr)
1291 {
1292 char *ret;
1293
1294 ret = (char *)*mem_ptr;
1295
1296 if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1297 *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1298 ret = (char *)*mem_ptr;
1299 }
1300 *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1301 return (ret);
1302 }
1303
1304 static int pi_probe(struct device *dev, int card_type)
1305 {
1306 short ioaddr;
1307 struct pi_local *lp;
1308 int i;
1309 unsigned long flags;
1310 unsigned long mem_ptr;
1311
1312 ioaddr = dev->base_addr;
1313
1314
1315
1316
1317 dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1318 lp = (struct pi_local *) dev->priv;
1319
1320 memset(dev->priv, 0, sizeof(struct pi_local));
1321
1322
1323 mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1324 lp->txdmabuf = get_dma_buffer(&mem_ptr);
1325 lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1326 lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1327
1328
1329 lp->rcvbuf = lp->rxdmabuf1;
1330 lp->rcp = lp->rcvbuf->data;
1331 lp->rcvbuf->cnt = 0;
1332
1333
1334 skb_queue_head_init(&lp->sndq);
1335
1336
1337 if (card_type == 1)
1338 lp->xtal = (unsigned long) SINGLE / 2;
1339 else
1340 lp->xtal = (unsigned long) DOUBLE / 2;
1341 lp->base = dev->base_addr;
1342 lp->cardbase = dev->base_addr & 0x3f0;
1343 if (dev->base_addr & CHANA) {
1344 lp->speed = DEF_A_SPEED;
1345
1346 lp->txdelay = DEF_A_TXDELAY;
1347 lp->persist = DEF_A_PERSIST;
1348 lp->slotime = DEF_A_SLOTIME;
1349 lp->squeldelay = DEF_A_SQUELDELAY;
1350 lp->clockmode = DEF_A_CLOCKMODE;
1351
1352 } else {
1353 lp->speed = DEF_B_SPEED;
1354
1355 lp->txdelay = DEF_B_TXDELAY;
1356 lp->persist = DEF_B_PERSIST;
1357 lp->slotime = DEF_B_SLOTIME;
1358 lp->squeldelay = DEF_B_SQUELDELAY;
1359 lp->clockmode = DEF_B_CLOCKMODE;
1360 }
1361 lp->bufsiz = DMA_BUFF_SIZE;
1362 lp->tstate = IDLE;
1363
1364 chipset_init(dev);
1365
1366 if (dev->base_addr & CHANA) {
1367
1368
1369 lp->dmachan = dev->dma;
1370 if (lp->dmachan < 1 || lp->dmachan > 3)
1371 printk("PI: DMA channel %d out of range\n", lp->dmachan);
1372
1373
1374
1375 if (dev->irq < 2) {
1376 autoirq_setup(0);
1377 save_flags(flags);
1378 cli();
1379 wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1380
1381 wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1382 restore_flags(flags);
1383
1384 tdelay(lp, 1);
1385
1386 dev->irq = autoirq_report(20);
1387 if (!dev->irq) {
1388 printk(". Failed to detect IRQ line.\n");
1389 }
1390 save_flags(flags);
1391 cli();
1392 wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);
1393
1394 wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1395 restore_flags(flags);
1396 }
1397
1398 printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1399 dev->irq, dev->dma);
1400
1401
1402
1403
1404 {
1405 int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1406 if (irqval) {
1407 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1408 dev->irq, irqval);
1409 return EAGAIN;
1410 }
1411 }
1412
1413
1414 snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1415
1416
1417 }
1418 dev->open = pi_open;
1419 dev->stop = pi_close;
1420 dev->do_ioctl = pi_ioctl;
1421 dev->hard_start_xmit = pi_send_packet;
1422 dev->get_stats = pi_get_stats;
1423
1424
1425 for (i = 0; i < DEV_NUMBUFFS; i++)
1426 skb_queue_head_init(&dev->buffs[i]);
1427
1428
1429 dev->hard_header = pi_header;
1430 dev->rebuild_header = pi_rebuild_header;
1431 dev->set_mac_address = pi_set_mac_address;
1432
1433 dev->type = ARPHRD_AX25;
1434 dev->hard_header_len = 73;
1435 dev->mtu = 1500;
1436 dev->addr_len = 7;
1437 memcpy(dev->broadcast, ax25_bcast, 7);
1438 memcpy(dev->dev_addr, ax25_test, 7);
1439
1440
1441 dev->flags = 0;
1442 dev->family = AF_INET;
1443 dev->pa_addr = 0;
1444 dev->pa_brdaddr = 0;
1445 dev->pa_mask = 0;
1446 dev->pa_alen = 4;
1447
1448 return 0;
1449 }
1450
1451
1452
1453
1454
1455
1456
1457
1458 static int pi_open(struct device *dev)
1459 {
1460 unsigned long flags;
1461 static first_time = 1;
1462
1463 struct pi_local *lp = (struct pi_local *) dev->priv;
1464
1465 if (dev->base_addr & 2) {
1466 if (first_time) {
1467 if (request_dma(dev->dma,"pi2")) {
1468 free_irq(dev->irq);
1469 return -EAGAIN;
1470 }
1471 irq2dev_map[dev->irq] = dev;
1472 }
1473
1474 chipset_init(dev);
1475 }
1476 lp->tstate = IDLE;
1477
1478 if (dev->base_addr & 2) {
1479 scc_init(dev);
1480 scc_init(dev->next);
1481 }
1482
1483 save_flags(flags);
1484 cli();
1485 wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1486 restore_flags(flags);
1487
1488 lp->open_time = jiffies;
1489
1490 dev->tbusy = 0;
1491 dev->interrupt = 0;
1492 dev->start = 1;
1493 first_time = 0;
1494 return 0;
1495 }
1496
1497 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
1498 {
1499 struct pi_local *lp = (struct pi_local *) dev->priv;
1500
1501
1502
1503
1504 if (skb == NULL) {
1505 dev_tint(dev);
1506 return 0;
1507 }
1508 hardware_send_packet(lp, skb);
1509 dev->trans_start = jiffies;
1510
1511 return 0;
1512 }
1513
1514
1515
1516 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
1517 {
1518
1519 struct pi_local *lp;
1520 int st;
1521 unsigned long flags;
1522
1523
1524
1525 #if 0
1526 if (dev_a == NULL) {
1527 printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1528 return;
1529 }
1530 #endif
1531
1532
1533
1534 lp = (struct pi_local *) pi0a.priv;
1535 while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1536 if (st & CHBTxIP) {
1537
1538 lp = (struct pi_local *) pi0b.priv;
1539 b_txint(lp);
1540 } else if (st & CHARxIP) {
1541
1542 lp = (struct pi_local *) pi0a.priv;
1543 a_rxint(&pi0a, lp);
1544 } else if (st & CHATxIP) {
1545
1546 lp = (struct pi_local *) pi0a.priv;
1547 a_txint(lp);
1548 } else if (st & CHAEXT) {
1549
1550 lp = (struct pi_local *) pi0a.priv;
1551 a_exint(lp);
1552 } else if (st & CHBRxIP) {
1553
1554 lp = (struct pi_local *) pi0b.priv;
1555 b_rxint(&pi0b, lp);
1556 } else if (st & CHBEXT) {
1557
1558 lp = (struct pi_local *) pi0b.priv;
1559 b_exint(lp);
1560 }
1561
1562 save_flags(flags);
1563 cli();
1564 wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1565 restore_flags(flags);
1566 }
1567 return;
1568 }
1569
1570
1571 static int pi_close(struct device *dev)
1572 {
1573 unsigned long flags;
1574 struct pi_local *lp;
1575 struct sk_buff *ptr;
1576
1577 save_flags(flags);
1578 cli();
1579
1580 lp = (struct pi_local *) dev->priv;
1581 ptr = NULL;
1582
1583 chipset_init(dev);
1584 disable_dma(lp->dmachan);
1585
1586 lp->open_time = 0;
1587
1588 dev->tbusy = 1;
1589 dev->start = 0;
1590
1591
1592 while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1593 free_p(ptr);
1594
1595 restore_flags(flags);
1596 return 0;
1597 }
1598
1599 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
1600 {
1601 unsigned long flags;
1602 struct pi_req rq;
1603 struct pi_local *lp = (struct pi_local *) dev->priv;
1604
1605 int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1606 if (ret)
1607 return ret;
1608
1609 if(cmd!=SIOCDEVPRIVATE)
1610 return -EINVAL;
1611
1612 memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1613
1614 switch (rq.cmd) {
1615 case SIOCSPIPARAM:
1616
1617 if (!suser())
1618 return -EPERM;
1619 save_flags(flags);
1620 cli();
1621 lp->txdelay = rq.txdelay;
1622 lp->persist = rq.persist;
1623 lp->slotime = rq.slotime;
1624 lp->squeldelay = rq.squeldelay;
1625 lp->clockmode = rq.clockmode;
1626 lp->speed = rq.speed;
1627 pi_open(&pi0a);
1628 restore_flags(flags);
1629 ret = 0;
1630 break;
1631
1632 case SIOCSPIDMA:
1633
1634 if (!suser())
1635 return -EPERM;
1636 ret = 0;
1637 if (dev->base_addr & 2) {
1638 if (rq.dmachan < 1 || rq.dmachan > 3)
1639 return -EINVAL;
1640 save_flags(flags);
1641 cli();
1642 pi_close(dev);
1643 free_dma(lp->dmachan);
1644 dev->dma = lp->dmachan = rq.dmachan;
1645 if (request_dma(lp->dmachan,"pi2"))
1646 ret = -EAGAIN;
1647 pi_open(dev);
1648 restore_flags(flags);
1649 }
1650 break;
1651
1652 case SIOCSPIIRQ:
1653 ret = -EINVAL;
1654 break;
1655
1656 case SIOCGPIPARAM:
1657 case SIOCGPIDMA:
1658 case SIOCGPIIRQ:
1659
1660 rq.speed = lp->speed;
1661 rq.txdelay = lp->txdelay;
1662 rq.persist = lp->persist;
1663 rq.slotime = lp->slotime;
1664 rq.squeldelay = lp->squeldelay;
1665 rq.clockmode = lp->clockmode;
1666 rq.dmachan = lp->dmachan;
1667 rq.irq = dev->irq;
1668 memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1669 ret = 0;
1670 break;
1671
1672 default:
1673 ret = -EINVAL;
1674 }
1675 return ret;
1676 }
1677
1678
1679
1680 static struct netstats *
1681 pi_get_stats(struct device *dev)
1682 {
1683 struct pi_local *lp = (struct pi_local *) dev->priv;
1684
1685 return &lp->stats;
1686 }
1687
1688
1689
1690
1691
1692
1693
1694
1695
1696