root/drivers/pci/pci.c

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DEFINITIONS

This source file includes following definitions.
  1. pci_lookup_dev
  2. pci_strbioserr
  3. pci_strclass
  4. pci_strvendor
  5. pci_strdev
  6. burst_bridge
  7. sprint_dev_config
  8. get_pci_list
  9. pci_malloc
  10. scan_bus
  11. pci_init

   1 /*
   2  * drivers/pci/pci.c
   3  *
   4  * PCI services that are built on top of the BIOS32 service.
   5  *
   6  * Copyright 1993, 1994, 1995 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  */
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/bios32.h>
  13 #include <linux/pci.h>
  14 #include <linux/string.h>
  15 
  16 #include <asm/page.h>
  17 
  18 struct pci_bus pci_root;
  19 struct pci_dev *pci_devices = 0;
  20 
  21 
  22 /* 
  23  * The bridge_id field is an offset of an item into the array
  24  * BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI
  25  * bridge, or that we don't know for the moment how to configure it.
  26  * I'm trying to do my best so that the kernel stays small.  Different
  27  * chipset can have same optimization structure. i486 and pentium
  28  * chipsets from the same manufacturer usually have the same
  29  * structure.
  30  */
  31 #define DEVICE(vid,did,name) \
  32   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
  33 
  34 #define BRIDGE(vid,did,name,bridge) \
  35   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
  36 
  37 struct pci_dev_info dev_info[] = {
  38         DEVICE( NCR,            NCR_53C810,     "53c810"),
  39         DEVICE( NCR,            NCR_53C815,     "53c815"),
  40         DEVICE( NCR,            NCR_53C820,     "53c820"),
  41         DEVICE( NCR,            NCR_53C825,     "53c825"),
  42         DEVICE( ADAPTEC,        ADAPTEC_2940,   "2940"),
  43         DEVICE( ADAPTEC,        ADAPTEC_294x,   "294x"),
  44         DEVICE( ADAPTEC,        ADAPTEC_7850,   "AIC-7850"),
  45         DEVICE( DPT,            DPT,            "SmartCache/Raid"),
  46         DEVICE( S3,             S3_864_1,       "Vision 864-P"),
  47         DEVICE( S3,             S3_864_2,       "Vision 864-P"),
  48         DEVICE( S3,             S3_868, "Vision 868"),
  49         DEVICE( S3,             S3_928,         "Vision 928-P"),
  50         DEVICE( S3,             S3_964_1,       "Vision 964-P"),
  51         DEVICE( S3,             S3_964_2,       "Vision 964-P"),
  52         DEVICE( S3,             S3_811,         "Trio32/Trio64"),
  53         DEVICE( S3,             S3_968,         "Vision 968"),
  54         DEVICE( OPTI,           OPTI_82C822,    "82C822"),
  55         DEVICE( OPTI,           OPTI_82C621,    "82C621"),
  56         DEVICE( OPTI,           OPTI_82C557,    "82C557"),
  57         DEVICE( OPTI,           OPTI_82C558,    "82C558"),
  58         BRIDGE( UMC,            UMC_UM8881F,    "UM8881F",              0x02),
  59         BRIDGE( UMC,            UMC_UM8891A,    "UM8891A",              0x01),
  60         DEVICE( UMC,            UMC_UM8886F,    "UM8886F"),
  61         DEVICE( UMC,            UMC_UM8886A,    "UM8886A"),
  62         DEVICE( UMC,            UMC_UM8673F,    "UM8673F"),
  63         DEVICE( DEC,            DEC_TULIP,      "DC21040"),
  64         DEVICE( DEC,            DEC_TULIP_FAST, "DC21140"),
  65         DEVICE( DEC,            DEC_TULIP_PLUS, "DC21041"),
  66         DEVICE( DEC,            DEC_FDDI,       "DEFPA"),
  67         DEVICE( DEC,            DEC_BRD,        "DC21050"),
  68         DEVICE( MATROX,         MATROX_MGA_2,   "Atlas PX2085"),
  69         DEVICE( MATROX,         MATROX_MGA_IMP, "MGA Impression"),
  70         DEVICE( INTEL,          INTEL_82378,    "82378IB"),
  71         BRIDGE( INTEL,          INTEL_82424,    "82424ZX Saturn",       0x00),
  72         DEVICE( INTEL,          INTEL_82375,    "82375EB"),
  73         BRIDGE( INTEL,          INTEL_82434,    "82434LX Mercury/Neptune", 0x00),
  74         DEVICE( INTEL,          INTEL_82430,    "82430ZX Aries"),
  75         DEVICE( INTEL,          INTEL_82437,    "82437 Triton"),
  76         DEVICE( INTEL,          INTEL_82371,    "82471 Triton"),
  77         DEVICE( INTEL,          INTEL_82438,    "82438"),
  78         DEVICE( INTEL,          INTEL_7116,     "SAA7116"),
  79         DEVICE( SMC,            SMC_37C665,     "FDC 37C665"),
  80         DEVICE( ATI,            ATI_M32,        "Mach 32"),
  81         DEVICE( ATI,            ATI_M64,        "Mach 64"),
  82         DEVICE( WEITEK,         WEITEK_P9000,   "P9000"),
  83         DEVICE( WEITEK,         WEITEK_P9100,   "P9100"),
  84         DEVICE( CIRRUS,         CIRRUS_5430,    "GD 5430"),
  85         DEVICE( CIRRUS,         CIRRUS_5434_4,  "GD 5434"),
  86         DEVICE( CIRRUS,         CIRRUS_5434_8,  "GD 5434"),
  87         DEVICE( CIRRUS,         CIRRUS_6729,    "CL 6729"),
  88         DEVICE( CIRRUS,         CIRRUS_7542,    "CL 7542"),
  89         DEVICE( BUSLOGIC,       BUSLOGIC_946C,  "946C"),
  90         DEVICE( BUSLOGIC,       BUSLOGIC_946C_2,"946C"),
  91         DEVICE( N9,             N9_I128,        "Imagine 128"),
  92         DEVICE( AI,             AI_M1435,       "M1435"),
  93         DEVICE( AL,             AL_M1445,       "M1445"),
  94         DEVICE( AL,             AL_M1449,       "M1449"),
  95         DEVICE( AL,             AL_M1451,       "M1451"),
  96         DEVICE( AL,             AL_M4803,       "M4803"),
  97         DEVICE( TSENG,          TSENG_W32P_2,   "ET4000W32P"),
  98         DEVICE( TSENG,          TSENG_W32P_b,   "ET4000W32P rev B"),
  99         DEVICE( TSENG,          TSENG_W32P_c,   "ET4000W32P rev C"),
 100         DEVICE( TSENG,          TSENG_W32P_d,   "ET4000W32P rev D"),
 101         DEVICE( CMD,            CMD_640,        "640A"),
 102         DEVICE( VISION,         VISION_QD8500,  "QD-8500"),
 103         DEVICE( VISION,         VISION_QD8580,  "QD-8580"),
 104         DEVICE( AMD,            AMD_LANCE,      "79C970"),
 105         DEVICE( AMD,            AMD_SCSI,       "53C974"),
 106         DEVICE( VLSI,           VLSI_82C593,    "82C593-FC1"),
 107         DEVICE( VLSI,           VLSI_82C592,    "82C592-FC1"),
 108         DEVICE( ADL,            ADL_2301,       "2301"),
 109         DEVICE( SYMPHONY,       SYMPHONY_101,   "82C101"),
 110         DEVICE( TRIDENT,        TRIDENT_9420,   "TG 9420"),
 111         DEVICE( TRIDENT,        TRIDENT_9440,   "TG 9440"),
 112         DEVICE( CONTAQ,         CONTAQ_82C599,  "82C599"),
 113         DEVICE( NS,             NS_87410,       "87410"),
 114         DEVICE( VIA,            VIA_82C505,     "VT 82C505"),
 115         DEVICE( VIA,            VIA_82C576,     "VT 82C576 3V"),
 116         DEVICE( VIA,            VIA_82C561,     "VT 82C561"),
 117         DEVICE( SI,             SI_496,         "85C496"),
 118         DEVICE( SI,             SI_501,         "85C501"),
 119         DEVICE( SI,             SI_503,         "85C503"),
 120         DEVICE( SI,             SI_601,         "85C601"),
 121         DEVICE( LEADTEK,        LEADTEK_805,    "S3 805"),
 122         DEVICE( IMS,            IMS_8849,       "8849"),
 123         DEVICE( ZEINET,         ZEINET_1221,    "1221"),
 124         DEVICE( EF,             EF_ATM,         "155P-MF1"),
 125         DEVICE( HER,            HER_STING,      "Stingray"),
 126         DEVICE( ATRONICS,       ATRONICS_2015,  "IDE-2015PL"),
 127         DEVICE( CT,             CT_65545,       "65545"),
 128         DEVICE( FD,             FD_36C70,       "TMC-18C30"),
 129         DEVICE( WINBOND,        WINBOND_83769,  "W83769F"),
 130         DEVICE( 3COM,           3COM_3C590,     "3C590 10bT"),
 131         DEVICE( 3COM,           3COM_3C595TX,   "3C595 100bTX"),
 132         DEVICE( 3COM,           3COM_3C595T4,   "3C595 100bT4"),
 133         DEVICE( 3COM,           3COM_3C595MII,  "3C595 100b-MII"),
 134         DEVICE( PROMISE,        PROMISE_5300,   "DC5030"),
 135         DEVICE( QLOGIC,         QLOGIC_ISP1020, "ISP1020"),
 136         DEVICE( QLOGIC,         QLOGIC_ISP1022, "ISP1022"),
 137         DEVICE( X,              X_AGX016,       "ITT AGX016"),
 138         DEVICE( VORTEX,         VORTEX_GDT,     "GDT 6000b"),
 139         DEVICE( HP,             HP_J2585A,      "J2585A")
 140 };
 141 
 142 
 143 #ifdef CONFIG_PCI_OPTIMIZE
 144 
 145 /*
 146  * An item of this structure has the following meaning:
 147  * for each optimization, the register address, the mask
 148  * and value to write to turn it on.
 149  * There are 5 optimizations for the moment:
 150  * Cache L2 write back best than write through
 151  * Posted Write for CPU to PCI enable
 152  * Posted Write for CPU to MEMORY enable
 153  * Posted Write for PCI to MEMORY enable
 154  * PCI Burst enable
 155  *
 156  * Half of the bios I've meet don't allow you to turn that on, and you
 157  * can gain more than 15% on graphic accesses using those
 158  * optimizations...
 159  */
 160 struct optimization_type {
 161         const char      *type;
 162         const char      *off;
 163         const char      *on;
 164 } bridge_optimization[] = {
 165         {"Cache L2",                    "write trough", "write back"},
 166         {"CPU-PCI posted write",        "off",          "on"},
 167         {"CPU-Memory posted write",     "off",          "on"},
 168         {"PCI-Memory posted write",     "off",          "on"},
 169         {"PCI burst",                   "off",          "on"}
 170 };
 171 
 172 #define NUM_OPTIMIZATIONS \
 173         (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
 174 
 175 struct bridge_mapping_type {
 176         unsigned char   addr;   /* config space address */
 177         unsigned char   mask;
 178         unsigned char   value;
 179 } bridge_mapping[] = {
 180         /*
 181          * Intel Neptune/Mercury/Saturn:
 182          *      If the internal cache is write back,
 183          *      the L2 cache must be write through!
 184          *      I've to check out how to control that
 185          *      for the moment, we won't touch the cache
 186          */
 187         {0x0    ,0x02   ,0x02   },
 188         {0x53   ,0x02   ,0x02   },
 189         {0x53   ,0x01   ,0x01   },
 190         {0x54   ,0x01   ,0x01   },
 191         {0x54   ,0x02   ,0x02   },
 192 
 193         /*
 194          * UMC 8891A Pentium chipset:
 195          *      Why did you think UMC was cheaper ??
 196          */
 197         {0x50   ,0x10   ,0x00   },
 198         {0x51   ,0x40   ,0x40   },
 199         {0x0    ,0x0    ,0x0    },
 200         {0x0    ,0x0    ,0x0    },
 201         {0x0    ,0x0    ,0x0    },
 202 
 203         /*
 204          * UMC UM8881F
 205          *      This is a dummy entry for my tests.
 206          *      I have this chipset and no docs....
 207          */
 208         {0x0    ,0x1    ,0x1    },
 209         {0x0    ,0x2    ,0x0    },
 210         {0x0    ,0x0    ,0x0    },
 211         {0x0    ,0x0    ,0x0    },
 212         {0x0    ,0x0    ,0x0    }
 213 };
 214 
 215 #endif /* CONFIG_PCI_OPTIMIZE */
 216 
 217 
 218 /*
 219  * If performance ever becomes important, device_info[] could be
 220  * sorted by key and this could be replaced by a binary search.
 221  */
 222 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
     /* [previous][next][first][last][top][bottom][index][help] */
 223 {
 224         int i;
 225 
 226         for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
 227                 if (dev_info[i].vendor == vendor &&
 228                     dev_info[i].device == dev)
 229                 {
 230                         return &dev_info[i];
 231                 }
 232         }
 233         return 0;
 234 }
 235 
 236 
 237 const char *pci_strbioserr (int error)
     /* [previous][next][first][last][top][bottom][index][help] */
 238 {
 239         switch (error) {
 240               case PCIBIOS_SUCCESSFUL:          return "SUCCESSFUL";
 241               case PCIBIOS_FUNC_NOT_SUPPORTED:  return "FUNC_NOT_SUPPORTED";
 242               case PCIBIOS_BAD_VENDOR_ID:       return "SUCCESSFUL";
 243               case PCIBIOS_DEVICE_NOT_FOUND:    return "DEVICE_NOT_FOUND";
 244               case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
 245               case PCIBIOS_SET_FAILED:          return "SET_FAILED";
 246               case PCIBIOS_BUFFER_TOO_SMALL:    return "BUFFER_TOO_SMALL";
 247               default:                          return "Unknown error status";
 248         }
 249 }
 250 
 251 
 252 const char *pci_strclass (unsigned int class)
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 253 {
 254         switch (class >> 8) {
 255               case PCI_CLASS_NOT_DEFINED:               return "Non-VGA device";
 256               case PCI_CLASS_NOT_DEFINED_VGA:           return "VGA compatible device";
 257 
 258               case PCI_CLASS_STORAGE_SCSI:              return "SCSI storage controller";
 259               case PCI_CLASS_STORAGE_IDE:               return "IDE controller";
 260               case PCI_CLASS_STORAGE_FLOPPY:            return "Floppy disk controller";
 261               case PCI_CLASS_STORAGE_IPI:               return "IPI bus controller";
 262               case PCI_CLASS_STORAGE_OTHER:             return "Unknown mass storage controller";
 263 
 264               case PCI_CLASS_NETWORK_ETHERNET:          return "Ethernet controller";
 265               case PCI_CLASS_NETWORK_TOKEN_RING:        return "Token ring network controller";
 266               case PCI_CLASS_NETWORK_FDDI:              return "FDDI network controller";
 267               case PCI_CLASS_NETWORK_OTHER:             return "Network controller";
 268 
 269               case PCI_CLASS_DISPLAY_VGA:               return "VGA compatible controller";
 270               case PCI_CLASS_DISPLAY_XGA:               return "XGA compatible controller";
 271               case PCI_CLASS_DISPLAY_OTHER:             return "Display controller";
 272 
 273               case PCI_CLASS_MULTIMEDIA_VIDEO:          return "Multimedia video controller";
 274               case PCI_CLASS_MULTIMEDIA_AUDIO:          return "Multimedia audio controller";
 275               case PCI_CLASS_MULTIMEDIA_OTHER:          return "Multimedia controller";
 276 
 277               case PCI_CLASS_MEMORY_RAM:                return "RAM memory";
 278               case PCI_CLASS_MEMORY_FLASH:              return "FLASH memory";
 279               case PCI_CLASS_MEMORY_OTHER:              return "Memory";
 280 
 281               case PCI_CLASS_BRIDGE_HOST:               return "Host bridge";
 282               case PCI_CLASS_BRIDGE_ISA:                return "ISA bridge";
 283               case PCI_CLASS_BRIDGE_EISA:               return "EISA bridge";
 284               case PCI_CLASS_BRIDGE_MC:                 return "MicroChannel bridge";
 285               case PCI_CLASS_BRIDGE_PCI:                return "PCI bridge";
 286               case PCI_CLASS_BRIDGE_PCMCIA:             return "PCMCIA bridge";
 287               case PCI_CLASS_BRIDGE_OTHER:              return "Bridge";
 288 
 289               default:                                  return "Unknown class";
 290         }
 291 }
 292 
 293 
 294 const char *pci_strvendor(unsigned int vendor)
     /* [previous][next][first][last][top][bottom][index][help] */
 295 {
 296         switch (vendor) {
 297               case PCI_VENDOR_ID_NCR:           return "NCR";
 298               case PCI_VENDOR_ID_ADAPTEC:       return "Adaptec";
 299               case PCI_VENDOR_ID_DPT:           return "DPT";
 300               case PCI_VENDOR_ID_S3:            return "S3 Inc.";
 301               case PCI_VENDOR_ID_OPTI:          return "OPTI";
 302               case PCI_VENDOR_ID_UMC:           return "UMC";
 303               case PCI_VENDOR_ID_DEC:           return "DEC";
 304               case PCI_VENDOR_ID_MATROX:        return "Matrox";
 305               case PCI_VENDOR_ID_INTEL:         return "Intel";
 306               case PCI_VENDOR_ID_SMC:           return "SMC";
 307               case PCI_VENDOR_ID_ATI:           return "ATI";
 308               case PCI_VENDOR_ID_WEITEK:        return "Weitek";
 309               case PCI_VENDOR_ID_CIRRUS:        return "Cirrus Logic";
 310               case PCI_VENDOR_ID_BUSLOGIC:      return "Bus Logic";
 311               case PCI_VENDOR_ID_N9:            return "Number Nine";
 312               case PCI_VENDOR_ID_AI:            return "Acer Incorporated";
 313               case PCI_VENDOR_ID_AL:            return "Acer Labs";
 314               case PCI_VENDOR_ID_TSENG:         return "Tseng'Lab";
 315               case PCI_VENDOR_ID_CMD:           return "CMD";
 316               case PCI_VENDOR_ID_VISION:        return "Vision";
 317               case PCI_VENDOR_ID_AMD:           return "AMD";
 318               case PCI_VENDOR_ID_VLSI:          return "VLSI";
 319               case PCI_VENDOR_ID_ADL:           return "Advance Logic";
 320               case PCI_VENDOR_ID_SYMPHONY:      return "Symphony";
 321               case PCI_VENDOR_ID_TRIDENT:       return "Trident";
 322               case PCI_VENDOR_ID_CONTAQ:        return "Contaq";
 323               case PCI_VENDOR_ID_NS:            return "NS";
 324               case PCI_VENDOR_ID_VIA:           return "VIA Technologies";
 325               case PCI_VENDOR_ID_SI:            return "Silicon Integrated Systems";
 326               case PCI_VENDOR_ID_LEADTEK:       return "Leadtek Research";
 327               case PCI_VENDOR_ID_IMS:           return "IMS";
 328               case PCI_VENDOR_ID_ZEINET:        return "ZeiNet";
 329               case PCI_VENDOR_ID_EF:            return "Efficient Networks";
 330               case PCI_VENDOR_ID_HER:           return "Hercules";
 331               case PCI_VENDOR_ID_ATRONICS:      return "Atronics";
 332               case PCI_VENDOR_ID_CT:            return "Chips & Technologies";
 333               case PCI_VENDOR_ID_FD:            return "Future Domain";
 334               case PCI_VENDOR_ID_WINBOND:       return "Winbond";
 335               case PCI_VENDOR_ID_3COM:          return "3Com";
 336               case PCI_VENDOR_ID_PROMISE:       return "Promise Technology";
 337               case PCI_VENDOR_ID_QLOGIC:        return "Q Logic";
 338               case PCI_VENDOR_ID_X:             return "X TECHNOLOGY";
 339               case PCI_VENDOR_ID_ACC:           return "ACC MICROELECTRONICS";
 340               case PCI_VENDOR_ID_VORTEX:        return "VORTEX";
 341               case PCI_VENDOR_ID_HP:            return "Hewlett Packard";
 342               default:                          return "Unknown vendor";
 343         }
 344 }
 345 
 346 
 347 const char *pci_strdev(unsigned int vendor, unsigned int device) 
     /* [previous][next][first][last][top][bottom][index][help] */
 348 {
 349         struct pci_dev_info *info;
 350 
 351         info =  pci_lookup_dev(vendor, device);
 352         return info ? info->name : "Unknown device";
 353 }
 354 
 355 
 356 
 357 /*
 358  * Turn on/off PCI bridge optimization. This should allow benchmarking.
 359  */
 360 static void burst_bridge(unsigned char bus, unsigned char devfn,
     /* [previous][next][first][last][top][bottom][index][help] */
 361                          unsigned char pos, int turn_on)
 362 {
 363 #ifdef CONFIG_PCI_OPTIMIZE
 364         struct bridge_mapping_type *bmap;
 365         unsigned char val;
 366         int i;
 367 
 368         pos *= NUM_OPTIMIZATIONS;
 369         printk("PCI bridge optimization.\n");
 370         for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
 371                 printk("    %s: ", bridge_optimization[i].type);
 372                 bmap = &bridge_mapping[pos + i];
 373                 if (!bmap->addr) {
 374                         printk("Not supported.");
 375                 } else {
 376                         pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
 377                         if ((val & bmap->mask) == bmap->value) {
 378                                 printk("%s.", bridge_optimization[i].on);
 379                                 if (!turn_on) {
 380                                         pcibios_write_config_byte(bus, devfn,
 381                                                                   bmap->addr,
 382                                                                   (val | bmap->mask)
 383                                                                   - bmap->value);
 384                                         printk("Changed!  Now %s.", bridge_optimization[i].off);
 385                                 }
 386                         } else {
 387                                 printk("%s.", bridge_optimization[i].off);
 388                                 if (turn_on) {
 389                                         pcibios_write_config_byte(bus, devfn,
 390                                                                   bmap->addr,
 391                                                                   (val & (0xff - bmap->mask))
 392                                                                   + bmap->value);
 393                                         printk("Changed!  Now %s.", bridge_optimization[i].on);
 394                                 }
 395                         }
 396                 }
 397                 printk("\n");
 398         }
 399 #endif /* CONFIG_PCI_OPTIMIZE */
 400 }
 401 
 402 
 403 /*
 404  * Convert some of the configuration space registers of the device at
 405  * address (bus,devfn) into a string (possibly several lines each).
 406  * The configuration string is stored starting at buf[len].  If the
 407  * string would exceed the size of the buffer (SIZE), 0 is returned.
 408  */
 409 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
     /* [previous][next][first][last][top][bottom][index][help] */
 410 {
 411         unsigned long base;
 412         unsigned int l, class_rev, bus, devfn;
 413         unsigned short vendor, device, status;
 414         unsigned char bist, latency, min_gnt, max_lat;
 415         int reg, len = 0;
 416         const char *str;
 417 
 418         bus   = dev->bus->number;
 419         devfn = dev->devfn;
 420 
 421         pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
 422         pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
 423         pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
 424         pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
 425         pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
 426         pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
 427         pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
 428         pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
 429         if (len + 80 > size) {
 430                 return -1;
 431         }
 432         len += sprintf(buf + len, "  Bus %2d, device %3d, function %2d:\n",
 433                        bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
 434 
 435         if (len + 80 > size) {
 436                 return -1;
 437         }
 438         len += sprintf(buf + len, "    %s: %s %s (rev %d).\n      ",
 439                        pci_strclass(class_rev >> 8), pci_strvendor(vendor),
 440                        pci_strdev(vendor, device), class_rev & 0xff);
 441 
 442         if (!pci_lookup_dev(vendor, device)) {
 443                 len += sprintf(buf + len,
 444                                "Vendor id=%x. Device id=%x.\n      ",
 445                                vendor, device);
 446         }
 447 
 448         str = 0;        /* to keep gcc shut... */
 449         switch (status & PCI_STATUS_DEVSEL_MASK) {
 450               case PCI_STATUS_DEVSEL_FAST:   str = "Fast devsel.  "; break;
 451               case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel.  "; break;
 452               case PCI_STATUS_DEVSEL_SLOW:   str = "Slow devsel.  "; break;
 453         }
 454         if (len + strlen(str) > size) {
 455                 return -1;
 456         }
 457         len += sprintf(buf + len, str);
 458 
 459         if (status & PCI_STATUS_FAST_BACK) {
 460 #               define fast_b2b_capable "Fast back-to-back capable.  "
 461                 if (len + strlen(fast_b2b_capable) > size) {
 462                         return -1;
 463                 }
 464                 len += sprintf(buf + len, fast_b2b_capable);
 465 #               undef fast_b2b_capable
 466         }
 467 
 468         if (bist & PCI_BIST_CAPABLE) {
 469 #               define BIST_capable     "BIST capable.  "
 470                 if (len + strlen(BIST_capable) > size) {
 471                         return -1;
 472                 }
 473                 len += sprintf(buf + len, BIST_capable);
 474 #               undef BIST_capable
 475         }
 476 
 477         if (dev->irq) {
 478                 if (len + 40 > size) {
 479                         return -1;
 480                 }
 481                 len += sprintf(buf + len, "IRQ %d.  ", dev->irq);
 482         }
 483 
 484         if (dev->master) {
 485                 if (len + 80 > size) {
 486                         return -1;
 487                 }
 488                 len += sprintf(buf + len, "Master Capable.  ");
 489                 if (latency)
 490                   len += sprintf(buf + len, "Latency=%d.  ", latency); 
 491                 else
 492                   len += sprintf(buf + len, "No bursts.  ");
 493                 if (min_gnt)
 494                   len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
 495                 if (max_lat)
 496                   len += sprintf(buf + len, "Max Lat=%d.", max_lat);
 497         }
 498 
 499         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 500                 if (len + 40 > size) {
 501                         return -1;
 502                 }
 503                 pcibios_read_config_dword(bus, devfn, reg, &l);
 504                 base = l;
 505                 if (!base) {
 506                         continue;
 507                 }
 508 
 509                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 510                         len += sprintf(buf + len,
 511                                        "\n      I/O at 0x%lx.",
 512                                        base & PCI_BASE_ADDRESS_IO_MASK);
 513                 } else {
 514                         const char *pref, *type = "unknown";
 515 
 516                         if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 517                                 pref = "P";
 518                         } else {
 519                                 pref = "Non-p";
 520                         }
 521                         switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
 522                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 523                                 type = "32 bit"; break;
 524                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 525                                 type = "20 bit"; break;
 526                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 527                                 type = "64 bit";
 528                                 /* read top 32 bit address of base addr: */
 529                                 reg += 4;
 530                                 pcibios_read_config_dword(bus, devfn, reg, &l);
 531                                 base |= ((u64) l) << 32;
 532                                 break;
 533                         }
 534                         len += sprintf(buf + len,
 535                                        "\n      %srefetchable %s memory at "
 536                                        "0x%lx.", pref, type,
 537                                        base & PCI_BASE_ADDRESS_MEM_MASK);
 538                 }
 539         }
 540 
 541         len += sprintf(buf + len, "\n");
 542         return len;
 543 }
 544 
 545 
 546 /*
 547  * Return list of PCI devices as a character string for /proc/pci.
 548  * BUF is a buffer that is PAGE_SIZE bytes long.
 549  */
 550 int get_pci_list(char *buf)
     /* [previous][next][first][last][top][bottom][index][help] */
 551 {
 552         int nprinted, len, size;
 553         struct pci_dev *dev;
 554 #       define MSG "\nwarning: page-size limit reached!\n"
 555 
 556         /* reserve same for truncation warning message: */
 557         size  = PAGE_SIZE - (strlen(MSG) + 1);
 558         len   = sprintf(buf, "PCI devices found:\n");
 559 
 560         for (dev = pci_devices; dev; dev = dev->next) {
 561                 nprinted = sprint_dev_config(dev, buf + len, size - len);
 562                 if (nprinted < 0) {
 563                         return len + sprintf(buf + len, MSG);
 564                 }
 565                 len += nprinted;
 566         }
 567         return len;
 568 }
 569 
 570 
 571 /*
 572  * pci_malloc() returns initialized memory of size SIZE.  Can be
 573  * used only while pci_init() is active.
 574  */
 575 static void *pci_malloc(long size, unsigned long *mem_startp)
     /* [previous][next][first][last][top][bottom][index][help] */
 576 {
 577         void *mem;
 578 
 579 #ifdef DEBUG
 580         printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
 581 #endif
 582         mem = (void*) *mem_startp;
 583         *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
 584         memset(mem, 0, size);
 585         return mem;
 586 }
 587 
 588 
 589 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
     /* [previous][next][first][last][top][bottom][index][help] */
 590 {
 591         unsigned int devfn, l, max;
 592         unsigned char cmd, tmp, hdr_type = 0;
 593         struct pci_dev_info *info;
 594         struct pci_dev *dev;
 595         struct pci_bus *child;
 596 
 597 #ifdef DEBUG
 598         printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
 599 #endif
 600 
 601         max = bus->secondary;
 602         for (devfn = 0; devfn < 0xff; ++devfn) {
 603                 if (PCI_FUNC(devfn) == 0) {
 604                         pcibios_read_config_byte(bus->number, devfn,
 605                                                  PCI_HEADER_TYPE, &hdr_type);
 606                 } else if (!(hdr_type & 0x80)) {
 607                         /* not a multi-function device */
 608                         continue;
 609                 }
 610 
 611                 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
 612                                           &l);
 613                 /* some broken boards return 0 if a slot is empty: */
 614                 if (l == 0xffffffff || l == 0x00000000) {
 615                         hdr_type = 0;
 616                         continue;
 617                 }
 618 
 619                 dev = pci_malloc(sizeof(*dev), mem_startp);
 620                 dev->bus = bus;
 621                 /*
 622                  * Put it into the simple chain of devices on this
 623                  * bus.  It is used to find devices once everything is
 624                  * set up.
 625                  */
 626                 dev->next = pci_devices;
 627                 pci_devices = dev;
 628 
 629                 dev->devfn  = devfn;
 630                 dev->vendor = l & 0xffff;
 631                 dev->device = (l >> 16) & 0xffff;
 632 
 633                 /*
 634                  * Check to see if we now about this device and report
 635                  * a message at boot time.  This is the only way to
 636                  * learn about new hardware...
 637                  */
 638                 info = pci_lookup_dev(dev->vendor, dev->device);
 639                 if (!info) {
 640                         printk("Warning : Unknown PCI device.  Please read include/linux/pci.h \n");
 641                 } else {
 642                         /* Some BIOS' are lazy. Let's do their job: */
 643                         if (info->bridge_type != 0xff) {
 644                                 burst_bridge(bus->number, devfn,
 645                                              info->bridge_type, 1);
 646                         }
 647                 }
 648 
 649                 /* non-destructively determine if device can be a master: */
 650                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 651                                          &cmd);
 652                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 653                                           cmd | PCI_COMMAND_MASTER);
 654                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 655                                          &tmp);
 656                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 657                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 658                                           cmd);
 659 
 660                 /* read irq level (may be changed during pcibios_fixup()): */
 661                 pcibios_read_config_byte(bus->number, devfn,
 662                                          PCI_INTERRUPT_LINE, &dev->irq);
 663 
 664                 /* check to see if this device is a PCI-PCI bridge: */
 665                 pcibios_read_config_dword(bus->number, devfn,
 666                                           PCI_CLASS_REVISION, &l);
 667                 l = l >> 8;                     /* upper 3 bytes */
 668                 dev->class = l;
 669                 /*
 670                  * Now insert it into the list of devices held
 671                  * by the parent bus.
 672                  */
 673                 dev->sibling = bus->devices;
 674                 bus->devices = dev;
 675 
 676                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
 677                         unsigned int buses;
 678 
 679                         /*
 680                          * Insert it into the tree of buses.
 681                          */
 682                         child = pci_malloc(sizeof(*child), mem_startp);
 683                         child->next   = bus->children;
 684                         bus->children = child;
 685                         child->self = dev;
 686                         child->parent = bus;
 687 
 688                         /*
 689                          * Set up the primary, secondary and subordinate
 690                          * bus numbers.
 691                          */
 692                         child->number = child->secondary = ++max;
 693                         child->primary = bus->secondary;
 694                         child->subordinate = 0xff;
 695                         /*
 696                          * Clear all status bits and turn off memory,
 697                          * I/O and master enables.
 698                          */
 699                         pcibios_write_config_word(bus->number, devfn,
 700                                                   PCI_COMMAND, 0x0000);
 701                         pcibios_write_config_word(bus->number, devfn,
 702                                                   PCI_STATUS, 0xffff);
 703                         /*
 704                          * Configure the bus numbers for this bridge:
 705                          */
 706                         pcibios_read_config_dword(bus->number, devfn, 0x18,
 707                                                   &buses);
 708                         buses &= 0xff000000;
 709                         buses |= (((unsigned int)(child->primary)     <<  0) |
 710                                   ((unsigned int)(child->secondary)   <<  8) |
 711                                   ((unsigned int)(child->subordinate) << 16));
 712                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 713                                                    buses);
 714                         /*
 715                          * Now we can scan all subordinate buses:
 716                          */
 717                         max = scan_bus(child, mem_startp);
 718                         /*
 719                          * Set the subordinate bus number to its real
 720                          * value:
 721                          */
 722                         child->subordinate = max;
 723                         buses = (buses & 0xff00ffff)
 724                           | ((unsigned int)(child->subordinate) << 16);
 725                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 726                                                    buses);
 727                 }
 728         }
 729         /*
 730          * We've scanned the bus and so we know all about what's on
 731          * the other side of any bridges that may be on this bus plus
 732          * any devices.
 733          *
 734          * Return how far we've got finding sub-buses.
 735          */
 736         return max;
 737 }
 738 
 739 
 740 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
 741 {
 742         mem_start = pcibios_init(mem_start, mem_end);
 743 
 744         if (!pcibios_present()) {
 745                 printk("pci_init: no BIOS32 detected\n");
 746                 return mem_start;
 747         }
 748 
 749         printk("Probing PCI hardware.\n");
 750 
 751         memset(&pci_root, 0, sizeof(pci_root));
 752         pci_root.subordinate = scan_bus(&pci_root, &mem_start);
 753 
 754         /* give BIOS a chance to apply platform specific fixes: */
 755         mem_start = pcibios_fixup(mem_start, mem_end);
 756 
 757 #ifdef DEBUG
 758         {
 759                 int len = get_pci_list(mem_start);
 760                 if (len) {
 761                         ((char*)mem_start)[len] = '\0';
 762                         printk("%s\n", mem_start);
 763                 }
 764         }
 765 #endif
 766         return mem_start;
 767 }

/* [previous][next][first][last][top][bottom][index][help] */