This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
45 DEVICE( DPT, DPT, "SmartCache/Raid"),
46 DEVICE( S3, S3_864_1, "Vision 864-P"),
47 DEVICE( S3, S3_864_2, "Vision 864-P"),
48 DEVICE( S3, S3_868, "Vision 868"),
49 DEVICE( S3, S3_928, "Vision 928-P"),
50 DEVICE( S3, S3_964_1, "Vision 964-P"),
51 DEVICE( S3, S3_964_2, "Vision 964-P"),
52 DEVICE( S3, S3_811, "Trio32/Trio64"),
53 DEVICE( S3, S3_968, "Vision 968"),
54 DEVICE( OPTI, OPTI_82C822, "82C822"),
55 DEVICE( OPTI, OPTI_82C621, "82C621"),
56 DEVICE( OPTI, OPTI_82C557, "82C557"),
57 DEVICE( OPTI, OPTI_82C558, "82C558"),
58 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
59 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
60 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
61 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
62 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_BRD, "DC21050"),
68 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
69 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
70 DEVICE( INTEL, INTEL_82378, "82378IB"),
71 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
72 DEVICE( INTEL, INTEL_82375, "82375EB"),
73 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
74 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
75 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
76 DEVICE( INTEL, INTEL_82371, "82471 Triton"),
77 DEVICE( INTEL, INTEL_82438, "82438"),
78 DEVICE( INTEL, INTEL_7116, "SAA7116"),
79 DEVICE( INTEL, INTEL_82865, "82865"),
80 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
81 DEVICE( ATI, ATI_M32, "Mach 32"),
82 DEVICE( ATI, ATI_M64, "Mach 64"),
83 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
84 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
85 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
86 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
87 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
88 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
89 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
90 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
91 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
92 DEVICE( N9, N9_I128, "Imagine 128"),
93 DEVICE( AI, AI_M1435, "M1435"),
94 DEVICE( AL, AL_M1445, "M1445"),
95 DEVICE( AL, AL_M1449, "M1449"),
96 DEVICE( AL, AL_M1451, "M1451"),
97 DEVICE( AL, AL_M1461, "M1461"),
98 DEVICE( AL, AL_M4803, "M4803"),
99 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
100 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
101 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
102 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
103 DEVICE( CMD, CMD_640, "640A"),
104 DEVICE( VISION, VISION_QD8500, "QD-8500"),
105 DEVICE( VISION, VISION_QD8580, "QD-8580"),
106 DEVICE( AMD, AMD_LANCE, "79C970"),
107 DEVICE( AMD, AMD_SCSI, "53C974"),
108 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
109 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
110 DEVICE( ADL, ADL_2301, "2301"),
111 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
112 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
113 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
114 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
115 DEVICE( NS, NS_87410, "87410"),
116 DEVICE( VIA, VIA_82C505, "VT 82C505"),
117 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
118 DEVICE( VIA, VIA_82C561, "VT 82C561"),
119 DEVICE( SI, SI_496, "85C496"),
120 DEVICE( SI, SI_501, "85C501"),
121 DEVICE( SI, SI_503, "85C503"),
122 DEVICE( SI, SI_601, "85C601"),
123 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
124 DEVICE( IMS, IMS_8849, "8849"),
125 DEVICE( ZEINET, ZEINET_1221, "1221"),
126 DEVICE( EF, EF_ATM, "155P-MF1"),
127 DEVICE( HER, HER_STING, "Stingray"),
128 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
129 DEVICE( CT, CT_65545, "65545"),
130 DEVICE( FD, FD_36C70, "TMC-18C30"),
131 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
132 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
133 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
134 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
135 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
136 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
137 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
138 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
139 DEVICE( X, X_AGX016, "ITT AGX016"),
140 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
141 DEVICE( HP, HP_J2585A, "J2585A")
142 };
143
144
145 #ifdef CONFIG_PCI_OPTIMIZE
146
147
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150
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160
161
162 struct optimization_type {
163 const char *type;
164 const char *off;
165 const char *on;
166 } bridge_optimization[] = {
167 {"Cache L2", "write trough", "write back"},
168 {"CPU-PCI posted write", "off", "on"},
169 {"CPU-Memory posted write", "off", "on"},
170 {"PCI-Memory posted write", "off", "on"},
171 {"PCI burst", "off", "on"}
172 };
173
174 #define NUM_OPTIMIZATIONS \
175 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
176
177 struct bridge_mapping_type {
178 unsigned char addr;
179 unsigned char mask;
180 unsigned char value;
181 } bridge_mapping[] = {
182
183
184
185
186
187
188
189 {0x0 ,0x02 ,0x02 },
190 {0x53 ,0x02 ,0x02 },
191 {0x53 ,0x01 ,0x01 },
192 {0x54 ,0x01 ,0x01 },
193 {0x54 ,0x02 ,0x02 },
194
195
196
197
198
199 {0x50 ,0x10 ,0x00 },
200 {0x51 ,0x40 ,0x40 },
201 {0x0 ,0x0 ,0x0 },
202 {0x0 ,0x0 ,0x0 },
203 {0x0 ,0x0 ,0x0 },
204
205
206
207
208
209
210 {0x0 ,0x1 ,0x1 },
211 {0x0 ,0x2 ,0x0 },
212 {0x0 ,0x0 ,0x0 },
213 {0x0 ,0x0 ,0x0 },
214 {0x0 ,0x0 ,0x0 }
215 };
216
217 #endif
218
219
220
221
222
223
224 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
225 {
226 int i;
227
228 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
229 if (dev_info[i].vendor == vendor &&
230 dev_info[i].device == dev)
231 {
232 return &dev_info[i];
233 }
234 }
235 return 0;
236 }
237
238
239 const char *pci_strbioserr (int error)
240 {
241 switch (error) {
242 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
243 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
244 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
245 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
246 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
247 case PCIBIOS_SET_FAILED: return "SET_FAILED";
248 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
249 default: return "Unknown error status";
250 }
251 }
252
253
254 const char *pci_strclass (unsigned int class)
255 {
256 switch (class >> 8) {
257 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
258 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
259
260 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
261 case PCI_CLASS_STORAGE_IDE: return "IDE controller";
262 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
263 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
264 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
265 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
266
267 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
268 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
269 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
270 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
271 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
272
273 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
274 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
275 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
276
277 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
278 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
279 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
280
281 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
282 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
283 case PCI_CLASS_MEMORY_OTHER: return "Memory";
284
285 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
286 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
287 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
288 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
289 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
290 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
291 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
292 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
293 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
294
295 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
296 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
297 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
298
299 case PCI_CLASS_SYSTEM_PIC: return "PIC";
300 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
301 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
302 case PCI_CLASS_SYSTEM_RTC: return "RTC";
303 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
304
305 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
306 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
307 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
308 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
309
310 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
311 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
312
313 case PCI_CLASS_PROCESSOR_386: return "386";
314 case PCI_CLASS_PROCESSOR_486: return "486";
315 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
316 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
317 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
318 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
319
320 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
321 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
322 case PCI_CLASS_SERIAL_SSA: return "SSA";
323 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
324
325 default: return "Unknown class";
326 }
327 }
328
329
330 const char *pci_strvendor(unsigned int vendor)
331 {
332 switch (vendor) {
333 case PCI_VENDOR_ID_NCR: return "NCR";
334 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
335 case PCI_VENDOR_ID_DPT: return "DPT";
336 case PCI_VENDOR_ID_S3: return "S3 Inc.";
337 case PCI_VENDOR_ID_OPTI: return "OPTI";
338 case PCI_VENDOR_ID_UMC: return "UMC";
339 case PCI_VENDOR_ID_DEC: return "DEC";
340 case PCI_VENDOR_ID_MATROX: return "Matrox";
341 case PCI_VENDOR_ID_INTEL: return "Intel";
342 case PCI_VENDOR_ID_SMC: return "SMC";
343 case PCI_VENDOR_ID_ATI: return "ATI";
344 case PCI_VENDOR_ID_WEITEK: return "Weitek";
345 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
346 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
347 case PCI_VENDOR_ID_N9: return "Number Nine";
348 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
349 case PCI_VENDOR_ID_AL: return "Acer Labs";
350 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
351 case PCI_VENDOR_ID_CMD: return "CMD";
352 case PCI_VENDOR_ID_VISION: return "Vision";
353 case PCI_VENDOR_ID_AMD: return "AMD";
354 case PCI_VENDOR_ID_VLSI: return "VLSI";
355 case PCI_VENDOR_ID_ADL: return "Advance Logic";
356 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
357 case PCI_VENDOR_ID_TRIDENT: return "Trident";
358 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
359 case PCI_VENDOR_ID_NS: return "NS";
360 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
361 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
362 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
363 case PCI_VENDOR_ID_IMS: return "IMS";
364 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
365 case PCI_VENDOR_ID_EF: return "Efficient Networks";
366 case PCI_VENDOR_ID_HER: return "Hercules";
367 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
368 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
369 case PCI_VENDOR_ID_FD: return "Future Domain";
370 case PCI_VENDOR_ID_WINBOND: return "Winbond";
371 case PCI_VENDOR_ID_3COM: return "3Com";
372 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
373 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
374 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
375 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
376 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
377 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
378 default: return "Unknown vendor";
379 }
380 }
381
382
383 const char *pci_strdev(unsigned int vendor, unsigned int device)
384 {
385 struct pci_dev_info *info;
386
387 info = pci_lookup_dev(vendor, device);
388 return info ? info->name : "Unknown device";
389 }
390
391
392
393
394
395
396 static void burst_bridge(unsigned char bus, unsigned char devfn,
397 unsigned char pos, int turn_on)
398 {
399 #ifdef CONFIG_PCI_OPTIMIZE
400 struct bridge_mapping_type *bmap;
401 unsigned char val;
402 int i;
403
404 pos *= NUM_OPTIMIZATIONS;
405 printk("PCI bridge optimization.\n");
406 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
407 printk(" %s: ", bridge_optimization[i].type);
408 bmap = &bridge_mapping[pos + i];
409 if (!bmap->addr) {
410 printk("Not supported.");
411 } else {
412 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
413 if ((val & bmap->mask) == bmap->value) {
414 printk("%s.", bridge_optimization[i].on);
415 if (!turn_on) {
416 pcibios_write_config_byte(bus, devfn,
417 bmap->addr,
418 (val | bmap->mask)
419 - bmap->value);
420 printk("Changed! Now %s.", bridge_optimization[i].off);
421 }
422 } else {
423 printk("%s.", bridge_optimization[i].off);
424 if (turn_on) {
425 pcibios_write_config_byte(bus, devfn,
426 bmap->addr,
427 (val & (0xff - bmap->mask))
428 + bmap->value);
429 printk("Changed! Now %s.", bridge_optimization[i].on);
430 }
431 }
432 }
433 printk("\n");
434 }
435 #endif
436 }
437
438
439
440
441
442
443
444
445 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
446 {
447 unsigned long base;
448 unsigned int l, class_rev, bus, devfn;
449 unsigned short vendor, device, status;
450 unsigned char bist, latency, min_gnt, max_lat;
451 int reg, len = 0;
452 const char *str;
453
454 bus = dev->bus->number;
455 devfn = dev->devfn;
456
457 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
458 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
459 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
460 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
461 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
462 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
463 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
464 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
465 if (len + 80 > size) {
466 return -1;
467 }
468 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
469 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
470
471 if (len + 80 > size) {
472 return -1;
473 }
474 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
475 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
476 pci_strdev(vendor, device), class_rev & 0xff);
477
478 if (!pci_lookup_dev(vendor, device)) {
479 len += sprintf(buf + len,
480 "Vendor id=%x. Device id=%x.\n ",
481 vendor, device);
482 }
483
484 str = 0;
485 switch (status & PCI_STATUS_DEVSEL_MASK) {
486 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
487 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
488 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
489 }
490 if (len + strlen(str) > size) {
491 return -1;
492 }
493 len += sprintf(buf + len, str);
494
495 if (status & PCI_STATUS_FAST_BACK) {
496 # define fast_b2b_capable "Fast back-to-back capable. "
497 if (len + strlen(fast_b2b_capable) > size) {
498 return -1;
499 }
500 len += sprintf(buf + len, fast_b2b_capable);
501 # undef fast_b2b_capable
502 }
503
504 if (bist & PCI_BIST_CAPABLE) {
505 # define BIST_capable "BIST capable. "
506 if (len + strlen(BIST_capable) > size) {
507 return -1;
508 }
509 len += sprintf(buf + len, BIST_capable);
510 # undef BIST_capable
511 }
512
513 if (dev->irq) {
514 if (len + 40 > size) {
515 return -1;
516 }
517 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
518 }
519
520 if (dev->master) {
521 if (len + 80 > size) {
522 return -1;
523 }
524 len += sprintf(buf + len, "Master Capable. ");
525 if (latency)
526 len += sprintf(buf + len, "Latency=%d. ", latency);
527 else
528 len += sprintf(buf + len, "No bursts. ");
529 if (min_gnt)
530 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
531 if (max_lat)
532 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
533 }
534
535 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
536 if (len + 40 > size) {
537 return -1;
538 }
539 pcibios_read_config_dword(bus, devfn, reg, &l);
540 base = l;
541 if (!base) {
542 continue;
543 }
544
545 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
546 len += sprintf(buf + len,
547 "\n I/O at 0x%lx.",
548 base & PCI_BASE_ADDRESS_IO_MASK);
549 } else {
550 const char *pref, *type = "unknown";
551
552 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
553 pref = "P";
554 } else {
555 pref = "Non-p";
556 }
557 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
558 case PCI_BASE_ADDRESS_MEM_TYPE_32:
559 type = "32 bit"; break;
560 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
561 type = "20 bit"; break;
562 case PCI_BASE_ADDRESS_MEM_TYPE_64:
563 type = "64 bit";
564
565 reg += 4;
566 pcibios_read_config_dword(bus, devfn, reg, &l);
567 base |= ((u64) l) << 32;
568 break;
569 }
570 len += sprintf(buf + len,
571 "\n %srefetchable %s memory at "
572 "0x%lx.", pref, type,
573 base & PCI_BASE_ADDRESS_MEM_MASK);
574 }
575 }
576
577 len += sprintf(buf + len, "\n");
578 return len;
579 }
580
581
582
583
584
585
586 int get_pci_list(char *buf)
587 {
588 int nprinted, len, size;
589 struct pci_dev *dev;
590 # define MSG "\nwarning: page-size limit reached!\n"
591
592
593 size = PAGE_SIZE - (strlen(MSG) + 1);
594 len = sprintf(buf, "PCI devices found:\n");
595
596 for (dev = pci_devices; dev; dev = dev->next) {
597 nprinted = sprint_dev_config(dev, buf + len, size - len);
598 if (nprinted < 0) {
599 return len + sprintf(buf + len, MSG);
600 }
601 len += nprinted;
602 }
603 return len;
604 }
605
606
607
608
609
610
611 static void *pci_malloc(long size, unsigned long *mem_startp)
612 {
613 void *mem;
614
615 #ifdef DEBUG
616 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
617 #endif
618 mem = (void*) *mem_startp;
619 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
620 memset(mem, 0, size);
621 return mem;
622 }
623
624
625 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
626 {
627 unsigned int devfn, l, max;
628 unsigned char cmd, tmp, hdr_type = 0;
629 struct pci_dev_info *info;
630 struct pci_dev *dev;
631 struct pci_bus *child;
632
633 #ifdef DEBUG
634 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
635 #endif
636
637 max = bus->secondary;
638 for (devfn = 0; devfn < 0xff; ++devfn) {
639 if (PCI_FUNC(devfn) == 0) {
640 pcibios_read_config_byte(bus->number, devfn,
641 PCI_HEADER_TYPE, &hdr_type);
642 } else if (!(hdr_type & 0x80)) {
643
644 continue;
645 }
646
647 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
648 &l);
649
650 if (l == 0xffffffff || l == 0x00000000) {
651 hdr_type = 0;
652 continue;
653 }
654
655 dev = pci_malloc(sizeof(*dev), mem_startp);
656 dev->bus = bus;
657
658
659
660
661
662 dev->next = pci_devices;
663 pci_devices = dev;
664
665 dev->devfn = devfn;
666 dev->vendor = l & 0xffff;
667 dev->device = (l >> 16) & 0xffff;
668
669
670
671
672
673
674 info = pci_lookup_dev(dev->vendor, dev->device);
675 if (!info) {
676 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
677 } else {
678
679 if (info->bridge_type != 0xff) {
680 burst_bridge(bus->number, devfn,
681 info->bridge_type, 1);
682 }
683 }
684
685
686 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
687 &cmd);
688 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
689 cmd | PCI_COMMAND_MASTER);
690 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
691 &tmp);
692 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
693 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
694 cmd);
695
696
697 pcibios_read_config_byte(bus->number, devfn,
698 PCI_INTERRUPT_LINE, &dev->irq);
699
700
701 pcibios_read_config_dword(bus->number, devfn,
702 PCI_CLASS_REVISION, &l);
703 l = l >> 8;
704 dev->class = l;
705
706
707
708
709 dev->sibling = bus->devices;
710 bus->devices = dev;
711
712 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
713 unsigned int buses;
714
715
716
717
718 child = pci_malloc(sizeof(*child), mem_startp);
719 child->next = bus->children;
720 bus->children = child;
721 child->self = dev;
722 child->parent = bus;
723
724
725
726
727
728 child->number = child->secondary = ++max;
729 child->primary = bus->secondary;
730 child->subordinate = 0xff;
731
732
733
734
735 pcibios_write_config_word(bus->number, devfn,
736 PCI_COMMAND, 0x0000);
737 pcibios_write_config_word(bus->number, devfn,
738 PCI_STATUS, 0xffff);
739
740
741
742 pcibios_read_config_dword(bus->number, devfn, 0x18,
743 &buses);
744 buses &= 0xff000000;
745 buses |= (((unsigned int)(child->primary) << 0) |
746 ((unsigned int)(child->secondary) << 8) |
747 ((unsigned int)(child->subordinate) << 16));
748 pcibios_write_config_dword(bus->number, devfn, 0x18,
749 buses);
750
751
752
753 max = scan_bus(child, mem_startp);
754
755
756
757
758 child->subordinate = max;
759 buses = (buses & 0xff00ffff)
760 | ((unsigned int)(child->subordinate) << 16);
761 pcibios_write_config_dword(bus->number, devfn, 0x18,
762 buses);
763 }
764 }
765
766
767
768
769
770
771
772 return max;
773 }
774
775
776 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
777 {
778 mem_start = pcibios_init(mem_start, mem_end);
779
780 if (!pcibios_present()) {
781 printk("pci_init: no BIOS32 detected\n");
782 return mem_start;
783 }
784
785 printk("Probing PCI hardware.\n");
786
787 memset(&pci_root, 0, sizeof(pci_root));
788 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
789
790
791 mem_start = pcibios_fixup(mem_start, mem_end);
792
793 #ifdef DEBUG
794 {
795 int len = get_pci_list(mem_start);
796 if (len) {
797 ((char*)mem_start)[len] = '\0';
798 printk("%s\n", mem_start);
799 }
800 }
801 #endif
802 return mem_start;
803 }
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