root/include/linux/scc.h

/* [previous][next][first][last][top][bottom][index][help] */

INCLUDED FROM


   1 
   2 #ifndef _SCC_H
   3 #define _SCC_H
   4 
   5 /* selection of hardware types */
   6 
   7 #define PA0HZP          0x00    /* hardware type for PA0HZP SCC card and compatible */
   8 #define EAGLE           0x01    /* hardware type for EAGLE card */
   9 #define PC100           0x02    /* hardware type for PC100 card */
  10 #define PRIMUS          0x04    /* hardware type for PRIMUS-PC (DG9BL) card */
  11 #define DRSI            0x08    /* hardware type for DRSI PC*Packet card */
  12 #define BAYCOM          0x10    /* hardware type for BayCom (U)SCC */
  13 
  14 /* Constants */
  15 
  16 #define MAXSCC          4       /* number of max. supported chips */
  17 #define MAX_IBUFS       300     /* change this if you run out of memory */
  18 #define BUFSIZE         64      /* must not exceed 4096 */
  19 #define TPS             25      /* scc_timer(): 25  Ticks Per Second */
  20 
  21 #define SCC_TIMER       3
  22 
  23 #define SCC_PARANOIA_CHECK      /* tell the user if something is going wrong */
  24 
  25 /* ioctl() commands */
  26 
  27 /* !!! NEW VALUES !!! */
  28 
  29 #define TIOCSCCINI      0x5470          /* init driver */
  30 #define TIOCCHANINI     0x5471          /* init channel */
  31 
  32 #define TIOCGKISS       0x5472          /* get kiss parameter */
  33 #define TIOCSKISS       0x5473          /* set kiss parameter */
  34 
  35 #define TIOCSCCSTAT     0x5474          /* get scc status */
  36 
  37 
  38 /* magic number */
  39 
  40 #define SCC_MAGIC       0x8530          /* ;-) */
  41 
  42 /* KISS protocol flags */
  43 #define FEND    192
  44 #define FESC    219
  45 #define TFEND   220
  46 #define TFESC   221
  47 
  48 /* KISS state machine */
  49 
  50 #define KISS_IDLE       0
  51 #define KISS_DATA       1
  52 #define KISS_ESCAPE     2
  53 #define KISS_RXFRAME    3
  54 
  55 /* Device parameter control (from WAMPES) */
  56 
  57 #define PARAM_TXDELAY   1
  58 #define PARAM_PERSIST   2
  59 #define PARAM_SLOTTIME  3
  60 #define PARAM_TXTAIL    4
  61 #define PARAM_FULLDUP   5
  62 #define PARAM_SOFTDCD   6       /* was: PARAM_HW */
  63 #define PARAM_MUTE      7       /* ??? */
  64 #define PARAM_DTR       8
  65 #define PARAM_RTS       9
  66 #define PARAM_SPEED     10
  67 #define PARAM_ENDDELAY  11      /* ??? */
  68 #define PARAM_GROUP     12
  69 #define PARAM_IDLE      13
  70 #define PARAM_MIN       14
  71 #define PARAM_MAXKEY    15
  72 #define PARAM_WAIT      16
  73 #define PARAM_MAXDEFER  17
  74 #define PARAM_TX        18
  75 #define PARAM_SLIP      19
  76 #define PARAM_RETURN    255     /* reset kiss mode */
  77 
  78 #define TIMER_OFF       65535U  /* to switch off timers */
  79 #define NO_SUCH_PARAM   65534U  /* param not implemented */
  80 
  81 /* channel grouping */
  82 
  83 #define RXGROUP         0x100   /* if set, only tx when all channels clear */
  84 #define TXGROUP         0x200   /* if set, don't transmit simultaneously */
  85 
  86 /* Tx/Rx clock sources */
  87 
  88 #define CLK_DPLL        0       /* normal halfduplex operation */
  89 #define CLK_EXTERNAL    1       /* external clocking (G3RUH/DF9IC modems) */
  90 #define CLK_DIVIDER     2       /* Rx = DPLL, Tx = divider (fullduplex with */
  91                                 /* modems without clock regeneration */
  92 
  93 /* Tx state */
  94 
  95 #define TXS_IDLE        0       /* Transmitter off, no data pending */
  96 #define TXS_BUSY        1       /* waiting for permission to send / tailtime */
  97 #define TXS_ACTIVE      2       /* Transmitter on, sending data */
  98 #define TXS_NEWFRAME    3       /* reset CRC and send (next) frame */
  99 
 100 #define TX_ON           1       /* command for scc_key_trx() */
 101 #define TX_OFF          0       /* dto */
 102 
 103 /* Buffer management */
 104 
 105 #define BT_RECEIVE  1           /* buffer allocated by receive */
 106 #define BT_TRANSMIT 2           /* buffer allocated by transmit */
 107 
 108 #define QUEUE_THRES MAX_IBUFS/20        /* maximum amount of packets being queued */
 109 #define QUEUE_HYST  3                   /* leave QUEUE_HYST packets untouched */
 110 
 111 #define NULLBUF  (struct mbuf *)0
 112 #define NULLBUFP (struct mbuf **)0
 113 
 114 
 115 typedef unsigned short io_port; /* type definition for an 'io port address' */
 116 typedef unsigned short ioaddr;  /* old def */
 117 
 118 #ifdef SCC_DELAY
 119 #define Inb(port)       inb_p(port)
 120 #define Outb(port, val) outb_p(val, port)
 121 #else
 122 #define Inb(port)       inb(port)
 123 #define Outb(port, val) outb(val, port)
 124 #endif
 125 
 126 /* some nasty macros (esp. Expired) */
 127 
 128 #define TIMER_STOPPED 65535U
 129 #define Running(k) (scc->k != TIMER_STOPPED)
 130 #define Expired(k) (scc->k != TIMER_STOPPED) && (!(scc->k) || (--(scc->k) == 0))
 131 #define Stop_Timer(k) scc->k = TIMER_STOPPED
 132 
 133 
 134 /* Basic message buffer structure */
 135 
 136 struct mbuf {
 137         struct mbuf *next;      /* Links mbufs belonging to single packets */
 138         struct mbuf *anext;     /* Links packets on queues */
 139 
 140         char type;              /* who allocated this buffer? */
 141         unsigned long  time_out;/* buffer time out */
 142 
 143         int size;               /* Size of associated data buffer */
 144         int refcnt;             /* Reference count */
 145         struct mbuf *dup;       /* Pointer to duplicated mbuf */
 146         char data[BUFSIZE];     /* Active working pointers */
 147         int cnt;
 148         int in_use;
 149 };
 150 
 151 
 152 struct sccbuf {
 153         struct mbuf *bp;
 154         int inuse;
 155 };
 156                                                                                                 
 157                 
 158 /* SCC channel control structure for KISS */
 159 
 160 struct scc_kiss {
 161         unsigned char txdelay;          /* Transmit Delay 10 ms/cnt */
 162         unsigned char persist;          /* Persistence (0-255) as a % */
 163         unsigned char slottime;         /* Delay to wait on persistence hit */
 164         unsigned char tailtime;         /* Delay after XMTR OFF */
 165         unsigned char fulldup;          /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
 166         unsigned char waittime;         /* Waittime before any transmit attempt */
 167         unsigned int  maxkeyup;         /* Maximum time to transmit (seconds) */
 168         unsigned char mintime;          /* Minimal offtime after MAXKEYUP timeout */
 169         unsigned int  idletime;         /* Maximum idle time in ALWAYS KEYED mode (seconds) */
 170         unsigned int  maxdefer;         /* Timer for CSMA channel busy limit */
 171         unsigned char tx_inhibit;       /* Transmit is not allowed when set */  
 172         unsigned char group;            /* group ID for AX.25 TX interlocking */
 173         unsigned char not_slip;         /* set to zero: use SLIP instead of KISS */
 174         unsigned char softdcd;          /* use DPLL instead of DCD pin for carrier detect */
 175 };
 176 
 177 
 178 /* SCC statistical information */
 179 
 180 struct scc_stat {
 181         long rxints;            /* Receiver interrupts */
 182         long txints;            /* Transmitter interrupts */
 183         long exints;            /* External/status interrupts */
 184         long spints;            /* Special receiver interrupts */
 185 
 186         long txframes;          /* Packets sent */
 187         long rxframes;          /* Number of Frames Actally Received */
 188         long rxerrs;            /* CRC Errors */
 189         long txerrs;            /* KISS errors */
 190         
 191         unsigned int nospace;   /* "Out of buffers" */
 192         unsigned int rx_over;   /* Receiver Overruns */
 193         unsigned int tx_under;  /* Transmitter Underruns */
 194 
 195         unsigned int tx_state;  /* Transmitter state */
 196         
 197         char tx_kiss_state;     /* state of the kiss interpreter */
 198         char rx_kiss_state;     /* state of the kiss encoder */
 199         
 200         int tx_queued;          /* tx frames enqueued */
 201         int rx_queued;          /* rx frames enqueued */
 202         
 203         unsigned int rx_alloc;  /* allocated rx_buffers */
 204         unsigned int tx_alloc;  /* allocated tx_buffers */
 205         unsigned int used_buf;  /* used buffers (should be rx_alloc+tx_alloc) */
 206 };
 207 
 208 
 209 struct scc_modem{
 210         long speed;             /* Line speed, bps */
 211         char clocksrc;          /* 0 = DPLL, 1 = external, 2 = divider */
 212         char nrz;               /* NRZ instead of NRZI */       
 213 };
 214 
 215 struct ioctl_command {
 216         int      command;       /* one of the KISS-Commands devined above */
 217         unsigned param;         /* KISS-Param */
 218 };
 219 
 220 /* SCC channel structure */
 221 
 222 struct scc_channel {
 223         int magic;              /* magic word */
 224         
 225         int init;               /* channel exists? */
 226         struct tty_struct *tty; /* link to tty control structure */
 227         unsigned char tty_opened;
 228         
 229         io_port ctrl;           /* I/O address of CONTROL register */
 230         io_port data;           /* I/O address of DATA register */
 231         char enhanced;          /* Enhanced SCC support */
 232 
 233         unsigned char wreg[16]; /* Copy of last written value in WRx */
 234         unsigned char status;   /* Copy of R0 at last external interrupt */
 235 
 236         struct scc_kiss kiss;   /* control structure for KISS params */
 237         struct scc_stat stat;   /* statistical information */
 238         struct scc_modem modem; /* modem information */
 239 
 240         char rxbuf[2048];       /* Rx frame buffer max framesize * 2 */
 241         int rxbufcnt;           /* Rx frame counter */
 242 
 243         struct mbuf *sndq;      /* tx: Packets awaiting transmission */
 244         struct mbuf *tbp;       /* tx: Transmit mbuf being sent */
 245 
 246         struct mbuf *sndq1;     /* Pointer to mbuf currently under construction */
 247         struct mbuf *sndq2;     /* Pointer to mbuf currently under construction */
 248 
 249 /*      unsigned char           *xmit_buf;
 250         int                     xmit_head;
 251         int                     xmit_tail;
 252         int                     xmit_cnt;*/
 253         
 254         /* Timer */
 255 
 256         unsigned int t_dwait;   /* wait time (DWAIT) */
 257         unsigned int t_slot;    /* channel sample frequency */
 258         unsigned int t_txdel;   /* TX delay */
 259         unsigned int t_tail;    /* tail time */
 260         unsigned int t_maxk;    /* max. key up */
 261         unsigned int t_min;     /* minimal key up */
 262         unsigned int t_idle;    /* */
 263         unsigned int t_mbusy;   /* time until defer if channel busy */          
 264 };
 265 
 266 
 267 
 268 /* 8530 Serial Communications Controller Register definitions */
 269 #define FLAG    0x7e
 270 
 271 /* Write Register 0 */
 272 #define R0      0               /* Register selects */
 273 #define R1      1
 274 #define R2      2
 275 #define R3      3
 276 #define R4      4
 277 #define R5      5
 278 #define R6      6
 279 #define R7      7
 280 #define R8      8
 281 #define R9      9
 282 #define R10     10
 283 #define R11     11
 284 #define R12     12
 285 #define R13     13
 286 #define R14     14
 287 #define R15     15
 288 
 289 #define NULLCODE        0       /* Null Code */
 290 #define POINT_HIGH      0x8     /* Select upper half of registers */
 291 #define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
 292 #define SEND_ABORT      0x18    /* HDLC Abort */
 293 #define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
 294 #define RES_Tx_P        0x28    /* Reset TxINT Pending */
 295 #define ERR_RES         0x30    /* Error Reset */
 296 #define RES_H_IUS       0x38    /* Reset highest IUS */
 297 
 298 #define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
 299 #define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
 300 #define RES_EOM_L       0xC0    /* Reset EOM latch */
 301 
 302 /* Write Register 1 */
 303 
 304 #define EXT_INT_ENAB    0x1     /* Ext Int Enable */
 305 #define TxINT_ENAB      0x2     /* Tx Int Enable */
 306 #define PAR_SPEC        0x4     /* Parity is special condition */
 307 
 308 #define RxINT_DISAB     0       /* Rx Int Disable */
 309 #define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
 310 #define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
 311 #define INT_ERR_Rx      0x18    /* Int on error only */
 312 
 313 #define WT_RDY_RT       0x20    /* Wait/Ready on R/T */
 314 #define WT_FN_RDYFN     0x40    /* Wait/FN/Ready FN */
 315 #define WT_RDY_ENAB     0x80    /* Wait/Ready Enable */
 316 
 317 /* Write Register 2 (Interrupt Vector) */
 318 
 319 /* Write Register 3 */
 320 
 321 #define RxENABLE        0x1     /* Rx Enable */
 322 #define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 323 #define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 324 #define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 325 #define ENT_HM          0x10    /* Enter Hunt Mode */
 326 #define AUTO_ENAB       0x20    /* Auto Enables */
 327 #define Rx5             0x0     /* Rx 5 Bits/Character */
 328 #define Rx7             0x40    /* Rx 7 Bits/Character */
 329 #define Rx6             0x80    /* Rx 6 Bits/Character */
 330 #define Rx8             0xc0    /* Rx 8 Bits/Character */
 331 
 332 /* Write Register 4 */
 333 
 334 #define PAR_ENA         0x1     /* Parity Enable */
 335 #define PAR_EVEN        0x2     /* Parity Even/Odd* */
 336 
 337 #define SYNC_ENAB       0       /* Sync Modes Enable */
 338 #define SB1             0x4     /* 1 stop bit/char */
 339 #define SB15            0x8     /* 1.5 stop bits/char */
 340 #define SB2             0xc     /* 2 stop bits/char */
 341 
 342 #define MONSYNC         0       /* 8 Bit Sync character */
 343 #define BISYNC          0x10    /* 16 bit sync character */
 344 #define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 345 #define EXTSYNC         0x30    /* External Sync Mode */
 346 
 347 #define X1CLK           0x0     /* x1 clock mode */
 348 #define X16CLK          0x40    /* x16 clock mode */
 349 #define X32CLK          0x80    /* x32 clock mode */
 350 #define X64CLK          0xC0    /* x64 clock mode */
 351 
 352 /* Write Register 5 */
 353 
 354 #define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 355 #define RTS             0x2     /* RTS */
 356 #define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 357 #define TxENAB          0x8     /* Tx Enable */
 358 #define SND_BRK         0x10    /* Send Break */
 359 #define Tx5             0x0     /* Tx 5 bits (or less)/character */
 360 #define Tx7             0x20    /* Tx 7 bits/character */
 361 #define Tx6             0x40    /* Tx 6 bits/character */
 362 #define Tx8             0x60    /* Tx 8 bits/character */
 363 #define DTR             0x80    /* DTR */
 364 
 365 /* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 366 
 367 /* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 368 
 369 /* Write Register 8 (transmit buffer) */
 370 
 371 /* Write Register 9 (Master interrupt control) */
 372 #define VIS     1       /* Vector Includes Status */
 373 #define NV      2       /* No Vector */
 374 #define DLC     4       /* Disable Lower Chain */
 375 #define MIE     8       /* Master Interrupt Enable */
 376 #define STATHI  0x10    /* Status high */
 377 #define NORESET 0       /* No reset on write to R9 */
 378 #define CHRB    0x40    /* Reset channel B */
 379 #define CHRA    0x80    /* Reset channel A */
 380 #define FHWRES  0xc0    /* Force hardware reset */
 381 
 382 /* Write Register 10 (misc control bits) */
 383 #define BIT6    1       /* 6 bit/8bit sync */
 384 #define LOOPMODE 2      /* SDLC Loop mode */
 385 #define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 386 #define MARKIDLE 8      /* Mark/flag on idle */
 387 #define GAOP    0x10    /* Go active on poll */
 388 #define NRZ     0       /* NRZ mode */
 389 #define NRZI    0x20    /* NRZI mode */
 390 #define FM1     0x40    /* FM1 (transition = 1) */
 391 #define FM0     0x60    /* FM0 (transition = 0) */
 392 #define CRCPS   0x80    /* CRC Preset I/O */
 393 
 394 /* Write Register 11 (Clock Mode control) */
 395 #define TRxCXT  0       /* TRxC = Xtal output */
 396 #define TRxCTC  1       /* TRxC = Transmit clock */
 397 #define TRxCBR  2       /* TRxC = BR Generator Output */
 398 #define TRxCDP  3       /* TRxC = DPLL output */
 399 #define TRxCOI  4       /* TRxC O/I */
 400 #define TCRTxCP 0       /* Transmit clock = RTxC pin */
 401 #define TCTRxCP 8       /* Transmit clock = TRxC pin */
 402 #define TCBR    0x10    /* Transmit clock = BR Generator output */
 403 #define TCDPLL  0x18    /* Transmit clock = DPLL output */
 404 #define RCRTxCP 0       /* Receive clock = RTxC pin */
 405 #define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 406 #define RCBR    0x40    /* Receive clock = BR Generator output */
 407 #define RCDPLL  0x60    /* Receive clock = DPLL output */
 408 #define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 409 
 410 /* Write Register 12 (lower byte of baud rate generator time constant) */
 411 
 412 /* Write Register 13 (upper byte of baud rate generator time constant) */
 413 
 414 /* Write Register 14 (Misc control bits) */
 415 #define BRENABL 1       /* Baud rate generator enable */
 416 #define BRSRC   2       /* Baud rate generator source */
 417 #define DTRREQ  4       /* DTR/Request function */
 418 #define AUTOECHO 8      /* Auto Echo */
 419 #define LOOPBAK 0x10    /* Local loopback */
 420 #define SEARCH  0x20    /* Enter search mode */
 421 #define RMC     0x40    /* Reset missing clock */
 422 #define DISDPLL 0x60    /* Disable DPLL */
 423 #define SSBR    0x80    /* Set DPLL source = BR generator */
 424 #define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 425 #define SFMM    0xc0    /* Set FM mode */
 426 #define SNRZI   0xe0    /* Set NRZI mode */
 427 
 428 /* Write Register 15 (external/status interrupt control) */
 429 #define ZCIE    2       /* Zero count IE */
 430 #define DCDIE   8       /* DCD IE */
 431 #define SYNCIE  0x10    /* Sync/hunt IE */
 432 #define CTSIE   0x20    /* CTS IE */
 433 #define TxUIE   0x40    /* Tx Underrun/EOM IE */
 434 #define BRKIE   0x80    /* Break/Abort IE */
 435 
 436 
 437 /* Read Register 0 */
 438 #define Rx_CH_AV        0x1     /* Rx Character Available */
 439 #define ZCOUNT          0x2     /* Zero count */
 440 #define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 441 #define DCD             0x8     /* DCD */
 442 #define SYNC_HUNT       0x10    /* Sync/hunt */
 443 #define CTS             0x20    /* CTS */
 444 #define TxEOM           0x40    /* Tx underrun */
 445 #define BRK_ABRT        0x80    /* Break/Abort */
 446 
 447 /* Read Register 1 */
 448 #define ALL_SNT         0x1     /* All sent */
 449 /* Residue Data for 8 Rx bits/char programmed */
 450 #define RES3            0x8     /* 0/3 */
 451 #define RES4            0x4     /* 0/4 */
 452 #define RES5            0xc     /* 0/5 */
 453 #define RES6            0x2     /* 0/6 */
 454 #define RES7            0xa     /* 0/7 */
 455 #define RES8            0x6     /* 0/8 */
 456 #define RES18           0xe     /* 1/8 */
 457 #define RES28           0x0     /* 2/8 */
 458 /* Special Rx Condition Interrupts */
 459 #define PAR_ERR         0x10    /* Parity error */
 460 #define Rx_OVR          0x20    /* Rx Overrun Error */
 461 #define CRC_ERR         0x40    /* CRC/Framing Error */
 462 #define END_FR          0x80    /* End of Frame (SDLC) */
 463 
 464 /* Read Register 2 (channel B only) - Interrupt vector */
 465 
 466 #define VECTOR_MASK     0x06
 467 
 468 #define TXINT   0x00
 469 #define EXINT   0x02
 470 #define RXINT   0x04
 471 #define SPINT   0x06
 472 
 473 
 474 /* Read Register 3 (interrupt pending register) ch a only */
 475 #define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 476 #define CHBTxIP 0x2             /* Channel B Tx IP */
 477 #define CHBRxIP 0x4             /* Channel B Rx IP */
 478 #define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 479 #define CHATxIP 0x10            /* Channel A Tx IP */
 480 #define CHARxIP 0x20            /* Channel A Rx IP */
 481 
 482 /* Read Register 8 (receive data register) */
 483 
 484 /* Read Register 10  (misc status bits) */
 485 #define ONLOOP  2               /* On loop */
 486 #define LOOPSEND 0x10           /* Loop sending */
 487 #define CLK2MIS 0x40            /* Two clocks missing */
 488 #define CLK1MIS 0x80            /* One clock missing */
 489 
 490 /* Read Register 12 (lower byte of baud rate generator constant) */
 491 
 492 /* Read Register 13 (upper byte of baud rate generator constant) */
 493 
 494 /* Read Register 15 (value of WR 15) */
 495 
 496 
 497 /* 8536 register definitions */
 498 
 499 #define CIO_MICR        0x00    /* Master interrupt control register */
 500 #define CIO_MCCR        0x01    /* Master configuration control register */
 501 #define CIO_CTMS1       0x1c    /* Counter/timer mode specification #1 */
 502 #define CIO_CTMS2       0x1d    /* Counter/timer mode specification #2 */
 503 #define CIO_CTMS3       0x1e    /* Counter/timer mode specification #3 */
 504 #define CIO_IVR         0x04    /* Interrupt vector register */
 505 
 506 #define CIO_CSR1        0x0a    /* Command and status register CTC #1 */
 507 #define CIO_CSR2        0x0b    /* Command and status register CTC #2 */
 508 #define CIO_CSR3        0x0c    /* Command and status register CTC #3 */
 509 
 510 #define CIO_CT1MSB      0x16    /* CTC #1 Timer constant - MSB */
 511 #define CIO_CT1LSB      0x17    /* CTC #1 Timer constant - LSB */
 512 #define CIO_CT2MSB      0x18    /* CTC #2 Timer constant - MSB */
 513 #define CIO_CT2LSB      0x19    /* CTC #2 Timer constant - LSB */
 514 #define CIO_CT3MSB      0x1a    /* CTC #3 Timer constant - MSB */
 515 #define CIO_CT3LSB      0x1b    /* CTC #3 Timer constant - LSB */
 516 #define CIO_PDCA        0x23    /* Port A data direction control */
 517 #define CIO_PDCB        0x2b    /* Port B data direction control */
 518 
 519 #define CIO_GCB         0x04    /* CTC Gate command bit */
 520 #define CIO_TCB         0x02    /* CTC Trigger command bit */
 521 #define CIO_IE          0xc0    /* CTC Interrupt enable (set) */
 522 #define CIO_CIP         0x20    /* CTC Clear interrupt pending */
 523 #define CIO_IP          0x20    /* CTC Interrupt pending */
 524 
 525 
 526 /* 8580/85180/85280 Enhanced SCC register definitions */
 527 
 528 /* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
 529 #define AUTOTXF 0x01            /* Auto Tx Flag */
 530 #define AUTOEOM 0x02            /* Auto EOM Latch Reset */
 531 #define AUTORTS 0x04            /* Auto RTS */
 532 #define TXDNRZI 0x08            /* TxD Pulled High in SDLC NRZI mode */
 533 #define FASTDTR 0x10            /* Fast DTR/REQ Mode */
 534 #define CRCCBCR 0x20            /* CRC Check Bytes Completely Received */
 535 #define EXTRDEN 0x40            /* Extended Read Enabled */
 536 
 537 /* Write Register 15 (external/status interrupt control) */
 538 #define SHDLCE  1               /* SDLC/HDLC Enhancements Enable */
 539 #define FIFOE   4               /* FIFO Enable */
 540 
 541 /* Read Register 6 (frame status FIFO) */
 542 #define BCLSB   0xff            /* LSB of 14 bits count */
 543 
 544 /* Read Register 7 (frame status FIFO) */
 545 #define BCMSB   0x3f            /* MSB of 14 bits count */
 546 #define FDA     0x40            /* FIFO Data Available Status */
 547 #define FOY     0x80            /* FIFO Overflow Status */
 548 
 549 /* global functions */
 550 
 551 extern long scc_init(long kmem_start);
 552 
 553 #endif  /* _SCC_H */

/* [previous][next][first][last][top][bottom][index][help] */