This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
1
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( DPT, DPT, "SmartCache/Raid"),
45 DEVICE( S3, S3_864_1, "Vision 864-P"),
46 DEVICE( S3, S3_864_2, "Vision 864-P"),
47 DEVICE( S3, S3_868, "Vision 868"),
48 DEVICE( S3, S3_928, "Vision 928-P"),
49 DEVICE( S3, S3_964_1, "Vision 964-P"),
50 DEVICE( S3, S3_964_2, "Vision 964-P"),
51 DEVICE( S3, S3_811, "Trio32/Trio64"),
52 DEVICE( S3, S3_968, "Vision 968"),
53 DEVICE( OPTI, OPTI_82C822, "82C822"),
54 DEVICE( OPTI, OPTI_82C621, "82C621"),
55 DEVICE( OPTI, OPTI_82C557, "82C557"),
56 DEVICE( OPTI, OPTI_82C558, "82C558"),
57 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
58 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
59 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
60 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
61 DEVICE( DEC, DEC_TULIP, "DC21040"),
62 DEVICE( DEC, DEC_TULIP_FAST, "DC21040"),
63 DEVICE( DEC, DEC_FDDI, "DEFPA"),
64 DEVICE( DEC, DEC_BRD, "DC21050"),
65 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
66 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
67 DEVICE( INTEL, INTEL_82378, "82378IB"),
68 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
69 DEVICE( INTEL, INTEL_82375, "82375EB"),
70 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
71 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
72 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
73 DEVICE( INTEL, INTEL_82371, "82471 Triton"),
74 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
75 DEVICE( ATI, ATI_M32, "Mach 32"),
76 DEVICE( ATI, ATI_M64, "Mach 64"),
77 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
78 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
79 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
80 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
81 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
82 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
83 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
84 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
85 DEVICE( N9, N9_I128, "Imagine 128"),
86 DEVICE( AI, AI_M1435, "M1435"),
87 DEVICE( AL, AL_M1445, "M1445"),
88 DEVICE( AL, AL_M1449, "M1449"),
89 DEVICE( AL, AL_M1451, "M1451"),
90 DEVICE( AL, AL_M4803, "M4803"),
91 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
92 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
93 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
94 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
95 DEVICE( CMD, CMD_640, "640A"),
96 DEVICE( VISION, VISION_QD8500, "QD-8500"),
97 DEVICE( VISION, VISION_QD8580, "QD-8580"),
98 DEVICE( AMD, AMD_LANCE, "79C970"),
99 DEVICE( AMD, AMD_SCSI, "53C974"),
100 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
101 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
102 DEVICE( ADL, ADL_2301, "2301"),
103 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
104 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
105 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
106 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
107 DEVICE( NS, NS_87410, "87410"),
108 DEVICE( VIA, VIA_82C505, "VT 82C505"),
109 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
110 DEVICE( VIA, VIA_82C561, "VT 82C561"),
111 DEVICE( SI, SI_496, "85C496"),
112 DEVICE( SI, SI_501, "85C501"),
113 DEVICE( SI, SI_503, "85C503"),
114 DEVICE( SI, SI_601, "85C601"),
115 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
116 DEVICE( IMS, IMS_8849, "8849"),
117 DEVICE( ZEINET, ZEINET_1221, "1221"),
118 DEVICE( EF, EF_ATM, "155P-MF1"),
119 DEVICE( HER, HER_STING, "Stingray"),
120 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
121 DEVICE( CT, CT_65545, "65545"),
122 DEVICE( FD, FD_36C70, "TMC-18C30"),
123 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
124 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
125 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
126 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
127 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
128 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
129 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
130 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
131 DEVICE( X, X_AGX016, "ITT AGX016")
132 };
133
134
135 #ifdef CONFIG_PCI_OPTIMIZE
136
137
138
139
140
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142
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149
150
151
152 struct optimization_type {
153 char *type;
154 char *off;
155 char *on;
156 } bridge_optimization[] = {
157 {"Cache L2", "write trough", "write back"},
158 {"CPU-PCI posted write", "off", "on"},
159 {"CPU-Memory posted write", "off", "on"},
160 {"PCI-Memory posted write", "off", "on"},
161 {"PCI burst", "off", "on"}
162 };
163
164 #define NUM_OPTIMIZATIONS \
165 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
166
167 struct bridge_mapping_type {
168 unsigned char addr;
169 unsigned char mask;
170 unsigned char value;
171 } bridge_mapping[] = {
172
173
174
175
176
177
178
179 {0x0 ,0x02 ,0x02 },
180 {0x53 ,0x02 ,0x02 },
181 {0x53 ,0x01 ,0x01 },
182 {0x54 ,0x01 ,0x01 },
183 {0x54 ,0x02 ,0x02 },
184
185
186
187
188
189 {0x50 ,0x10 ,0x00 },
190 {0x51 ,0x40 ,0x40 },
191 {0x0 ,0x0 ,0x0 },
192 {0x0 ,0x0 ,0x0 },
193 {0x0 ,0x0 ,0x0 },
194
195
196
197
198
199
200 {0x0 ,0x1 ,0x1 },
201 {0x0 ,0x2 ,0x0 },
202 {0x0 ,0x0 ,0x0 },
203 {0x0 ,0x0 ,0x0 },
204 {0x0 ,0x0 ,0x0 }
205 };
206
207 #endif
208
209
210
211
212
213
214 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
215 {
216 int i;
217
218 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
219 if (dev_info[i].vendor == vendor &&
220 dev_info[i].device == dev)
221 {
222 return &dev_info[i];
223 }
224 }
225 return 0;
226 }
227
228
229 char *pci_strbioserr (int error)
230 {
231 switch (error) {
232 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
233 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
234 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
235 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
236 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
237 case PCIBIOS_SET_FAILED: return "SET_FAILED";
238 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
239 default: return "Unknown error status";
240 }
241 }
242
243
244 const char *pci_strclass (unsigned int class)
245 {
246 switch (class >> 8) {
247 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
248 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
249
250 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
251 case PCI_CLASS_STORAGE_IDE: return "IDE controller";
252 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
253 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
254 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
255
256 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
257 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
258 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
259 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
260
261 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
262 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
263 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
264
265 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
266 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
267 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
268
269 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
270 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
271 case PCI_CLASS_MEMORY_OTHER: return "Memory";
272
273 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
274 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
275 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
276 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
277 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
278 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
279 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
280
281 default: return "Unknown class";
282 }
283 }
284
285
286 const char *pci_strvendor(unsigned int vendor)
287 {
288 switch (vendor) {
289 case PCI_VENDOR_ID_NCR: return "NCR";
290 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
291 case PCI_VENDOR_ID_DPT: return "DPT";
292 case PCI_VENDOR_ID_S3: return "S3 Inc.";
293 case PCI_VENDOR_ID_OPTI: return "OPTI";
294 case PCI_VENDOR_ID_UMC: return "UMC";
295 case PCI_VENDOR_ID_DEC: return "DEC";
296 case PCI_VENDOR_ID_MATROX: return "Matrox";
297 case PCI_VENDOR_ID_INTEL: return "Intel";
298 case PCI_VENDOR_ID_SMC: return "SMC";
299 case PCI_VENDOR_ID_ATI: return "ATI";
300 case PCI_VENDOR_ID_WEITEK: return "Weitek";
301 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
302 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
303 case PCI_VENDOR_ID_N9: return "Number Nine";
304 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
305 case PCI_VENDOR_ID_AL: return "Acer Labs";
306 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
307 case PCI_VENDOR_ID_CMD: return "CMD";
308 case PCI_VENDOR_ID_VISION: return "Vision";
309 case PCI_VENDOR_ID_AMD: return "AMD";
310 case PCI_VENDOR_ID_VLSI: return "VLSI";
311 case PCI_VENDOR_ID_ADL: return "Advance Logic";
312 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
313 case PCI_VENDOR_ID_TRIDENT: return "Trident";
314 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
315 case PCI_VENDOR_ID_NS: return "NS";
316 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
317 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
318 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
319 case PCI_VENDOR_ID_IMS: return "IMS";
320 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
321 case PCI_VENDOR_ID_EF: return "Efficient Networks";
322 case PCI_VENDOR_ID_HER: return "Hercules";
323 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
324 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
325 case PCI_VENDOR_ID_FD: return "Future Domain";
326 case PCI_VENDOR_ID_WINBOND: return "Winbond";
327 case PCI_VENDOR_ID_3COM: return "3Com";
328 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
329 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
330 default: return "Unknown vendor";
331 }
332 }
333
334
335 const char *pci_strdev(unsigned int vendor, unsigned int device)
336 {
337 struct pci_dev_info *info;
338
339 info = pci_lookup_dev(vendor, device);
340 return info ? info->name : "Unknown device";
341 }
342
343
344
345
346
347
348 static void burst_bridge(unsigned char bus, unsigned char devfn,
349 unsigned char pos, int turn_on)
350 {
351 #ifdef CONFIG_PCI_OPTIMIZE
352 struct bridge_mapping_type *bmap;
353 unsigned char val;
354 int i;
355
356 pos *= NUM_OPTIMIZATIONS;
357 printk("PCI bridge optimization.\n");
358 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
359 printk(" %s: ", bridge_optimization[i].type);
360 bmap = &bridge_mapping[pos + i];
361 if (!bmap->addr) {
362 printk("Not supported.");
363 } else {
364 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
365 if ((val & bmap->mask) == bmap->value) {
366 printk("%s.", bridge_optimization[i].on);
367 if (!turn_on) {
368 pcibios_write_config_byte(bus, devfn,
369 bmap->addr,
370 (val | bmap->mask)
371 - bmap->value);
372 printk("Changed! Now %s.", bridge_optimization[i].off);
373 }
374 } else {
375 printk("%s.", bridge_optimization[i].off);
376 if (turn_on) {
377 pcibios_write_config_byte(bus, devfn,
378 bmap->addr,
379 (val & (0xff - bmap->mask))
380 + bmap->value);
381 printk("Changed! Now %s.", bridge_optimization[i].on);
382 }
383 }
384 }
385 printk("\n");
386 }
387 #endif
388 }
389
390
391
392
393
394
395
396
397 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
398 {
399 unsigned long base;
400 unsigned int l, class_rev, bus, devfn;
401 unsigned short vendor, device, status;
402 unsigned char bist, latency, min_gnt, max_lat;
403 int reg, len = 0;
404 const char *str;
405
406 bus = dev->bus->number;
407 devfn = dev->devfn;
408
409 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
410 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
411 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
412 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
413 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
414 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
415 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
416 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
417 if (len + 80 > size) {
418 return -1;
419 }
420 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
421 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
422
423 if (len + 80 > size) {
424 return -1;
425 }
426 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
427 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
428 pci_strdev(vendor, device), class_rev & 0xff);
429
430 if (!pci_lookup_dev(vendor, device)) {
431 len += sprintf(buf + len,
432 "Vendor id=%x. Device id=%x.\n ",
433 vendor, device);
434 }
435
436 str = 0;
437 switch (status & PCI_STATUS_DEVSEL_MASK) {
438 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
439 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
440 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
441 }
442 if (len + strlen(str) > size) {
443 return -1;
444 }
445 len += sprintf(buf + len, str);
446
447 if (status & PCI_STATUS_FAST_BACK) {
448 # define fast_b2b_capable "Fast back-to-back capable. "
449 if (len + strlen(fast_b2b_capable) > size) {
450 return -1;
451 }
452 len += sprintf(buf + len, fast_b2b_capable);
453 # undef fast_b2b_capable
454 }
455
456 if (bist & PCI_BIST_CAPABLE) {
457 # define BIST_capable "BIST capable. "
458 if (len + strlen(BIST_capable) > size) {
459 return -1;
460 }
461 len += sprintf(buf + len, BIST_capable);
462 # undef BIST_capable
463 }
464
465 if (dev->irq) {
466 if (len + 40 > size) {
467 return -1;
468 }
469 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
470 }
471
472 if (dev->master) {
473 if (len + 80 > size) {
474 return -1;
475 }
476 len += sprintf(buf + len, "Master Capable. ");
477 if (latency)
478 len += sprintf(buf + len, "Latency=%d. ", latency);
479 else
480 len += sprintf(buf + len, "No bursts. ");
481 if (min_gnt)
482 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
483 if (max_lat)
484 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
485 }
486
487 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
488 if (len + 40 > size) {
489 return -1;
490 }
491 pcibios_read_config_dword(bus, devfn, reg, &l);
492 base = l;
493 if (!base) {
494 continue;
495 }
496
497 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
498 len += sprintf(buf + len,
499 "\n I/O at 0x%lx.",
500 base & PCI_BASE_ADDRESS_IO_MASK);
501 } else {
502 const char *pref, *type = "unknown";
503
504 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
505 pref = "P";
506 } else {
507 pref = "Non-p";
508 }
509 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
510 case PCI_BASE_ADDRESS_MEM_TYPE_32:
511 type = "32 bit"; break;
512 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
513 type = "20 bit"; break;
514 case PCI_BASE_ADDRESS_MEM_TYPE_64:
515 type = "64 bit";
516
517 reg += 4;
518 pcibios_read_config_dword(bus, devfn, reg, &l);
519 base |= ((u64) l) << 32;
520 break;
521 }
522 len += sprintf(buf + len,
523 "\n %srefetchable %s memory at "
524 "0x%lx.", pref, type,
525 base & PCI_BASE_ADDRESS_MEM_MASK);
526 }
527 }
528
529 len += sprintf(buf + len, "\n");
530 return len;
531 }
532
533
534
535
536
537
538 int get_pci_list(char *buf)
539 {
540 int nprinted, len, size;
541 struct pci_dev *dev;
542 # define MSG "\nwarning: page-size limit reached!\n"
543
544
545 size = PAGE_SIZE - (strlen(MSG) + 1);
546 len = sprintf(buf, "PCI devices found:\n");
547
548 for (dev = pci_devices; dev; dev = dev->next) {
549 nprinted = sprint_dev_config(dev, buf + len, size - len);
550 if (nprinted < 0) {
551 return len + sprintf(buf + len, MSG);
552 }
553 len += nprinted;
554 }
555 return len;
556 }
557
558
559
560
561
562
563 static void *pci_malloc(long size, unsigned long *mem_startp)
564 {
565 void *mem;
566
567 #ifdef DEBUG
568 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
569 #endif
570 mem = (void*) *mem_startp;
571 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
572 memset(mem, 0, size);
573 return mem;
574 }
575
576
577 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
578 {
579 unsigned int devfn, l, max;
580 unsigned char cmd, tmp, hdr_type = 0;
581 struct pci_dev_info *info;
582 struct pci_dev *dev;
583 struct pci_bus *child;
584
585 #ifdef DEBUG
586 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
587 #endif
588
589 max = bus->secondary;
590 for (devfn = 0; devfn < 0xff; ++devfn) {
591 if (PCI_FUNC(devfn) == 0) {
592 pcibios_read_config_byte(bus->number, devfn,
593 PCI_HEADER_TYPE, &hdr_type);
594 } else if (!(hdr_type & 0x80)) {
595
596 continue;
597 }
598
599 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
600 &l);
601
602 if (l == 0xffffffff || l == 0x00000000) {
603 hdr_type = 0;
604 continue;
605 }
606
607 dev = pci_malloc(sizeof(*dev), mem_startp);
608 dev->bus = bus;
609
610
611
612
613
614 dev->next = pci_devices;
615 pci_devices = dev;
616
617 dev->devfn = devfn;
618 dev->vendor = l & 0xffff;
619 dev->device = (l >> 16) & 0xffff;
620
621
622
623
624
625
626 info = pci_lookup_dev(dev->vendor, dev->device);
627 if (!info) {
628 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
629 } else {
630
631 if (info->bridge_type != 0xff) {
632 burst_bridge(bus->number, devfn,
633 info->bridge_type, 1);
634 }
635 }
636
637
638 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
639 &cmd);
640 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
641 cmd | PCI_COMMAND_MASTER);
642 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
643 &tmp);
644 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
645 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
646 cmd);
647
648
649 pcibios_read_config_byte(bus->number, devfn,
650 PCI_INTERRUPT_LINE, &dev->irq);
651
652
653 pcibios_read_config_dword(bus->number, devfn,
654 PCI_CLASS_REVISION, &l);
655 l = l >> 8;
656 dev->class = l;
657
658
659
660
661 dev->sibling = bus->devices;
662 bus->devices = dev;
663
664 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
665 unsigned int buses;
666
667
668
669
670 child = pci_malloc(sizeof(*child), mem_startp);
671 child->next = bus->children;
672 bus->children = child;
673 child->self = dev;
674 child->parent = bus;
675
676
677
678
679
680 child->number = child->secondary = ++max;
681 child->primary = bus->secondary;
682 child->subordinate = 0xff;
683
684
685
686
687 pcibios_write_config_word(bus->number, devfn,
688 PCI_COMMAND, 0x0000);
689 pcibios_write_config_word(bus->number, devfn,
690 PCI_STATUS, 0xffff);
691
692
693
694 pcibios_read_config_dword(bus->number, devfn, 0x18,
695 &buses);
696 buses &= 0xff000000;
697 buses |= (((unsigned int)(child->primary) << 0) |
698 ((unsigned int)(child->secondary) << 8) |
699 ((unsigned int)(child->subordinate) << 16));
700 pcibios_write_config_dword(bus->number, devfn, 0x18,
701 buses);
702
703
704
705 max = scan_bus(child, mem_startp);
706
707
708
709
710 child->subordinate = max;
711 buses = (buses & 0xff00ffff)
712 | ((unsigned int)(child->subordinate) << 16);
713 pcibios_write_config_dword(bus->number, devfn, 0x18,
714 buses);
715 }
716 }
717
718
719
720
721
722
723
724 return max;
725 }
726
727
728 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
729 {
730 mem_start = pcibios_init(mem_start, mem_end);
731
732 if (!pcibios_present()) {
733 printk("pci_init: no BIOS32 detected\n");
734 return mem_start;
735 }
736
737 printk("Probing PCI hardware.\n");
738
739 memset(&pci_root, 0, sizeof(pci_root));
740 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
741
742
743 mem_start = pcibios_fixup(mem_start, mem_end);
744
745 #ifdef DEBUG
746 {
747 int len = get_pci_list(mem_start);
748 if (len) {
749 ((char*)mem_start)[len] = '\0';
750 printk("%s\n", mem_start);
751 }
752 }
753 #endif
754 return mem_start;
755 }