tag | line | file | source code |
wr | 887 | drivers/char/scc.c | wr(scc,R12,tc & 255); /* brg rate LOW */ |
wr | 888 | drivers/char/scc.c | wr(scc,R13,tc >> 8); /* brg rate HIGH */ |
wr | 904 | drivers/char/scc.c | wr(scc, R14, BRSRC); /* BRG source = PCLK */ |
wr | 916 | drivers/char/scc.c | wr(scc,R1,0); /* no W/REQ operation */ |
wr | 917 | drivers/char/scc.c | wr(scc,R3,Rx8|RxCRC_ENAB); /* RX 8 bits/char, CRC, disabled */ |
wr | 918 | drivers/char/scc.c | wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */ |
wr | 919 | drivers/char/scc.c | wr(scc,R5,Tx8|DTR|TxCRC_ENAB); /* TX 8 bits/char, disabled, DTR */ |
wr | 920 | drivers/char/scc.c | wr(scc,R6,0); /* SDLC address zero (not used) */ |
wr | 921 | drivers/char/scc.c | wr(scc,R7,FLAG); /* SDLC flag value */ |
wr | 922 | drivers/char/scc.c | wr(scc,R9,VIS); /* vector includes status */ |
wr | 923 | drivers/char/scc.c | wr(scc,R10,(scc->modem.nrz? NRZ : NRZI)|CRCPS|ABUNDER); /* abort on underrun, preset CRC generator, NRZ(I) */ |
wr | 924 | drivers/char/scc.c | wr(scc,R14, 0); |
wr | 956 | drivers/char/scc.c | wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP); |
wr | 961 | drivers/char/scc.c | wr(scc, R11, ((Board & BAYCOM)? TRxCDP : TRxCBR) | RCDPLL|TCRTxCP|TRxCOI); |
wr | 966 | drivers/char/scc.c | wr(scc, R11, (Board & BAYCOM)? RCTRxCP|TCRTxCP : RCRTxCP|TCTRxCP); |
wr | 973 | drivers/char/scc.c | wr(scc,R15,((Board & BAYCOM) ? 0 : CTSIE)|BRKIE|DCDIE|TxUIE); |
wr | 978 | drivers/char/scc.c | wr(scc,R7,AUTOEOM); |
wr | 1035 | drivers/char/scc.c | wr(scc, R11, RCDPLL|TCBR|TRxCOI|TRxCBR); |
wr | 1044 | drivers/char/scc.c | wr(scc, R11, RCDPLL|TCDPLL|TRxCOI|TRxCDP); |
wr | 1625 | drivers/char/scc.c | wr(scc,R1,0); /* disable interrupts */ |
wr | 1626 | drivers/char/scc.c | wr(scc,R3,0); |