This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/bios32.h>
13 #include <linux/pci.h>
14 #include <linux/string.h>
15
16 #include <asm/page.h>
17
18 struct pci_bus pci_root;
19 struct pci_dev *pci_devices = 0;
20
21
22
23
24
25
26
27
28
29
30
31 #define DEVICE(vid,did,name) \
32 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
33
34 #define BRIDGE(vid,did,name,bridge) \
35 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
36
37 struct pci_dev_info dev_info[] = {
38 DEVICE( NCR, NCR_53C810, "53c810"),
39 DEVICE( NCR, NCR_53C815, "53c815"),
40 DEVICE( NCR, NCR_53C820, "53c820"),
41 DEVICE( NCR, NCR_53C825, "53c825"),
42 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
43 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
44 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
45 DEVICE( DPT, DPT, "SmartCache/Raid"),
46 DEVICE( S3, S3_864_1, "Vision 864-P"),
47 DEVICE( S3, S3_864_2, "Vision 864-P"),
48 DEVICE( S3, S3_868, "Vision 868"),
49 DEVICE( S3, S3_928, "Vision 928-P"),
50 DEVICE( S3, S3_964_1, "Vision 964-P"),
51 DEVICE( S3, S3_964_2, "Vision 964-P"),
52 DEVICE( S3, S3_811, "Trio32/Trio64"),
53 DEVICE( S3, S3_968, "Vision 968"),
54 DEVICE( OPTI, OPTI_82C822, "82C822"),
55 DEVICE( OPTI, OPTI_82C621, "82C621"),
56 DEVICE( OPTI, OPTI_82C557, "82C557"),
57 DEVICE( OPTI, OPTI_82C558, "82C558"),
58 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
59 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
60 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
61 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
62 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_BRD, "DC21050"),
68 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
69 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
70 DEVICE( INTEL, INTEL_82378, "82378IB"),
71 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
72 DEVICE( INTEL, INTEL_82375, "82375EB"),
73 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
74 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
75 DEVICE( INTEL, INTEL_82437, "82437 Triton"),
76 DEVICE( INTEL, INTEL_82371, "82471 Triton"),
77 DEVICE( INTEL, INTEL_82438, "82438"),
78 DEVICE( INTEL, INTEL_7116, "SAA7116"),
79 DEVICE( INTEL, INTEL_82865, "82865"),
80 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
81 DEVICE( SMC, SMC_37C922, "FDC 37C922"),
82 DEVICE( ATI, ATI_M32, "Mach 32"),
83 DEVICE( ATI, ATI_M64, "Mach 64"),
84 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
85 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
86 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
87 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
88 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
89 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
90 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
91 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
92 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
93 DEVICE( N9, N9_I128, "Imagine 128"),
94 DEVICE( AI, AI_M1435, "M1435"),
95 DEVICE( AL, AL_M1445, "M1445"),
96 DEVICE( AL, AL_M1449, "M1449"),
97 DEVICE( AL, AL_M1451, "M1451"),
98 DEVICE( AL, AL_M1461, "M1461"),
99 DEVICE( AL, AL_M4803, "M4803"),
100 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
101 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
102 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
103 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
104 DEVICE( CMD, CMD_640, "640A"),
105 DEVICE( VISION, VISION_QD8500, "QD-8500"),
106 DEVICE( VISION, VISION_QD8580, "QD-8580"),
107 DEVICE( AMD, AMD_LANCE, "79C970"),
108 DEVICE( AMD, AMD_SCSI, "53C974"),
109 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
110 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
111 DEVICE( ADL, ADL_2301, "2301"),
112 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
113 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
114 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
115 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
116 DEVICE( NS, NS_87410, "87410"),
117 DEVICE( VIA, VIA_82C505, "VT 82C505"),
118 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
119 DEVICE( VIA, VIA_82C561, "VT 82C561"),
120 DEVICE( SI, SI_496, "85C496"),
121 DEVICE( SI, SI_501, "85C501"),
122 DEVICE( SI, SI_503, "85C503"),
123 DEVICE( SI, SI_601, "85C601"),
124 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
125 DEVICE( IMS, IMS_8849, "8849"),
126 DEVICE( ZEINET, ZEINET_1221, "1221"),
127 DEVICE( EF, EF_ATM, "155P-MF1"),
128 DEVICE( HER, HER_STING, "Stingray"),
129 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
130 DEVICE( CT, CT_65545, "65545"),
131 DEVICE( FD, FD_36C70, "TMC-18C30"),
132 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
133 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
134 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
135 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
136 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
137 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
138 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
139 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
140 DEVICE( X, X_AGX016, "ITT AGX016"),
141 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
142 DEVICE( HP, HP_J2585A, "J2585A"),
143 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
144 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290")
145 };
146
147
148 #ifdef CONFIG_PCI_OPTIMIZE
149
150
151
152
153
154
155
156
157
158
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161
162
163
164
165 struct optimization_type {
166 const char *type;
167 const char *off;
168 const char *on;
169 } bridge_optimization[] = {
170 {"Cache L2", "write trough", "write back"},
171 {"CPU-PCI posted write", "off", "on"},
172 {"CPU-Memory posted write", "off", "on"},
173 {"PCI-Memory posted write", "off", "on"},
174 {"PCI burst", "off", "on"}
175 };
176
177 #define NUM_OPTIMIZATIONS \
178 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
179
180 struct bridge_mapping_type {
181 unsigned char addr;
182 unsigned char mask;
183 unsigned char value;
184 } bridge_mapping[] = {
185
186
187
188
189
190
191
192 {0x0 ,0x02 ,0x02 },
193 {0x53 ,0x02 ,0x02 },
194 {0x53 ,0x01 ,0x01 },
195 {0x54 ,0x01 ,0x01 },
196 {0x54 ,0x02 ,0x02 },
197
198
199
200
201
202 {0x50 ,0x10 ,0x00 },
203 {0x51 ,0x40 ,0x40 },
204 {0x0 ,0x0 ,0x0 },
205 {0x0 ,0x0 ,0x0 },
206 {0x0 ,0x0 ,0x0 },
207
208
209
210
211
212
213 {0x0 ,0x1 ,0x1 },
214 {0x0 ,0x2 ,0x0 },
215 {0x0 ,0x0 ,0x0 },
216 {0x0 ,0x0 ,0x0 },
217 {0x0 ,0x0 ,0x0 }
218 };
219
220 #endif
221
222
223
224
225
226
227 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
228 {
229 int i;
230
231 for (i = 0; i < sizeof(dev_info)/sizeof(dev_info[0]); ++i) {
232 if (dev_info[i].vendor == vendor &&
233 dev_info[i].device == dev)
234 {
235 return &dev_info[i];
236 }
237 }
238 return 0;
239 }
240
241
242 const char *pci_strbioserr (int error)
243 {
244 switch (error) {
245 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
246 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
247 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
248 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
249 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
250 case PCIBIOS_SET_FAILED: return "SET_FAILED";
251 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
252 default: return "Unknown error status";
253 }
254 }
255
256
257 const char *pci_strclass (unsigned int class)
258 {
259 switch (class >> 8) {
260 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
261 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
262
263 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
264 case PCI_CLASS_STORAGE_IDE: return "IDE controller";
265 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
266 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
267 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
268 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
269
270 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
271 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
272 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
273 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
274 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
275
276 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
277 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
278 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
279
280 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
281 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
282 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
283
284 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
285 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
286 case PCI_CLASS_MEMORY_OTHER: return "Memory";
287
288 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
289 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
290 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
291 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
292 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
293 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
294 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
295 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
296 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
297
298 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
299 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
300 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
301
302 case PCI_CLASS_SYSTEM_PIC: return "PIC";
303 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
304 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
305 case PCI_CLASS_SYSTEM_RTC: return "RTC";
306 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
307
308 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
309 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
310 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
311 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
312
313 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
314 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
315
316 case PCI_CLASS_PROCESSOR_386: return "386";
317 case PCI_CLASS_PROCESSOR_486: return "486";
318 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
319 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
320 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
321 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
322
323 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
324 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
325 case PCI_CLASS_SERIAL_SSA: return "SSA";
326 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
327
328 default: return "Unknown class";
329 }
330 }
331
332
333 const char *pci_strvendor(unsigned int vendor)
334 {
335 switch (vendor) {
336 case PCI_VENDOR_ID_NCR: return "NCR";
337 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
338 case PCI_VENDOR_ID_DPT: return "DPT";
339 case PCI_VENDOR_ID_S3: return "S3 Inc.";
340 case PCI_VENDOR_ID_OPTI: return "OPTI";
341 case PCI_VENDOR_ID_UMC: return "UMC";
342 case PCI_VENDOR_ID_DEC: return "DEC";
343 case PCI_VENDOR_ID_MATROX: return "Matrox";
344 case PCI_VENDOR_ID_INTEL: return "Intel";
345 case PCI_VENDOR_ID_SMC: return "SMC";
346 case PCI_VENDOR_ID_ATI: return "ATI";
347 case PCI_VENDOR_ID_WEITEK: return "Weitek";
348 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
349 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
350 case PCI_VENDOR_ID_N9: return "Number Nine";
351 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
352 case PCI_VENDOR_ID_AL: return "Acer Labs";
353 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
354 case PCI_VENDOR_ID_CMD: return "CMD";
355 case PCI_VENDOR_ID_VISION: return "Vision";
356 case PCI_VENDOR_ID_AMD: return "AMD";
357 case PCI_VENDOR_ID_VLSI: return "VLSI";
358 case PCI_VENDOR_ID_ADL: return "Advance Logic";
359 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
360 case PCI_VENDOR_ID_TRIDENT: return "Trident";
361 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
362 case PCI_VENDOR_ID_NS: return "NS";
363 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
364 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
365 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
366 case PCI_VENDOR_ID_IMS: return "IMS";
367 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
368 case PCI_VENDOR_ID_EF: return "Efficient Networks";
369 case PCI_VENDOR_ID_HER: return "Hercules";
370 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
371 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
372 case PCI_VENDOR_ID_FD: return "Future Domain";
373 case PCI_VENDOR_ID_WINBOND: return "Winbond";
374 case PCI_VENDOR_ID_3COM: return "3Com";
375 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
376 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
377 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
378 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
379 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
380 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
381 default: return "Unknown vendor";
382 }
383 }
384
385
386 const char *pci_strdev(unsigned int vendor, unsigned int device)
387 {
388 struct pci_dev_info *info;
389
390 info = pci_lookup_dev(vendor, device);
391 return info ? info->name : "Unknown device";
392 }
393
394
395
396
397
398
399 static void burst_bridge(unsigned char bus, unsigned char devfn,
400 unsigned char pos, int turn_on)
401 {
402 #ifdef CONFIG_PCI_OPTIMIZE
403 struct bridge_mapping_type *bmap;
404 unsigned char val;
405 int i;
406
407 pos *= NUM_OPTIMIZATIONS;
408 printk("PCI bridge optimization.\n");
409 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
410 printk(" %s: ", bridge_optimization[i].type);
411 bmap = &bridge_mapping[pos + i];
412 if (!bmap->addr) {
413 printk("Not supported.");
414 } else {
415 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
416 if ((val & bmap->mask) == bmap->value) {
417 printk("%s.", bridge_optimization[i].on);
418 if (!turn_on) {
419 pcibios_write_config_byte(bus, devfn,
420 bmap->addr,
421 (val | bmap->mask)
422 - bmap->value);
423 printk("Changed! Now %s.", bridge_optimization[i].off);
424 }
425 } else {
426 printk("%s.", bridge_optimization[i].off);
427 if (turn_on) {
428 pcibios_write_config_byte(bus, devfn,
429 bmap->addr,
430 (val & (0xff - bmap->mask))
431 + bmap->value);
432 printk("Changed! Now %s.", bridge_optimization[i].on);
433 }
434 }
435 }
436 printk("\n");
437 }
438 #endif
439 }
440
441
442
443
444
445
446
447
448 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
449 {
450 unsigned long base;
451 unsigned int l, class_rev, bus, devfn;
452 unsigned short vendor, device, status;
453 unsigned char bist, latency, min_gnt, max_lat;
454 int reg, len = 0;
455 const char *str;
456
457 bus = dev->bus->number;
458 devfn = dev->devfn;
459
460 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
461 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
462 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
463 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
464 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
465 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
466 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
467 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
468 if (len + 80 > size) {
469 return -1;
470 }
471 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
472 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
473
474 if (len + 80 > size) {
475 return -1;
476 }
477 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
478 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
479 pci_strdev(vendor, device), class_rev & 0xff);
480
481 if (!pci_lookup_dev(vendor, device)) {
482 len += sprintf(buf + len,
483 "Vendor id=%x. Device id=%x.\n ",
484 vendor, device);
485 }
486
487 str = 0;
488 switch (status & PCI_STATUS_DEVSEL_MASK) {
489 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
490 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
491 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
492 }
493 if (len + strlen(str) > size) {
494 return -1;
495 }
496 len += sprintf(buf + len, str);
497
498 if (status & PCI_STATUS_FAST_BACK) {
499 # define fast_b2b_capable "Fast back-to-back capable. "
500 if (len + strlen(fast_b2b_capable) > size) {
501 return -1;
502 }
503 len += sprintf(buf + len, fast_b2b_capable);
504 # undef fast_b2b_capable
505 }
506
507 if (bist & PCI_BIST_CAPABLE) {
508 # define BIST_capable "BIST capable. "
509 if (len + strlen(BIST_capable) > size) {
510 return -1;
511 }
512 len += sprintf(buf + len, BIST_capable);
513 # undef BIST_capable
514 }
515
516 if (dev->irq) {
517 if (len + 40 > size) {
518 return -1;
519 }
520 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
521 }
522
523 if (dev->master) {
524 if (len + 80 > size) {
525 return -1;
526 }
527 len += sprintf(buf + len, "Master Capable. ");
528 if (latency)
529 len += sprintf(buf + len, "Latency=%d. ", latency);
530 else
531 len += sprintf(buf + len, "No bursts. ");
532 if (min_gnt)
533 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
534 if (max_lat)
535 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
536 }
537
538 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
539 if (len + 40 > size) {
540 return -1;
541 }
542 pcibios_read_config_dword(bus, devfn, reg, &l);
543 base = l;
544 if (!base) {
545 continue;
546 }
547
548 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
549 len += sprintf(buf + len,
550 "\n I/O at 0x%lx.",
551 base & PCI_BASE_ADDRESS_IO_MASK);
552 } else {
553 const char *pref, *type = "unknown";
554
555 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
556 pref = "P";
557 } else {
558 pref = "Non-p";
559 }
560 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
561 case PCI_BASE_ADDRESS_MEM_TYPE_32:
562 type = "32 bit"; break;
563 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
564 type = "20 bit"; break;
565 case PCI_BASE_ADDRESS_MEM_TYPE_64:
566 type = "64 bit";
567
568 reg += 4;
569 pcibios_read_config_dword(bus, devfn, reg, &l);
570 base |= ((u64) l) << 32;
571 break;
572 }
573 len += sprintf(buf + len,
574 "\n %srefetchable %s memory at "
575 "0x%lx.", pref, type,
576 base & PCI_BASE_ADDRESS_MEM_MASK);
577 }
578 }
579
580 len += sprintf(buf + len, "\n");
581 return len;
582 }
583
584
585
586
587
588
589 int get_pci_list(char *buf)
590 {
591 int nprinted, len, size;
592 struct pci_dev *dev;
593 # define MSG "\nwarning: page-size limit reached!\n"
594
595
596 size = PAGE_SIZE - (strlen(MSG) + 1);
597 len = sprintf(buf, "PCI devices found:\n");
598
599 for (dev = pci_devices; dev; dev = dev->next) {
600 nprinted = sprint_dev_config(dev, buf + len, size - len);
601 if (nprinted < 0) {
602 return len + sprintf(buf + len, MSG);
603 }
604 len += nprinted;
605 }
606 return len;
607 }
608
609
610
611
612
613
614 static void *pci_malloc(long size, unsigned long *mem_startp)
615 {
616 void *mem;
617
618 #ifdef DEBUG
619 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
620 #endif
621 mem = (void*) *mem_startp;
622 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
623 memset(mem, 0, size);
624 return mem;
625 }
626
627
628 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
629 {
630 unsigned int devfn, l, max;
631 unsigned char cmd, tmp, hdr_type = 0;
632 struct pci_dev_info *info;
633 struct pci_dev *dev;
634 struct pci_bus *child;
635
636 #ifdef DEBUG
637 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
638 #endif
639
640 max = bus->secondary;
641 for (devfn = 0; devfn < 0xff; ++devfn) {
642 if (PCI_FUNC(devfn) == 0) {
643 pcibios_read_config_byte(bus->number, devfn,
644 PCI_HEADER_TYPE, &hdr_type);
645 } else if (!(hdr_type & 0x80)) {
646
647 continue;
648 }
649
650 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
651 &l);
652
653 if (l == 0xffffffff || l == 0x00000000) {
654 hdr_type = 0;
655 continue;
656 }
657
658 dev = pci_malloc(sizeof(*dev), mem_startp);
659 dev->bus = bus;
660
661
662
663
664
665 dev->next = pci_devices;
666 pci_devices = dev;
667
668 dev->devfn = devfn;
669 dev->vendor = l & 0xffff;
670 dev->device = (l >> 16) & 0xffff;
671
672
673
674
675
676
677 info = pci_lookup_dev(dev->vendor, dev->device);
678 if (!info) {
679 printk("Warning : Unknown PCI device. Please read include/linux/pci.h \n");
680 } else {
681
682 if (info->bridge_type != 0xff) {
683 burst_bridge(bus->number, devfn,
684 info->bridge_type, 1);
685 }
686 }
687
688
689 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
690 &cmd);
691 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
692 cmd | PCI_COMMAND_MASTER);
693 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
694 &tmp);
695 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
696 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
697 cmd);
698
699
700 pcibios_read_config_byte(bus->number, devfn,
701 PCI_INTERRUPT_LINE, &dev->irq);
702
703
704 pcibios_read_config_dword(bus->number, devfn,
705 PCI_CLASS_REVISION, &l);
706 l = l >> 8;
707 dev->class = l;
708
709
710
711
712 dev->sibling = bus->devices;
713 bus->devices = dev;
714
715 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
716 unsigned int buses;
717 unsigned short cr;
718
719
720
721
722 child = pci_malloc(sizeof(*child), mem_startp);
723 child->next = bus->children;
724 bus->children = child;
725 child->self = dev;
726 child->parent = bus;
727
728
729
730
731
732 child->number = child->secondary = ++max;
733 child->primary = bus->secondary;
734 child->subordinate = 0xff;
735
736
737
738
739 pcibios_read_config_word(bus->number, devfn,
740 PCI_COMMAND, &cr);
741 pcibios_write_config_word(bus->number, devfn,
742 PCI_COMMAND, 0x0000);
743 pcibios_write_config_word(bus->number, devfn,
744 PCI_STATUS, 0xffff);
745
746
747
748 pcibios_read_config_dword(bus->number, devfn, 0x18,
749 &buses);
750 buses &= 0xff000000;
751 buses |= (((unsigned int)(child->primary) << 0) |
752 ((unsigned int)(child->secondary) << 8) |
753 ((unsigned int)(child->subordinate) << 16));
754 pcibios_write_config_dword(bus->number, devfn, 0x18,
755 buses);
756
757
758
759 max = scan_bus(child, mem_startp);
760
761
762
763
764 child->subordinate = max;
765 buses = (buses & 0xff00ffff)
766 | ((unsigned int)(child->subordinate) << 16);
767 pcibios_write_config_dword(bus->number, devfn, 0x18,
768 buses);
769 pcibios_write_config_word(bus->number, devfn,
770 PCI_COMMAND, cr);
771 }
772 }
773
774
775
776
777
778
779
780 return max;
781 }
782
783
784 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
785 {
786 mem_start = pcibios_init(mem_start, mem_end);
787
788 if (!pcibios_present()) {
789 printk("pci_init: no BIOS32 detected\n");
790 return mem_start;
791 }
792
793 printk("Probing PCI hardware.\n");
794
795 memset(&pci_root, 0, sizeof(pci_root));
796 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
797
798
799 mem_start = pcibios_fixup(mem_start, mem_end);
800
801 #ifdef DEBUG
802 {
803 int len = get_pci_list(mem_start);
804 if (len) {
805 ((char*)mem_start)[len] = '\0';
806 printk("%s\n", mem_start);
807 }
808 }
809 #endif
810 return mem_start;
811 }
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