drivers/pci/pci.c

/* */
This source file includes following definitions.
pci_lookup_dev
pci_strbioserr
pci_strclass
pci_strvendor
pci_strdev
burst_bridge
sprint_dev_config
get_pci_list
pci_malloc
scan_bus
pci_init
   1 /*
   2  * drivers/pci/pci.c
   3  *
   4  * PCI services that are built on top of the BIOS32 service.
   5  *
   6  * Copyright 1993, 1994, 1995 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  */
   9 #include <linux/config.h>
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/bios32.h>
  13 #include <linux/pci.h>
  14 #include <linux/string.h>
  15 
  16 #include <asm/page.h>
  17 
  18 struct pci_bus pci_root;
  19 struct pci_dev *pci_devices = 0;
  20 
  21 
  22 /*
  23  * The bridge_id field is an offset of an item into the array
  24  * BRIDGE_MAPPING_TYPE. 0xff indicates that the device is not a PCI
  25  * bridge, or that we don't know for the moment how to configure it.
  26  * I'm trying to do my best so that the kernel stays small.  Different
  27  * chipset can have same optimization structure. i486 and pentium
  28  * chipsets from the same manufacturer usually have the same
  29  * structure.
  30  */
  31 #define DEVICE(vid,did,name) \
  32   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
  33 
  34 #define BRIDGE(vid,did,name,bridge) \
  35   {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
  36 
  37 /*
  38  * Sorted in ascending order by vendor and device.
  39  * Use binary search for lookup. If you add a device make sure
  40  * it is sequential by both vendor and device id.
  41  */
  42 struct pci_dev_info dev_info[] = {
  43         DEVICE( NCR,            NCR_53C810,     "53c810"),
  44         DEVICE( NCR,            NCR_53C820,     "53c820"),
  45         DEVICE( NCR,            NCR_53C825,     "53c825"),
  46         DEVICE( NCR,            NCR_53C815,     "53c815"),
  47         DEVICE( ATI,            ATI_68800,      "68800AX"),
  48         DEVICE( ATI,            ATI_215CT222,   "215CT222"),
  49         DEVICE( ATI,            ATI_210888CX,   "210888CX"),
  50         DEVICE( ATI,            ATI_210888GX,   "210888GX"),
  51         DEVICE( VLSI,           VLSI_82C592,    "82C592-FC1"),
  52         DEVICE( VLSI,           VLSI_82C593,    "82C593-FC1"),
  53         DEVICE( ADL,            ADL_2301,       "2301"),
  54         DEVICE( NS,             NS_87410,       "87410"),
  55         DEVICE( TSENG,          TSENG_W32P_2,   "ET4000W32P"),
  56         DEVICE( TSENG,          TSENG_W32P_b,   "ET4000W32P rev B"),
  57         DEVICE( TSENG,          TSENG_W32P_c,   "ET4000W32P rev C"),
  58         DEVICE( TSENG,          TSENG_W32P_d,   "ET4000W32P rev D"),
  59         DEVICE( WEITEK,         WEITEK_P9000,   "P9000"),
  60         DEVICE( WEITEK,         WEITEK_P9100,   "P9100"),
  61         DEVICE( DEC,            DEC_BRD,        "DC21050"),
  62         DEVICE( DEC,            DEC_TULIP,      "DC21040"),
  63         DEVICE( DEC,            DEC_TULIP_FAST, "DC21140"),
  64         DEVICE( DEC,            DEC_FDDI,       "DEFPA"),
  65         DEVICE( DEC,            DEC_TULIP_PLUS, "DC21041"),
  66         DEVICE( CIRRUS,         CIRRUS_5430,    "GD 5430"),
  67         DEVICE( CIRRUS,         CIRRUS_5434_4,  "GD 5434"),
  68         DEVICE( CIRRUS,         CIRRUS_5434_8,  "GD 5434"),
  69         DEVICE( CIRRUS,         CIRRUS_6729,    "CL 6729"),
  70         DEVICE( CIRRUS,         CIRRUS_7542,    "CL 7542"),
  71         DEVICE( AMD,            AMD_LANCE,      "79C970"),
  72         DEVICE( AMD,            AMD_SCSI,       "53C974"),
  73         DEVICE( TRIDENT,        TRIDENT_9420,   "TG 9420"),
  74         DEVICE( TRIDENT,        TRIDENT_9440,   "TG 9440"),
  75         DEVICE( AI,             AI_M1435,       "M1435"),
  76         DEVICE( MATROX,         MATROX_MGA_2,   "Atlas PX2085"),
  77         DEVICE( MATROX,         MATROX_MIL     ,"Millenium"),
  78         DEVICE( MATROX,         MATROX_MGA_IMP, "MGA Impression"),
  79         DEVICE( CT,             CT_65545,       "65545"),
  80         DEVICE( FD,             FD_36C70,       "TMC-18C30"),
  81         DEVICE( SI,             SI_503,         "85C503"),
  82         DEVICE( SI,             SI_501,         "85C501"),
  83         DEVICE( SI,             SI_496,         "85C496"),
  84         DEVICE( SI,             SI_601,         "85C601"),
  85         DEVICE( HP,             HP_J2585A,      "J2585A"),
  86 #if 0
  87         DEVICE( SMC,            SMC_37C665,     "FDC 37C665"),  /* 1042 ? */
  88         DEVICE( SMC,            SMC_37C922,     "FDC 37C922"),
  89 #else
  90         DEVICE( PCTECH,         PCTECH_RZ1000,  "RZ1000 (buggy)"), /* 1042 */
  91 #endif
  92         DEVICE( DPT,            DPT,            "SmartCache/Raid"),
  93         DEVICE( OPTI,           OPTI_82C557,    "82C557"),
  94         DEVICE( OPTI,           OPTI_82C558,    "82C558"),
  95         DEVICE( OPTI,           OPTI_82C621,    "82C621"),
  96         DEVICE( OPTI,           OPTI_82C822,    "82C822"),
  97         DEVICE( BUSLOGIC,       BUSLOGIC_946C_2,"946C"),
  98         DEVICE( BUSLOGIC,       BUSLOGIC_946C,  "946C"),
  99         DEVICE( PROMISE,        PROMISE_5300,   "DC5030"),
 100         DEVICE( N9,             N9_I128,        "Imagine 128"),
 101         DEVICE( UMC,            UMC_UM8673F,    "UM8673F"),
 102         BRIDGE( UMC,            UMC_UM8891A,    "UM8891A",              0x01),
 103         DEVICE( UMC,            UMC_UM8886A,    "UM8886A"),
 104         BRIDGE( UMC,            UMC_UM8881F,    "UM8881F",              0x02),
 105         DEVICE( UMC,            UMC_UM8886F,    "UM8886F"),
 106         DEVICE( X,              X_AGX016,       "ITT AGX016"),
 107         DEVICE( QLOGIC,         QLOGIC_ISP1020, "ISP1020"),
 108         DEVICE( QLOGIC,         QLOGIC_ISP1022, "ISP1022"),
 109         DEVICE( LEADTEK,        LEADTEK_805,    "S3 805"),
 110         DEVICE( CONTAQ,         CONTAQ_82C599,  "82C599"),
 111         DEVICE( CMD,            CMD_640,        "640A"),
 112         DEVICE( VISION,         VISION_QD8500,  "QD-8500"),
 113         DEVICE( VISION,         VISION_QD8580,  "QD-8580"),
 114         DEVICE( WINBOND,        WINBOND_83769,  "W83769F"),
 115         DEVICE( 3COM,           3COM_3C590,     "3C590 10bT"),
 116         DEVICE( 3COM,           3COM_3C595TX,   "3C595 100bTX"),
 117         DEVICE( 3COM,           3COM_3C595T4,   "3C595 100bT4"),
 118         DEVICE( 3COM,           3COM_3C595MII,  "3C595 100b-MII"),
 119         DEVICE( AL,             AL_M1445,       "M1445"),
 120         DEVICE( AL,             AL_M1449,       "M1449"),
 121         DEVICE( AL,             AL_M1451,       "M1451"),
 122         DEVICE( AL,             AL_M1461,       "M1461"),
 123         DEVICE( AL,             AL_M4803,       "M4803"),
 124         DEVICE( IMS,            IMS_8849,       "8849"),
 125         DEVICE( VIA,            VIA_82C505,     "VT 82C505"),
 126         DEVICE( VIA,            VIA_82C561,     "VT 82C561"),
 127         DEVICE( VIA,            VIA_82C576,     "VT 82C576 3V"),
 128         DEVICE( VORTEX,         VORTEX_GDT,     "GDT 6000b"),
 129         DEVICE( EF,             EF_ATM,         "155P-MF1"),
 130         DEVICE( IMAGINGTECH,    IMAGINGTECH_ICPCI, "MVC IC-PCI"),
 131         DEVICE( PLX,            PLX_9060,       "PCI9060 i960 bridge"),
 132         DEVICE( MUTECH,         MUTECH_MV1000,  "MV-1000"),
 133         DEVICE( ZEINET,         ZEINET_1221,    "1221"),
 134         DEVICE( CYCLADES,       CYCLADES_Y,     "Cyclome-Y"),
 135         DEVICE( SYMPHONY,       SYMPHONY_101,   "82C101"),
 136         DEVICE( TEKRAM,         TEKRAM_DC290,   "DC-290"),
 137         DEVICE( S3,             S3_811,         "Trio32/Trio64"),
 138         DEVICE( S3,             S3_868, "Vision 868"),
 139         DEVICE( S3,             S3_928,         "Vision 928-P"),
 140         DEVICE( S3,             S3_864_1,       "Vision 864-P"),
 141         DEVICE( S3,             S3_864_2,       "Vision 864-P"),
 142         DEVICE( S3,             S3_964_1,       "Vision 964-P"),
 143         DEVICE( S3,             S3_964_2,       "Vision 964-P"),
 144         DEVICE( S3,             S3_968,         "Vision 968"),
 145         DEVICE( INTEL,          INTEL_82375,    "82375EB"),
 146         BRIDGE( INTEL,          INTEL_82424,    "82424ZX Saturn",       0x00),
 147         DEVICE( INTEL,          INTEL_82378,    "82378IB"),
 148         DEVICE( INTEL,          INTEL_82430,    "82430ZX Aries"),
 149         BRIDGE( INTEL,          INTEL_82434,    "82434LX Mercury/Neptune", 0x00),
 150         DEVICE( INTEL,          INTEL_7116,     "SAA7116"),
 151         DEVICE( INTEL,          INTEL_82865,    "82865"),
 152         DEVICE( INTEL,          INTEL_82437,    "82437 Triton"),
 153         DEVICE( INTEL,          INTEL_82371,    "82371 Triton"),
 154         DEVICE( INTEL,          INTEL_82438,    "82438"),
 155         DEVICE( INTEL,          INTEL_P6,       "Experimental P6 bridge"),
 156         DEVICE( ADAPTEC,        ADAPTEC_7850,   "AIC-7850"),
 157         DEVICE( ADAPTEC,        ADAPTEC_294x,   "294x"),
 158         DEVICE( ADAPTEC,        ADAPTEC_2940,   "2940"),
 159         DEVICE( ATRONICS,       ATRONICS_2015,  "IDE-2015PL"),
 160         DEVICE( HER,            HER_STING,      "Stingray"),
 161         DEVICE( HER,            HER_STINGARK,   "Stingray ARK 2000PV")
 162 };
 163 
 164 
 165 #ifdef CONFIG_PCI_OPTIMIZE
 166 
 167 /*
 168  * An item of this structure has the following meaning:
 169  * for each optimization, the register address, the mask
 170  * and value to write to turn it on.
 171  * There are 5 optimizations for the moment:
 172  * Cache L2 write back best than write through
 173  * Posted Write for CPU to PCI enable
 174  * Posted Write for CPU to MEMORY enable
 175  * Posted Write for PCI to MEMORY enable
 176  * PCI Burst enable
 177  *
 178  * Half of the bios I've meet don't allow you to turn that on, and you
 179  * can gain more than 15% on graphic accesses using those
 180  * optimizations...
 181  */
 182 struct optimization_type {
 183         const char      *type;
 184         const char      *off;
 185         const char      *on;
 186 } bridge_optimization[] = {
 187         {"Cache L2",                    "write trough", "write back"},
 188         {"CPU-PCI posted write",        "off",          "on"},
 189         {"CPU-Memory posted write",     "off",          "on"},
 190         {"PCI-Memory posted write",     "off",          "on"},
 191         {"PCI burst",                   "off",          "on"}
 192 };
 193 
 194 #define NUM_OPTIMIZATIONS \
 195         (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
 196 
 197 struct bridge_mapping_type {
 198         unsigned char   addr;   /* config space address */
 199         unsigned char   mask;
 200         unsigned char   value;
 201 } bridge_mapping[] = {
 202         /*
 203          * Intel Neptune/Mercury/Saturn:
 204          *      If the internal cache is write back,
 205          *      the L2 cache must be write through!
 206          *      I've to check out how to control that
 207          *      for the moment, we won't touch the cache
 208          */
 209         {0x0    ,0x02   ,0x02   },
 210         {0x53   ,0x02   ,0x02   },
 211         {0x53   ,0x01   ,0x01   },
 212         {0x54   ,0x01   ,0x01   },
 213         {0x54   ,0x02   ,0x02   },
 214 
 215         /*
 216          * UMC 8891A Pentium chipset:
 217          *      Why did you think UMC was cheaper ??
 218          */
 219         {0x50   ,0x10   ,0x00   },
 220         {0x51   ,0x40   ,0x40   },
 221         {0x0    ,0x0    ,0x0    },
 222         {0x0    ,0x0    ,0x0    },
 223         {0x0    ,0x0    ,0x0    },
 224 
 225         /*
 226          * UMC UM8881F
 227          *      This is a dummy entry for my tests.
 228          *      I have this chipset and no docs....
 229          */
 230         {0x0    ,0x1    ,0x1    },
 231         {0x0    ,0x2    ,0x0    },
 232         {0x0    ,0x0    ,0x0    },
 233         {0x0    ,0x0    ,0x0    },
 234         {0x0    ,0x0    ,0x0    }
 235 };
 236 
 237 #endif /* CONFIG_PCI_OPTIMIZE */
 238 
 239 
 240 /*
 241  * device_info[] is sorted so we can use binary search
 242  */
 243 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
     /*  */
 244 {
 245         int min = 0,
 246             max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
 247 
 248         for ( ; ; )
 249         {
 250             int i = (min + max) >> 1;
 251             long order;
 252 
 253             order = dev_info[i].vendor - (long) vendor;
 254             if (!order)
 255                 order = dev_info[i].device - (long) dev;
 256         
 257             if (order < 0)
 258             {
 259                     min = i + 1;
 260                     if ( min > max )
 261                        return 0;
 262                     continue;
 263             }
 264 
 265             if (order > 0)
 266             {
 267                     max = i - 1;
 268                     if ( min > max )
 269                        return 0;
 270                     continue;
 271             }
 272 
 273             return & dev_info[ i ];
 274         }
 275 }
 276 
 277 
 278 const char *pci_strbioserr (int error)
     /*  */
 279 {
 280         switch (error) {
 281               case PCIBIOS_SUCCESSFUL:          return "SUCCESSFUL";
 282               case PCIBIOS_FUNC_NOT_SUPPORTED:  return "FUNC_NOT_SUPPORTED";
 283               case PCIBIOS_BAD_VENDOR_ID:       return "SUCCESSFUL";
 284               case PCIBIOS_DEVICE_NOT_FOUND:    return "DEVICE_NOT_FOUND";
 285               case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
 286               case PCIBIOS_SET_FAILED:          return "SET_FAILED";
 287               case PCIBIOS_BUFFER_TOO_SMALL:    return "BUFFER_TOO_SMALL";
 288               default:                          return "Unknown error status";
 289         }
 290 }
 291 
 292 
 293 const char *pci_strclass (unsigned int class)
     /*  */
 294 {
 295         switch (class >> 8) {
 296               case PCI_CLASS_NOT_DEFINED:               return "Non-VGA device";
 297               case PCI_CLASS_NOT_DEFINED_VGA:           return "VGA compatible device";
 298 
 299               case PCI_CLASS_STORAGE_SCSI:              return "SCSI storage controller";
 300               case PCI_CLASS_STORAGE_IDE:               return "IDE interface";
 301               case PCI_CLASS_STORAGE_FLOPPY:            return "Floppy disk controller";
 302               case PCI_CLASS_STORAGE_IPI:               return "IPI bus controller";
 303               case PCI_CLASS_STORAGE_RAID:              return "RAID bus controller";
 304               case PCI_CLASS_STORAGE_OTHER:             return "Unknown mass storage controller";
 305 
 306               case PCI_CLASS_NETWORK_ETHERNET:          return "Ethernet controller";
 307               case PCI_CLASS_NETWORK_TOKEN_RING:        return "Token ring network controller";
 308               case PCI_CLASS_NETWORK_FDDI:              return "FDDI network controller";
 309               case PCI_CLASS_NETWORK_ATM:               return "ATM network controller";
 310               case PCI_CLASS_NETWORK_OTHER:             return "Network controller";
 311 
 312               case PCI_CLASS_DISPLAY_VGA:               return "VGA compatible controller";
 313               case PCI_CLASS_DISPLAY_XGA:               return "XGA compatible controller";
 314               case PCI_CLASS_DISPLAY_OTHER:             return "Display controller";
 315 
 316               case PCI_CLASS_MULTIMEDIA_VIDEO:          return "Multimedia video controller";
 317               case PCI_CLASS_MULTIMEDIA_AUDIO:          return "Multimedia audio controller";
 318               case PCI_CLASS_MULTIMEDIA_OTHER:          return "Multimedia controller";
 319 
 320               case PCI_CLASS_MEMORY_RAM:                return "RAM memory";
 321               case PCI_CLASS_MEMORY_FLASH:              return "FLASH memory";
 322               case PCI_CLASS_MEMORY_OTHER:              return "Memory";
 323 
 324               case PCI_CLASS_BRIDGE_HOST:               return "Host bridge";
 325               case PCI_CLASS_BRIDGE_ISA:                return "ISA bridge";
 326               case PCI_CLASS_BRIDGE_EISA:               return "EISA bridge";
 327               case PCI_CLASS_BRIDGE_MC:                 return "MicroChannel bridge";
 328               case PCI_CLASS_BRIDGE_PCI:                return "PCI bridge";
 329               case PCI_CLASS_BRIDGE_PCMCIA:             return "PCMCIA bridge";
 330               case PCI_CLASS_BRIDGE_NUBUS:              return "NuBus bridge";
 331               case PCI_CLASS_BRIDGE_CARDBUS:            return "CardBus bridge";
 332               case PCI_CLASS_BRIDGE_OTHER:              return "Bridge";
 333 
 334               case PCI_CLASS_COMMUNICATION_SERIAL:      return "Serial controller";
 335               case PCI_CLASS_COMMUNICATION_PARALLEL:    return "Parallel controller";
 336               case PCI_CLASS_COMMUNICATION_OTHER:       return "Communication controller";
 337 
 338               case PCI_CLASS_SYSTEM_PIC:                return "PIC";
 339               case PCI_CLASS_SYSTEM_DMA:                return "DMA controller";
 340               case PCI_CLASS_SYSTEM_TIMER:              return "Timer";
 341               case PCI_CLASS_SYSTEM_RTC:                return "RTC";
 342               case PCI_CLASS_SYSTEM_OTHER:              return "System peripheral";
 343 
 344               case PCI_CLASS_INPUT_KEYBOARD:            return "Keyboard controller";
 345               case PCI_CLASS_INPUT_PEN:                 return "Digitizer Pen";
 346               case PCI_CLASS_INPUT_MOUSE:               return "Mouse controller";
 347               case PCI_CLASS_INPUT_OTHER:               return "Input device controller";
 348 
 349               case PCI_CLASS_DOCKING_GENERIC:           return "Generic Docking Station";
 350               case PCI_CLASS_DOCKING_OTHER:             return "Docking Station";
 351 
 352               case PCI_CLASS_PROCESSOR_386:             return "386";
 353               case PCI_CLASS_PROCESSOR_486:             return "486";
 354               case PCI_CLASS_PROCESSOR_PENTIUM:         return "Pentium";
 355               case PCI_CLASS_PROCESSOR_ALPHA:           return "Alpha";
 356               case PCI_CLASS_PROCESSOR_POWERPC:         return "Power PC";
 357               case PCI_CLASS_PROCESSOR_CO:              return "Co-processor";
 358 
 359               case PCI_CLASS_SERIAL_FIREWIRE:           return "FireWire (IEEE 1394)";
 360               case PCI_CLASS_SERIAL_ACCESS:             return "ACCESS Bus";
 361               case PCI_CLASS_SERIAL_SSA:                return "SSA";
 362               case PCI_CLASS_SERIAL_FIBER:              return "Fiber Channel";
 363 
 364               default:                                  return "Unknown class";
 365         }
 366 }
 367 
 368 
 369 const char *pci_strvendor(unsigned int vendor)
     /*  */
 370 {
 371         switch (vendor) {
 372               case PCI_VENDOR_ID_NCR:           return "NCR";
 373               case PCI_VENDOR_ID_ADAPTEC:       return "Adaptec";
 374               case PCI_VENDOR_ID_DPT:           return "DPT";
 375               case PCI_VENDOR_ID_S3:            return "S3 Inc.";
 376               case PCI_VENDOR_ID_OPTI:          return "OPTI";
 377               case PCI_VENDOR_ID_UMC:           return "UMC";
 378               case PCI_VENDOR_ID_DEC:           return "DEC";
 379               case PCI_VENDOR_ID_MATROX:        return "Matrox";
 380               case PCI_VENDOR_ID_INTEL:         return "Intel";
 381 #if 0
 382               case PCI_VENDOR_ID_SMC:           return "SMC";
 383 #else
 384               case PCI_VENDOR_ID_PCTECH:        return "PCTECH";
 385 #endif
 386               case PCI_VENDOR_ID_ATI:           return "ATI";
 387               case PCI_VENDOR_ID_WEITEK:        return "Weitek";
 388               case PCI_VENDOR_ID_CIRRUS:        return "Cirrus Logic";
 389               case PCI_VENDOR_ID_BUSLOGIC:      return "Bus Logic";
 390               case PCI_VENDOR_ID_N9:            return "Number Nine";
 391               case PCI_VENDOR_ID_AI:            return "Acer Incorporated";
 392               case PCI_VENDOR_ID_AL:            return "Acer Labs";
 393               case PCI_VENDOR_ID_TSENG:         return "Tseng'Lab";
 394               case PCI_VENDOR_ID_CMD:           return "CMD";
 395               case PCI_VENDOR_ID_VISION:        return "Vision";
 396               case PCI_VENDOR_ID_AMD:           return "AMD";
 397               case PCI_VENDOR_ID_VLSI:          return "VLSI";
 398               case PCI_VENDOR_ID_ADL:           return "Advance Logic";
 399               case PCI_VENDOR_ID_SYMPHONY:      return "Symphony";
 400               case PCI_VENDOR_ID_TRIDENT:       return "Trident";
 401               case PCI_VENDOR_ID_CONTAQ:        return "Contaq";
 402               case PCI_VENDOR_ID_NS:            return "NS";
 403               case PCI_VENDOR_ID_VIA:           return "VIA Technologies";
 404               case PCI_VENDOR_ID_SI:            return "Silicon Integrated Systems";
 405               case PCI_VENDOR_ID_LEADTEK:       return "Leadtek Research";
 406               case PCI_VENDOR_ID_IMS:           return "IMS";
 407               case PCI_VENDOR_ID_ZEINET:        return "ZeiNet";
 408               case PCI_VENDOR_ID_EF:            return "Efficient Networks";
 409               case PCI_VENDOR_ID_HER:           return "Hercules";
 410               case PCI_VENDOR_ID_ATRONICS:      return "Atronics";
 411               case PCI_VENDOR_ID_CT:            return "Chips & Technologies";
 412               case PCI_VENDOR_ID_FD:            return "Future Domain";
 413               case PCI_VENDOR_ID_WINBOND:       return "Winbond";
 414               case PCI_VENDOR_ID_3COM:          return "3Com";
 415               case PCI_VENDOR_ID_PROMISE:       return "Promise Technology";
 416               case PCI_VENDOR_ID_QLOGIC:        return "Q Logic";
 417               case PCI_VENDOR_ID_X:             return "X TECHNOLOGY";
 418               case PCI_VENDOR_ID_ACC:           return "ACC MICROELECTRONICS";
 419               case PCI_VENDOR_ID_VORTEX:        return "VORTEX";
 420               case PCI_VENDOR_ID_HP:            return "Hewlett Packard";
 421               case PCI_VENDOR_ID_IMAGINGTECH:   return "Imaging Technology";
 422               case PCI_VENDOR_ID_CYCLADES:      return "Cyclades";
 423               case PCI_VENDOR_ID_OLICOM:        return "Olicom";
 424               default:                          return "Unknown vendor";
 425         }
 426 }
 427 
 428 
 429 const char *pci_strdev(unsigned int vendor, unsigned int device)
     /*  */
 430 {
 431         struct pci_dev_info *info;
 432 
 433         info =  pci_lookup_dev(vendor, device);
 434         return info ? info->name : "Unknown device";
 435 }
 436 
 437 
 438 
 439 /*
 440  * Turn on/off PCI bridge optimization. This should allow benchmarking.
 441  */
 442 static void burst_bridge(unsigned char bus, unsigned char devfn,
     /*  */
 443                          unsigned char pos, int turn_on)
 444 {
 445 #ifdef CONFIG_PCI_OPTIMIZE
 446         struct bridge_mapping_type *bmap;
 447         unsigned char val;
 448         int i;
 449 
 450         pos *= NUM_OPTIMIZATIONS;
 451         printk("PCI bridge optimization.\n");
 452         for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
 453                 printk("    %s: ", bridge_optimization[i].type);
 454                 bmap = &bridge_mapping[pos + i];
 455                 if (!bmap->addr) {
 456                         printk("Not supported.");
 457                 } else {
 458                         pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
 459                         if ((val & bmap->mask) == bmap->value) {
 460                                 printk("%s.", bridge_optimization[i].on);
 461                                 if (!turn_on) {
 462                                         pcibios_write_config_byte(bus, devfn,
 463                                                                   bmap->addr,
 464                                                                   (val | bmap->mask)
 465                                                                   - bmap->value);
 466                                         printk("Changed!  Now %s.", bridge_optimization[i].off);
 467                                 }
 468                         } else {
 469                                 printk("%s.", bridge_optimization[i].off);
 470                                 if (turn_on) {
 471                                         pcibios_write_config_byte(bus, devfn,
 472                                                                   bmap->addr,
 473                                                                   (val & (0xff - bmap->mask))
 474                                                                   + bmap->value);
 475                                         printk("Changed!  Now %s.", bridge_optimization[i].on);
 476                                 }
 477                         }
 478                 }
 479                 printk("\n");
 480         }
 481 #endif /* CONFIG_PCI_OPTIMIZE */
 482 }
 483 
 484 
 485 /*
 486  * Convert some of the configuration space registers of the device at
 487  * address (bus,devfn) into a string (possibly several lines each).
 488  * The configuration string is stored starting at buf[len].  If the
 489  * string would exceed the size of the buffer (SIZE), 0 is returned.
 490  */
 491 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
     /*  */
 492 {
 493         unsigned long base;
 494         unsigned int l, class_rev, bus, devfn;
 495         unsigned short vendor, device, status;
 496         unsigned char bist, latency, min_gnt, max_lat;
 497         int reg, len = 0;
 498         const char *str;
 499 
 500         bus   = dev->bus->number;
 501         devfn = dev->devfn;
 502 
 503         pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
 504         pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
 505         pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
 506         pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
 507         pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
 508         pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
 509         pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
 510         pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
 511         if (len + 80 > size) {
 512                 return -1;
 513         }
 514         len += sprintf(buf + len, "  Bus %2d, device %3d, function %2d:\n",
 515                        bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
 516 
 517         if (len + 80 > size) {
 518                 return -1;
 519         }
 520         len += sprintf(buf + len, "    %s: %s %s (rev %d).\n      ",
 521                        pci_strclass(class_rev >> 8), pci_strvendor(vendor),
 522                        pci_strdev(vendor, device), class_rev & 0xff);
 523 
 524         if (!pci_lookup_dev(vendor, device)) {
 525                 len += sprintf(buf + len,
 526                                "Vendor id=%x. Device id=%x.\n      ",
 527                                vendor, device);
 528         }
 529 
 530         str = 0;        /* to keep gcc shut... */
 531         switch (status & PCI_STATUS_DEVSEL_MASK) {
 532               case PCI_STATUS_DEVSEL_FAST:   str = "Fast devsel.  "; break;
 533               case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel.  "; break;
 534               case PCI_STATUS_DEVSEL_SLOW:   str = "Slow devsel.  "; break;
 535         }
 536         if (len + strlen(str) > size) {
 537                 return -1;
 538         }
 539         len += sprintf(buf + len, str);
 540 
 541         if (status & PCI_STATUS_FAST_BACK) {
 542 #               define fast_b2b_capable "Fast back-to-back capable.  "
 543                 if (len + strlen(fast_b2b_capable) > size) {
 544                         return -1;
 545                 }
 546                 len += sprintf(buf + len, fast_b2b_capable);
 547 #               undef fast_b2b_capable
 548         }
 549 
 550         if (bist & PCI_BIST_CAPABLE) {
 551 #               define BIST_capable     "BIST capable.  "
 552                 if (len + strlen(BIST_capable) > size) {
 553                         return -1;
 554                 }
 555                 len += sprintf(buf + len, BIST_capable);
 556 #               undef BIST_capable
 557         }
 558 
 559         if (dev->irq) {
 560                 if (len + 40 > size) {
 561                         return -1;
 562                 }
 563                 len += sprintf(buf + len, "IRQ %d.  ", dev->irq);
 564         }
 565 
 566         if (dev->master) {
 567                 if (len + 80 > size) {
 568                         return -1;
 569                 }
 570                 len += sprintf(buf + len, "Master Capable.  ");
 571                 if (latency)
 572                   len += sprintf(buf + len, "Latency=%d.  ", latency);
 573                 else
 574                   len += sprintf(buf + len, "No bursts.  ");
 575                 if (min_gnt)
 576                   len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
 577                 if (max_lat)
 578                   len += sprintf(buf + len, "Max Lat=%d.", max_lat);
 579         }
 580 
 581         for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
 582                 if (len + 40 > size) {
 583                         return -1;
 584                 }
 585                 pcibios_read_config_dword(bus, devfn, reg, &l);
 586                 base = l;
 587                 if (!base) {
 588                         continue;
 589                 }
 590 
 591                 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
 592                         len += sprintf(buf + len,
 593                                        "\n      I/O at 0x%lx.",
 594                                        base & PCI_BASE_ADDRESS_IO_MASK);
 595                 } else {
 596                         const char *pref, *type = "unknown";
 597 
 598                         if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
 599                                 pref = "P";
 600                         } else {
 601                                 pref = "Non-p";
 602                         }
 603                         switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
 604                               case PCI_BASE_ADDRESS_MEM_TYPE_32:
 605                                 type = "32 bit"; break;
 606                               case PCI_BASE_ADDRESS_MEM_TYPE_1M:
 607                                 type = "20 bit"; break;
 608                               case PCI_BASE_ADDRESS_MEM_TYPE_64:
 609                                 type = "64 bit";
 610                                 /* read top 32 bit address of base addr: */
 611                                 reg += 4;
 612                                 pcibios_read_config_dword(bus, devfn, reg, &l);
 613                                 base |= ((u64) l) << 32;
 614                                 break;
 615                         }
 616                         len += sprintf(buf + len,
 617                                        "\n      %srefetchable %s memory at "
 618                                        "0x%lx.", pref, type,
 619                                        base & PCI_BASE_ADDRESS_MEM_MASK);
 620                 }
 621         }
 622 
 623         len += sprintf(buf + len, "\n");
 624         return len;
 625 }
 626 
 627 
 628 /*
 629  * Return list of PCI devices as a character string for /proc/pci.
 630  * BUF is a buffer that is PAGE_SIZE bytes long.
 631  */
 632 int get_pci_list(char *buf)
     /*  */
 633 {
 634         int nprinted, len, size;
 635         struct pci_dev *dev;
 636 #       define MSG "\nwarning: page-size limit reached!\n"
 637 
 638         /* reserve same for truncation warning message: */
 639         size  = PAGE_SIZE - (strlen(MSG) + 1);
 640         len   = sprintf(buf, "PCI devices found:\n");
 641 
 642         for (dev = pci_devices; dev; dev = dev->next) {
 643                 nprinted = sprint_dev_config(dev, buf + len, size - len);
 644                 if (nprinted < 0) {
 645                         return len + sprintf(buf + len, MSG);
 646                 }
 647                 len += nprinted;
 648         }
 649         return len;
 650 }
 651 
 652 
 653 /*
 654  * pci_malloc() returns initialized memory of size SIZE.  Can be
 655  * used only while pci_init() is active.
 656  */
 657 static void *pci_malloc(long size, unsigned long *mem_startp)
     /*  */
 658 {
 659         void *mem;
 660 
 661 #ifdef DEBUG
 662         printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
 663 #endif
 664         mem = (void*) *mem_startp;
 665         *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
 666         memset(mem, 0, size);
 667         return mem;
 668 }
 669 
 670 
 671 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
     /*  */
 672 {
 673         unsigned int devfn, l, max;
 674         unsigned char cmd, tmp, hdr_type = 0;
 675         struct pci_dev_info *info;
 676         struct pci_dev *dev;
 677         struct pci_bus *child;
 678 
 679 #ifdef DEBUG
 680         printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
 681 #endif
 682 
 683         max = bus->secondary;
 684         for (devfn = 0; devfn < 0xff; ++devfn) {
 685                 if (PCI_FUNC(devfn) == 0) {
 686                         pcibios_read_config_byte(bus->number, devfn,
 687                                                  PCI_HEADER_TYPE, &hdr_type);
 688                 } else if (!(hdr_type & 0x80)) {
 689                         /* not a multi-function device */
 690                         continue;
 691                 }
 692 
 693                 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
 694                                           &l);
 695                 /* some broken boards return 0 if a slot is empty: */
 696                 if (l == 0xffffffff || l == 0x00000000) {
 697                         hdr_type = 0;
 698                         continue;
 699                 }
 700 
 701                 dev = pci_malloc(sizeof(*dev), mem_startp);
 702                 dev->bus = bus;
 703                 /*
 704                  * Put it into the simple chain of devices on this
 705                  * bus.  It is used to find devices once everything is
 706                  * set up.
 707                  */
 708                 dev->next = pci_devices;
 709                 pci_devices = dev;
 710 
 711                 dev->devfn  = devfn;
 712                 dev->vendor = l & 0xffff;
 713                 dev->device = (l >> 16) & 0xffff;
 714 
 715                 /*
 716                  * Check to see if we now about this device and report
 717                  * a message at boot time.  This is the only way to
 718                  * learn about new hardware...
 719                  */
 720                 info = pci_lookup_dev(dev->vendor, dev->device);
 721                 if (!info) {
 722                         printk("Warning : Unknown PCI device (%x:%x).  Please read include/linux/pci.h \n",
 723                                 dev->vendor, dev->device);
 724                 } else {
 725                         /* Some BIOS' are lazy. Let's do their job: */
 726                         if (info->bridge_type != 0xff) {
 727                                 burst_bridge(bus->number, devfn,
 728                                              info->bridge_type, 1);
 729                         }
 730                 }
 731 
 732                 /* non-destructively determine if device can be a master: */
 733                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 734                                          &cmd);
 735                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 736                                           cmd | PCI_COMMAND_MASTER);
 737                 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
 738                                          &tmp);
 739                 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
 740                 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
 741                                           cmd);
 742 
 743                 /* read irq level (may be changed during pcibios_fixup()): */
 744                 pcibios_read_config_byte(bus->number, devfn,
 745                                          PCI_INTERRUPT_LINE, &dev->irq);
 746 
 747                 /* check to see if this device is a PCI-PCI bridge: */
 748                 pcibios_read_config_dword(bus->number, devfn,
 749                                           PCI_CLASS_REVISION, &l);
 750                 l = l >> 8;                     /* upper 3 bytes */
 751                 dev->class = l;
 752                 /*
 753                  * Now insert it into the list of devices held
 754                  * by the parent bus.
 755                  */
 756                 dev->sibling = bus->devices;
 757                 bus->devices = dev;
 758 
 759                 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
 760                         unsigned int buses;
 761                         unsigned short cr;
 762 
 763                         /*
 764                          * Insert it into the tree of buses.
 765                          */
 766                         child = pci_malloc(sizeof(*child), mem_startp);
 767                         child->next   = bus->children;
 768                         bus->children = child;
 769                         child->self = dev;
 770                         child->parent = bus;
 771 
 772                         /*
 773                          * Set up the primary, secondary and subordinate
 774                          * bus numbers.
 775                          */
 776                         child->number = child->secondary = ++max;
 777                         child->primary = bus->secondary;
 778                         child->subordinate = 0xff;
 779                         /*
 780                          * Clear all status bits and turn off memory,
 781                          * I/O and master enables.
 782                          */
 783                         pcibios_read_config_word(bus->number, devfn,
 784                                                   PCI_COMMAND, &cr);
 785                         pcibios_write_config_word(bus->number, devfn,
 786                                                   PCI_COMMAND, 0x0000);
 787                         pcibios_write_config_word(bus->number, devfn,
 788                                                   PCI_STATUS, 0xffff);
 789                         /*
 790                          * Configure the bus numbers for this bridge:
 791                          */
 792                         pcibios_read_config_dword(bus->number, devfn, 0x18,
 793                                                   &buses);
 794                         buses &= 0xff000000;
 795                         buses |= (((unsigned int)(child->primary)     <<  0) |
 796                                   ((unsigned int)(child->secondary)   <<  8) |
 797                                   ((unsigned int)(child->subordinate) << 16));
 798                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 799                                                    buses);
 800                         /*
 801                          * Now we can scan all subordinate buses:
 802                          */
 803                         max = scan_bus(child, mem_startp);
 804                         /*
 805                          * Set the subordinate bus number to its real
 806                          * value:
 807                          */
 808                         child->subordinate = max;
 809                         buses = (buses & 0xff00ffff)
 810                           | ((unsigned int)(child->subordinate) << 16);
 811                         pcibios_write_config_dword(bus->number, devfn, 0x18,
 812                                                    buses);
 813                         pcibios_write_config_word(bus->number, devfn,
 814                                                   PCI_COMMAND, cr);
 815                 }
 816         }
 817         /*
 818          * We've scanned the bus and so we know all about what's on
 819          * the other side of any bridges that may be on this bus plus
 820          * any devices.
 821          *
 822          * Return how far we've got finding sub-buses.
 823          */
 824         return max;
 825 }
 826 
 827 
 828 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
     /*  */
 829 {
 830         mem_start = pcibios_init(mem_start, mem_end);
 831 
 832         if (!pcibios_present()) {
 833                 printk("pci_init: no BIOS32 detected\n");
 834                 return mem_start;
 835         }
 836 
 837         printk("Probing PCI hardware.\n");
 838 
 839         memset(&pci_root, 0, sizeof(pci_root));
 840         pci_root.subordinate = scan_bus(&pci_root, &mem_start);
 841 
 842         /* give BIOS a chance to apply platform specific fixes: */
 843         mem_start = pcibios_fixup(mem_start, mem_end);
 844 
 845 #ifdef DEBUG
 846         {
 847                 int len = get_pci_list((char*)mem_start);
 848                 if (len) {
 849                         ((char *) mem_start)[len] = '\0';
 850                         printk("%s\n", (char *) mem_start);
 851                 }
 852         }
 853 #endif
 854         return mem_start;
 855 }
/* */
root/drivers/pci/pci.c

DEFINITIONS
