drivers/net/pi2.h

/* */
   1 
   2 #define DMA_BUFF_SIZE 2200
   3 
   4 /* Network statistics, with the same names as 'struct enet_statistics'. */
   5 #define netstats enet_statistics
   6 
   7 #define ON 1
   8 #define OFF 0
   9 
  10 
  11 /* Register offset info, specific to the PI
  12  * E.g., to read the data port on channel A, use
  13  *  inportb(pichan[dev].base + CHANA + DATA)
  14  */
  15 #define CHANB   0   /* Base of channel B regs */
  16 #define CHANA   2   /* Base of channel A regs */
  17 
  18 /* 8530 ports on each channel */
  19 #define CTL 0
  20 #define DATA    1
  21 
  22 #define DMAEN   0x4 /* Offset off DMA Enable register */
  23 
  24 /* Timer chip offsets */
  25 #define TMR0    0x8 /* Offset of timer 0 register */
  26 #define TMR1    0x9 /* Offset of timer 1 register */
  27 #define TMR2    0xA /* Offset of timer 2 register */
  28 #define TMRCMD  0xB /* Offset of timer command register */
  29 
  30 /* Timer chip equates */
  31 #define SC0 0x00 /* Select counter 0 */
  32 #define SC1 0x40 /* Select counter 1 */
  33 #define SC2 0x80 /* Select counter 2 */
  34 #define CLATCH  0x00 /* Counter latching operation */
  35 #define MSB 0x20 /* Read/load MSB only */
  36 #define LSB 0x10 /* Read/load LSB only */
  37 #define LSB_MSB 0x30 /* Read/load LSB, then MSB */
  38 #define MODE0   0x00 /* Interrupt on terminal count */
  39 #define MODE1   0x02 /* Programmable one shot */
  40 #define MODE2   0x04 /* Rate generator */
  41 #define MODE3   0x06 /* Square wave rate generator */
  42 #define MODE4   0x08 /* Software triggered strobe */
  43 #define MODE5   0x0a /* Hardware triggered strobe */
  44 #define BCD 0x01 /* BCD counter */
  45 
  46 /* DMA controller registers */
  47 #define DMA_STAT    8   /* DMA controller status register */
  48 #define DMA_CMD     8   /* DMA controller command register */
  49 #define DMA_MASK        10  /* DMA controller mask register */
  50 #define DMA_MODE        11  /* DMA controller mode register */
  51 #define DMA_RESETFF 12  /* DMA controller first/last flip flop  */
  52 /* DMA data */
  53 #define DMA_DISABLE (0x04)  /* Disable channel n */
  54 #define DMA_ENABLE  (0x00)  /* Enable channel n */
  55 /* Single transfers, incr. address, auto init, writes, ch. n */
  56 #define DMA_RX_MODE (0x54)
  57 /* Single transfers, incr. address, no auto init, reads, ch. n */
  58 #define DMA_TX_MODE (0x48)
  59 
  60 #define SINGLE 3686400
  61 #define DOUBLE 7372800
  62 
  63 #define SIOCGPIPARAM            0x5000  /* get PI parameters */
  64 #define SIOCSPIPARAM            0x5001  /* set */
  65 #define SIOCGPIBAUD             0x5002  /* get only baud rate */
  66 #define SIOCSPIBAUD             0x5003  
  67 #define SIOCGPIDMA              0x5004  /* get only DMA */
  68 #define SIOCSPIDMA              0x5005  
  69 #define SIOCGPIIRQ              0x5006  /* get only IRQ */
  70 #define SIOCSPIIRQ              0x5007  
  71 
  72 struct pi_req  {
  73     int cmd;
  74     int speed;
  75     int clockmode;
  76     int txdelay;
  77     unsigned char persist;
  78     int slotime; 
  79     int squeldelay;
  80     int dmachan;    
  81     int irq;    
  82 };
  83 
  84 #ifdef __KERNEL__
  85 
  86 /* Information that needs to be kept for each channel. */
  87 struct pi_local {
  88     struct netstats stats; /* %%%dp*/
  89     long open_time;             /* Useless example local info. */
  90     unsigned long xtal; 
  91 
  92     struct mbuf *rcvbuf;/* Buffer for current rx packet */
  93     struct mbuf *rxdmabuf1; /* DMA rx buffer */
  94     struct mbuf *rxdmabuf2; /* DMA rx buffer */
  95 
  96     int bufsiz;         /* Size of rcvbuf */
  97     char *rcp;          /* Pointer into rcvbuf */
  98 
  99     struct sk_buff_head sndq;  /* Packets awaiting transmission */
 100     int sndcnt;         /* Number of packets on sndq */
 101     struct sk_buff *sndbuf;     /* Current buffer being transmitted */
 102     char *txdmabuf;     /* Transmit DMA buffer */
 103         char *txptr;            /* Used by B port tx */
 104         int txcnt;                      
 105     char tstate;        /* Transmitter state */
 106 #define IDLE    0       /* Transmitter off, no data pending */
 107 #define ACTIVE  1       /* Transmitter on, sending data */
 108 #define UNDERRUN 2      /* Transmitter on, flushing CRC */
 109 #define FLAGOUT 3       /* CRC sent - attempt to start next frame */
 110 #define DEFER 4         /* Receive Active - DEFER Transmit */
 111 #define ST_TXDELAY 5    /* Sending leading flags */
 112 #define CRCOUT 6
 113     char rstate;        /* Set when !DCD goes to 0 (TRUE) */
 114 /* Normal state is ACTIVE if Receive enabled */
 115 #define RXERROR 2       /* Error -- Aborting current Frame */
 116 #define RXABORT 3       /* ABORT sequence detected */
 117 #define TOOBIG 4        /* too large a frame to store */
 118     int dev;            /* Device number */
 119     int base;       /* Base of I/O registers */
 120     int cardbase;     /* Base address of card */
 121     int stata;        /* address of Channel A status regs */
 122     int statb;        /* address of Channel B status regs */
 123     int speed;        /* Line speed, bps */
 124     int clockmode;    /* tapr 9600 modem clocking option */
 125     int txdelay;      /* Transmit Delay 10 ms/cnt */
 126     unsigned char persist;       /* Persistence (0-255) as a % */
 127     int slotime;      /* Delay to wait on persistence hit */
 128     int squeldelay;   /* Delay after XMTR OFF for squelch tail */
 129     struct iface *iface;    /* Associated interface */
 130     int dmachan;           /* DMA channel for this port */
 131 };
 132 
 133 #endif
/* */
root/drivers/net/pi2.h

INCLUDED FROM
