taglinefilesource code
cardbase258drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
cardbase274drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
cardbase277drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1,
cardbase320drivers/net/pi2.cport = lp->cardbase + TMR1;
cardbase324drivers/net/pi2.cport = lp->cardbase + TMR2;
cardbase325drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
cardbase329drivers/net/pi2.coutb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
cardbase336drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
cardbase337drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
cardbase369drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase370drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase371drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase375drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase386drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
cardbase409drivers/net/pi2.cst = rdscc(lp->cardbase, lp->base + CTL, R0);  /* Fetch status */
cardbase412drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
cardbase440drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
cardbase457drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
cardbase460drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);
cardbase463drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
cardbase466drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
cardbase476drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase477drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase478drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase482drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
cardbase493drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
cardbase521drivers/net/pi2.crse = rdscc(lp->cardbase, cmd, R1);  /* Get special condition bits from R1 */
cardbase578drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
cardbase596drivers/net/pi2.crse = rdscc(lp->cardbase, cmd, R1);  /* get status byte from R1 */
cardbase598drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
cardbase620drivers/net/pi2.c*lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
cardbase624drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase625drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, ERR_RES);  /* reset err latch */
cardbase709drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase710drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase711drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase715drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase736drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase742drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
cardbase747drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
cardbase756drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
cardbase758drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS);
cardbase760drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_P);  /* reset Tx Int Pend */
cardbase785drivers/net/pi2.cst = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
cardbase787drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase794drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
cardbase822drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);  /* reset for next frame */
cardbase826drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
cardbase828drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
cardbase831drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);  /* First char out now */
cardbase832drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);  /* Reset end of message latch */
cardbase840drivers/net/pi2.cwhile((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
cardbase842drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase848drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
cardbase849drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase850drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);  /* Tx/Ext ints */
cardbase860drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase861drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase862drivers/net/pi2.cif ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
cardbase866drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
cardbase887drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);  /* reset for next frame */
cardbase891drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
cardbase893drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
cardbase896drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);  /* First char out now */
cardbase897drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EOM_L);  /* Reset end of message latch */
cardbase905drivers/net/pi2.cwhile((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
cardbase907drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R8, c);
cardbase913drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
cardbase914drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
cardbase916drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
cardbase929drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase930drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase931drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1012drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, 0);
cardbase1013drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* Rx off */
cardbase1017drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
cardbase1019drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, 0);  /* No interrupts */
cardbase1026drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1027drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1030drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
cardbase1034drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);  /*  TX off */
cardbase1040drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC);
cardbase1044drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1045drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1047drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
cardbase1049drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
cardbase1053drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* Make sure rx is off */
cardbase1054drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R0, ERR_RES);  /* reset err latch */
cardbase1055drivers/net/pi2.cdummy = rdscc(lp->cardbase, cmd, R1);  /* get status byte from R1 */
cardbase1056drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1057drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1059drivers/net/pi2.c(void) rdscc(lp->cardbase, cmd, R8);
cardbase1062drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
cardbase1071drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
cardbase1073drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
cardbase1108drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R9, CHRA);  /* Reset channel A */
cardbase1109drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R2, 0xff);  /* Initialize interrupt vector */
cardbase1112drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R9, CHRB);  /* Reset channel B */
cardbase1117drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, 0);
cardbase1120drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, 0);
cardbase1123drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
cardbase1127drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
cardbase1130drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
cardbase1133drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
cardbase1135drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R10, CRCPS);
cardbase1137drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R11, TCTRxCP);
cardbase1141drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R6, 0);
cardbase1144drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R7, FLAG);
cardbase1149drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
cardbase1152drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, Rx8);  /* 8 bits/char */
cardbase1155drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC);  /* BRG off, keep Pclk source */
cardbase1166drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
cardbase1167drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);  /* upper byte */
cardbase1174drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
cardbase1177drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
cardbase1179drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);  /* SEARCH mode, keep BRG src */
cardbase1180drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);  /* Enable the BRG */
cardbase1183drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
cardbase1185drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R15, BRKIE);  /* ABORT int */
cardbase1188drivers/net/pi2.cwrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
cardbase1195drivers/net/pi2.cint cardbase;
cardbase1198drivers/net/pi2.ccardbase = dev->base_addr & 0x3f0;
cardbase1202drivers/net/pi2.cwrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES);  /* Hardware reset */
cardbase1204drivers/net/pi2.cwrtscc(cardbase, dev->base_addr + CTL, R9, 0);
cardbase1343drivers/net/pi2.clp->cardbase = dev->base_addr & 0x3f0;
cardbase1380drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
cardbase1382drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
cardbase1393drivers/net/pi2.cwrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);  /* Hardware reset */
cardbase1395drivers/net/pi2.cwrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
cardbase1486drivers/net/pi2.cwrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
cardbase1536drivers/net/pi2.cwhile ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
cardbase1565drivers/net/pi2.cwrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
cardbase120drivers/net/pi2.hint cardbase;     /* Base address of card */