include/asm-i386/smp.h

/* */
This source file includes following definitions.
apic_write
apic_read
smp_processor_id
   1 #ifndef __ASM_SMP_H
   2 #define __ASM_SMP_H
   3 
   4 #ifndef ASSEMBLY
   5 
   6 #include <asm/i82489.h>
   7 #include <linux/tasks.h>
   8 #include <linux/ptrace.h>
   9 
  10 /*
  11  *      Support definitions for SMP machines following the intel multiprocessing
  12  *      specification
  13  */
  14 
  15 /*
  16  *      This tag identifies where the SMP configuration
  17  *      information is. 
  18  */
  19  
  20 #define SMP_MAGIC_IDENT ('_'<<24)|('P'<<16)|('M'<<8)|'_'
  21 
  22 struct intel_mp_floating
  23 {
  24         char mpf_signature[4];          /* "_MP_"                       */
  25         unsigned long mpf_physptr;      /* Configuration table address  */
  26         unsigned char mpf_length;       /* Our length (paragraphs)      */
  27         unsigned char mpf_specification;/* Specification version        */
  28         unsigned char mpf_checksum;     /* Checksum (makes sum 0)       */
  29         unsigned char mpf_feature1;     /* Standard or configuration ?  */
  30         unsigned char mpf_feature2;     /* Bit7 set for IMCR|PIC        */
  31         unsigned char mpf_feature3;     /* Unused (0)                   */
  32         unsigned char mpf_feature4;     /* Unused (0)                   */
  33         unsigned char mpf_feature5;     /* Unused (0)                   */
  34 };
  35 
  36 struct mp_config_table
  37 {
  38         char mpc_signature[4];
  39 #define MPC_SIGNATURE "PCMP"
  40         unsigned short mpc_length;      /* Size of table */
  41         char  mpc_spec;                 /* 0x01 */
  42         char  mpc_checksum;
  43         char  mpc_oem[8];
  44         char  mpc_productid[12];
  45         unsigned long mpc_oemptr;       /* 0 if not present */
  46         unsigned short mpc_oemsize;     /* 0 if not present */
  47         unsigned short mpc_oemcount;
  48         unsigned long mpc_lapic;        /* APIC address */
  49         unsigned long reserved;
  50 };
  51 
  52 /* Followed by entries */
  53 
  54 #define MP_PROCESSOR    0
  55 #define MP_BUS          1
  56 #define MP_IOAPIC       2
  57 #define MP_INTSRC       3
  58 #define MP_LINTSRC      4
  59 
  60 struct mpc_config_processor
  61 {
  62         unsigned char mpc_type;
  63         unsigned char mpc_apicid;       /* Local APIC number */
  64         unsigned char mpc_apicver;      /* Its versions */
  65         unsigned char mpc_cpuflag;
  66 #define CPU_ENABLED             1       /* Processor is available */
  67 #define CPU_BOOTPROCESSOR       2       /* Processor is the BP */
  68         unsigned long mpc_cpufeature;           
  69 #define CPU_STEPPING_MASK 0x0F
  70 #define CPU_MODEL_MASK  0xF0
  71 #define CPU_FAMILY_MASK 0xF00
  72         unsigned long mpc_featureflag;  /* CPUID feature value */
  73         unsigned long mpc_reserved[2];
  74 };
  75 
  76 struct mpc_config_bus
  77 {
  78         unsigned char mpc_type;
  79         unsigned char mpc_busid;
  80         unsigned char mpc_bustype[6] __attribute((packed));
  81 };
  82 
  83 #define BUSTYPE_EISA    "EISA"
  84 #define BUSTYPE_ISA     "ISA"
  85 #define BUSTYPE_INTERN  "INTERN"        /* Internal BUS */
  86 #define BUSTYPE_MCA     "MCA"
  87 #define BUSTYPE_VL      "VL"            /* Local bus */
  88 #define BUSTYPE_PCI     "PCI"
  89 #define BUSTYPE_PCMCIA  "PCMCIA"
  90 
  91 /* We don't understand the others */
  92 
  93 struct mpc_config_ioapic
  94 {
  95         unsigned char mpc_type;
  96         unsigned char mpc_apicid;
  97         unsigned char mpc_apicver;
  98         unsigned char mpc_flags;
  99 #define MPC_APIC_USABLE         0x01
 100         unsigned long mpc_apicaddr;
 101 };
 102 
 103 struct mpc_config_intsrc
 104 {
 105         unsigned char mpc_type;
 106         unsigned char mpc_irqtype;
 107         unsigned short mpc_irqflag;
 108         unsigned char mpc_srcbus;
 109         unsigned char mpc_srcbusirq;
 110         unsigned char mpc_dstapic;
 111         unsigned char mpc_dstirq;
 112 };
 113 
 114 #define MP_INT_VECTORED         0
 115 #define MP_INT_NMI              1
 116 #define MP_INT_SMI              2
 117 #define MP_INT_EXTINT           3
 118 
 119 #define MP_IRQDIR_DEFAULT       0
 120 #define MP_IRQDIR_HIGH          1
 121 #define MP_IRQDIR_LOW           3
 122 
 123 
 124 struct mpc_config_intlocal
 125 {
 126         unsigned char mpc_type;
 127         unsigned char mpc_irqtype;
 128         unsigned short mpc_irqflag;
 129         unsigned char mpc_srcbusid;
 130         unsigned char mpc_srcbusirq;
 131         unsigned char mpc_destapic;     
 132 #define MP_APIC_ALL     0xFF
 133         unsigned char mpc_destapiclint;
 134 };
 135 
 136 
 137 /*
 138  *      Default configurations
 139  *
 140  *      1       2 CPU ISA 82489DX
 141  *      2       2 CPU EISA 82489DX no IRQ 8 or timer chaining
 142  *      3       2 CPU EISA 82489DX
 143  *      4       2 CPU MCA 82489DX
 144  *      5       2 CPU ISA+PCI
 145  *      6       2 CPU EISA+PCI
 146  *      7       2 CPU MCA+PCI
 147  */
 148 
 149 /*
 150  *      Per process x86 parameters
 151  */
 152  
 153 struct cpuinfo_x86
 154 {
 155         char hard_math;
 156         char x86;
 157         char x86_model;
 158         char x86_mask;
 159         char x86_vendor_id[16];
 160         int  x86_capability;
 161         int  fdiv_bug;
 162         char wp_works_ok;
 163         char hlt_works_ok;
 164         unsigned long udelay_val;
 165 };
 166 
 167 
 168 extern struct cpuinfo_x86 cpu_data[NR_PROCS];
 169 
 170 /*
 171  *      Private routines/data
 172  */
 173  
 174 extern void smp_scan_config(unsigned long, unsigned long);
 175 extern unsigned long smp_alloc_memory(unsigned long mem_base);
 176 extern unsigned char *apic_reg;
 177 extern unsigned char *kernel_stacks[NR_PROCS];
 178 extern unsigned char boot_cpu_id;
 179 extern unsigned long cpu_present_map;
 180 extern void smp_invalidate(void);
 181 extern volatile unsigned long kernel_flag, kernel_counter;
 182 extern volatile unsigned char active_kernel_processor;
 183 extern void smp_message_irq(int cpl, struct pt_regs *regs);
 184 extern void smp_reschedule_irq(int cpl, struct pt_regs *regs);
 185 extern unsigned long ipi_count;
 186 extern void smp_invalidate_rcv(void);           /* Process an NMI */
 187 extern volatile unsigned long kernel_counter;
 188 extern volatile unsigned long syscall_count;
 189 
 190 /*
 191  *      General functions that each host system must provide.
 192  */
 193  
 194 extern void smp_callin(void);
 195 extern void smp_boot_cpus(void);
 196 extern void smp_store_cpu_info(int id);         /* Store per cpu info (like the initial udelay numbers */
 197 
 198 /*
 199  *      APIC handlers: Note according to the Intel specification update
 200  *      you should put reads between APIC writes.
 201  *      Intel Pentium processor specification update [11AP, pg 64]
 202  *              "Back to Back Assertions of HOLD May Cause Lost APIC Write Cycle"
 203  */
 204 
 205 extern __inline void apic_write(unsigned long reg, unsigned long v)
     /*  */
 206 {
 207         *((unsigned long *)(apic_reg+reg))=v;
 208 }
 209 
 210 extern __inline unsigned long apic_read(unsigned long reg)
     /*  */
 211 {
 212         return *((unsigned long *)(apic_reg+reg));
 213 }
 214 
 215 /*
 216  *      This function is needed by all SMP systems. It must _always_ be valid from the initial
 217  *      startup. This may require magic on some systems (in the i86 case we dig out the boot 
 218  *      cpu id from the config and set up a fake apic_reg pointer so that before we activate
 219  *      the apic we get the right answer). Hopefully other processors are more sensible 8)
 220  */
 221  
 222 extern __inline int smp_processor_id(void)
     /*  */
 223 {
 224         return GET_APIC_ID(apic_read(APIC_ID));
 225 }
 226 
 227 #endif /* !ASSEMBLY */
 228 
 229 #define NO_PROC_ID              0xFF            /* No processor magic marker */
 230 
 231 #endif
/* */
root/include/asm-i386/smp.h

INCLUDED FROM

DEFINITIONS
