This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( NCR, NCR_53C810, "53c810"),
45 DEVICE( NCR, NCR_53C820, "53c820"),
46 DEVICE( NCR, NCR_53C825, "53c825"),
47 DEVICE( NCR, NCR_53C815, "53c815"),
48 DEVICE( ATI, ATI_68800, "68800AX"),
49 DEVICE( ATI, ATI_215CT222, "215CT222"),
50 DEVICE( ATI, ATI_210888CX, "210888CX"),
51 DEVICE( ATI, ATI_210888GX, "210888GX"),
52 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
53 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
54 DEVICE( ADL, ADL_2301, "2301"),
55 DEVICE( NS, NS_87410, "87410"),
56 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
57 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
58 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
59 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
60 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
61 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
62 DEVICE( DEC, DEC_BRD, "DC21050"),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
65 DEVICE( DEC, DEC_FDDI, "DEFPA"),
66 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
67 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
68 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
69 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
70 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
71 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
72 DEVICE( AMD, AMD_LANCE, "79C970"),
73 DEVICE( AMD, AMD_SCSI, "53C974"),
74 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
75 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
76 DEVICE( AI, AI_M1435, "M1435"),
77 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
78 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
79 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
80 DEVICE( CT, CT_65545, "65545"),
81 DEVICE( FD, FD_36C70, "TMC-18C30"),
82 DEVICE( SI, SI_503, "85C503"),
83 DEVICE( SI, SI_501, "85C501"),
84 DEVICE( SI, SI_496, "85C496"),
85 DEVICE( SI, SI_601, "85C601"),
86 DEVICE( SI, SI_5511, "85C5511"),
87 DEVICE( SI, SI_5513, "85C5513"),
88 DEVICE( HP, HP_J2585A, "J2585A"),
89 #if 0
90 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
91 DEVICE( SMC, SMC_37C922, "FDC 37C922"),
92 #else
93 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
94 #endif
95 DEVICE( DPT, DPT, "SmartCache/Raid"),
96 DEVICE( OPTI, OPTI_82C557, "82C557"),
97 DEVICE( OPTI, OPTI_82C558, "82C558"),
98 DEVICE( OPTI, OPTI_82C621, "82C621"),
99 DEVICE( OPTI, OPTI_82C822, "82C822"),
100 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
101 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
102 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
103 DEVICE( N9, N9_I128, "Imagine 128"),
104 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
105 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
106 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
107 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
108 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
109 DEVICE( X, X_AGX016, "ITT AGX016"),
110 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
111 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
112 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
113 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
114 DEVICE( CMD, CMD_640, "640 (buggy)"),
115 DEVICE( CMD, CMD_646, "646"),
116 DEVICE( VISION, VISION_QD8500, "QD-8500"),
117 DEVICE( VISION, VISION_QD8580, "QD-8580"),
118 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
119 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
120 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
121 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
122 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
123 DEVICE( AL, AL_M1445, "M1445"),
124 DEVICE( AL, AL_M1449, "M1449"),
125 DEVICE( AL, AL_M1451, "M1451"),
126 DEVICE( AL, AL_M1461, "M1461"),
127 DEVICE( AL, AL_M4803, "M4803"),
128 DEVICE( IMS, IMS_8849, "8849"),
129 DEVICE( REALTEK, REALTEK_8029, "8029"),
130 DEVICE( VIA, VIA_82C505, "VT 82C505"),
131 DEVICE( VIA, VIA_82C561, "VT 82C561"),
132 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
133 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
134 DEVICE( EF, EF_ATM, "155P-MF1"),
135 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
136 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
137 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
138 DEVICE( ZEINET, ZEINET_1221, "1221"),
139 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
140 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
141 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
142 DEVICE( S3, S3_811, "Trio32/Trio64"),
143 DEVICE( S3, S3_868, "Vision 868"),
144 DEVICE( S3, S3_928, "Vision 928-P"),
145 DEVICE( S3, S3_864_1, "Vision 864-P"),
146 DEVICE( S3, S3_864_2, "Vision 864-P"),
147 DEVICE( S3, S3_964_1, "Vision 964-P"),
148 DEVICE( S3, S3_964_2, "Vision 964-P"),
149 DEVICE( S3, S3_968, "Vision 968"),
150 DEVICE( INTEL, INTEL_82375, "82375EB"),
151 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
152 DEVICE( INTEL, INTEL_82378, "82378IB"),
153 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
154 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
155 DEVICE( INTEL, INTEL_7116, "SAA7116"),
156 DEVICE( INTEL, INTEL_82865, "82865"),
157 DEVICE( INTEL, INTEL_82437, "82437"),
158 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
159 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
160 DEVICE( INTEL, INTEL_P6, "Experimental P6 bridge"),
161 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
162 DEVICE( ADAPTEC, ADAPTEC_294x, "294x"),
163 DEVICE( ADAPTEC, ADAPTEC_2940, "2940"),
164 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
165 DEVICE( HER, HER_STING, "Stingray"),
166 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
167 };
168
169
170 #ifdef CONFIG_PCI_OPTIMIZE
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187 struct optimization_type {
188 const char *type;
189 const char *off;
190 const char *on;
191 } bridge_optimization[] = {
192 {"Cache L2", "write trough", "write back"},
193 {"CPU-PCI posted write", "off", "on"},
194 {"CPU-Memory posted write", "off", "on"},
195 {"PCI-Memory posted write", "off", "on"},
196 {"PCI burst", "off", "on"}
197 };
198
199 #define NUM_OPTIMIZATIONS \
200 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
201
202 struct bridge_mapping_type {
203 unsigned char addr;
204 unsigned char mask;
205 unsigned char value;
206 } bridge_mapping[] = {
207
208
209
210
211
212
213
214 {0x0 ,0x02 ,0x02 },
215 {0x53 ,0x02 ,0x02 },
216 {0x53 ,0x01 ,0x01 },
217 {0x54 ,0x01 ,0x01 },
218 {0x54 ,0x02 ,0x02 },
219
220
221
222
223
224 {0x50 ,0x10 ,0x00 },
225 {0x51 ,0x40 ,0x40 },
226 {0x0 ,0x0 ,0x0 },
227 {0x0 ,0x0 ,0x0 },
228 {0x0 ,0x0 ,0x0 },
229
230
231
232
233
234
235 {0x0 ,0x1 ,0x1 },
236 {0x0 ,0x2 ,0x0 },
237 {0x0 ,0x0 ,0x0 },
238 {0x0 ,0x0 ,0x0 },
239 {0x0 ,0x0 ,0x0 }
240 };
241
242 #endif
243
244
245
246
247
248 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
249 {
250 int min = 0,
251 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
252
253 for ( ; ; )
254 {
255 int i = (min + max) >> 1;
256 long order;
257
258 order = dev_info[i].vendor - (long) vendor;
259 if (!order)
260 order = dev_info[i].device - (long) dev;
261
262 if (order < 0)
263 {
264 min = i + 1;
265 if ( min > max )
266 return 0;
267 continue;
268 }
269
270 if (order > 0)
271 {
272 max = i - 1;
273 if ( min > max )
274 return 0;
275 continue;
276 }
277
278 return & dev_info[ i ];
279 }
280 }
281
282
283 const char *pci_strbioserr (int error)
284 {
285 switch (error) {
286 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
287 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
288 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
289 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
290 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
291 case PCIBIOS_SET_FAILED: return "SET_FAILED";
292 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
293 default: return "Unknown error status";
294 }
295 }
296
297
298 const char *pci_strclass (unsigned int class)
299 {
300 switch (class >> 8) {
301 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
302 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
303
304 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
305 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
306 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
307 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
308 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
309 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
310
311 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
312 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
313 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
314 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
315 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
316
317 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
318 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
319 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
320
321 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
322 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
323 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
324
325 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
326 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
327 case PCI_CLASS_MEMORY_OTHER: return "Memory";
328
329 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
330 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
331 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
332 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
333 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
334 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
335 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
336 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
337 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
338
339 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
340 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
341 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
342
343 case PCI_CLASS_SYSTEM_PIC: return "PIC";
344 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
345 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
346 case PCI_CLASS_SYSTEM_RTC: return "RTC";
347 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
348
349 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
350 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
351 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
352 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
353
354 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
355 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
356
357 case PCI_CLASS_PROCESSOR_386: return "386";
358 case PCI_CLASS_PROCESSOR_486: return "486";
359 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
360 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
361 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
362 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
363
364 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
365 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
366 case PCI_CLASS_SERIAL_SSA: return "SSA";
367 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
368
369 default: return "Unknown class";
370 }
371 }
372
373
374 const char *pci_strvendor(unsigned int vendor)
375 {
376 switch (vendor) {
377 case PCI_VENDOR_ID_NCR: return "NCR";
378 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
379 case PCI_VENDOR_ID_DPT: return "DPT";
380 case PCI_VENDOR_ID_S3: return "S3 Inc.";
381 case PCI_VENDOR_ID_OPTI: return "OPTI";
382 case PCI_VENDOR_ID_UMC: return "UMC";
383 case PCI_VENDOR_ID_DEC: return "DEC";
384 case PCI_VENDOR_ID_MATROX: return "Matrox";
385 case PCI_VENDOR_ID_INTEL: return "Intel";
386 #if 0
387 case PCI_VENDOR_ID_SMC: return "SMC";
388 #else
389 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
390 #endif
391 case PCI_VENDOR_ID_ATI: return "ATI";
392 case PCI_VENDOR_ID_WEITEK: return "Weitek";
393 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
394 case PCI_VENDOR_ID_BUSLOGIC: return "Bus Logic";
395 case PCI_VENDOR_ID_N9: return "Number Nine";
396 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
397 case PCI_VENDOR_ID_AL: return "Acer Labs";
398 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
399 case PCI_VENDOR_ID_CMD: return "CMD";
400 case PCI_VENDOR_ID_VISION: return "Vision";
401 case PCI_VENDOR_ID_AMD: return "AMD";
402 case PCI_VENDOR_ID_VLSI: return "VLSI";
403 case PCI_VENDOR_ID_ADL: return "Advance Logic";
404 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
405 case PCI_VENDOR_ID_TRIDENT: return "Trident";
406 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
407 case PCI_VENDOR_ID_NS: return "NS";
408 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
409 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
410 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
411 case PCI_VENDOR_ID_IMS: return "IMS";
412 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
413 case PCI_VENDOR_ID_EF: return "Efficient Networks";
414 case PCI_VENDOR_ID_HER: return "Hercules";
415 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
416 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
417 case PCI_VENDOR_ID_FD: return "Future Domain";
418 case PCI_VENDOR_ID_WINBOND: return "Winbond";
419 case PCI_VENDOR_ID_3COM: return "3Com";
420 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
421 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
422 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
423 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
424 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
425 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
426 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
427 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
428 case PCI_VENDOR_ID_OLICOM: return "Olicom";
429 default: return "Unknown vendor";
430 }
431 }
432
433
434 const char *pci_strdev(unsigned int vendor, unsigned int device)
435 {
436 struct pci_dev_info *info;
437
438 info = pci_lookup_dev(vendor, device);
439 return info ? info->name : "Unknown device";
440 }
441
442
443
444
445
446
447 static void burst_bridge(unsigned char bus, unsigned char devfn,
448 unsigned char pos, int turn_on)
449 {
450 #ifdef CONFIG_PCI_OPTIMIZE
451 struct bridge_mapping_type *bmap;
452 unsigned char val;
453 int i;
454
455 pos *= NUM_OPTIMIZATIONS;
456 printk("PCI bridge optimization.\n");
457 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
458 printk(" %s: ", bridge_optimization[i].type);
459 bmap = &bridge_mapping[pos + i];
460 if (!bmap->addr) {
461 printk("Not supported.");
462 } else {
463 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
464 if ((val & bmap->mask) == bmap->value) {
465 printk("%s.", bridge_optimization[i].on);
466 if (!turn_on) {
467 pcibios_write_config_byte(bus, devfn,
468 bmap->addr,
469 (val | bmap->mask)
470 - bmap->value);
471 printk("Changed! Now %s.", bridge_optimization[i].off);
472 }
473 } else {
474 printk("%s.", bridge_optimization[i].off);
475 if (turn_on) {
476 pcibios_write_config_byte(bus, devfn,
477 bmap->addr,
478 (val & (0xff - bmap->mask))
479 + bmap->value);
480 printk("Changed! Now %s.", bridge_optimization[i].on);
481 }
482 }
483 }
484 printk("\n");
485 }
486 #endif
487 }
488
489
490
491
492
493
494
495
496 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
497 {
498 unsigned long base;
499 unsigned int l, class_rev, bus, devfn;
500 unsigned short vendor, device, status;
501 unsigned char bist, latency, min_gnt, max_lat;
502 int reg, len = 0;
503 const char *str;
504
505 bus = dev->bus->number;
506 devfn = dev->devfn;
507
508 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
509 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
510 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
511 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
512 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
513 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
514 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
515 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
516 if (len + 80 > size) {
517 return -1;
518 }
519 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
520 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
521
522 if (len + 80 > size) {
523 return -1;
524 }
525 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
526 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
527 pci_strdev(vendor, device), class_rev & 0xff);
528
529 if (!pci_lookup_dev(vendor, device)) {
530 len += sprintf(buf + len,
531 "Vendor id=%x. Device id=%x.\n ",
532 vendor, device);
533 }
534
535 str = 0;
536 switch (status & PCI_STATUS_DEVSEL_MASK) {
537 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
538 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
539 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
540 }
541 if (len + strlen(str) > size) {
542 return -1;
543 }
544 len += sprintf(buf + len, str);
545
546 if (status & PCI_STATUS_FAST_BACK) {
547 # define fast_b2b_capable "Fast back-to-back capable. "
548 if (len + strlen(fast_b2b_capable) > size) {
549 return -1;
550 }
551 len += sprintf(buf + len, fast_b2b_capable);
552 # undef fast_b2b_capable
553 }
554
555 if (bist & PCI_BIST_CAPABLE) {
556 # define BIST_capable "BIST capable. "
557 if (len + strlen(BIST_capable) > size) {
558 return -1;
559 }
560 len += sprintf(buf + len, BIST_capable);
561 # undef BIST_capable
562 }
563
564 if (dev->irq) {
565 if (len + 40 > size) {
566 return -1;
567 }
568 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
569 }
570
571 if (dev->master) {
572 if (len + 80 > size) {
573 return -1;
574 }
575 len += sprintf(buf + len, "Master Capable. ");
576 if (latency)
577 len += sprintf(buf + len, "Latency=%d. ", latency);
578 else
579 len += sprintf(buf + len, "No bursts. ");
580 if (min_gnt)
581 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
582 if (max_lat)
583 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
584 }
585
586 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
587 if (len + 40 > size) {
588 return -1;
589 }
590 pcibios_read_config_dword(bus, devfn, reg, &l);
591 base = l;
592 if (!base) {
593 continue;
594 }
595
596 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
597 len += sprintf(buf + len,
598 "\n I/O at 0x%lx.",
599 base & PCI_BASE_ADDRESS_IO_MASK);
600 } else {
601 const char *pref, *type = "unknown";
602
603 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
604 pref = "P";
605 } else {
606 pref = "Non-p";
607 }
608 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
609 case PCI_BASE_ADDRESS_MEM_TYPE_32:
610 type = "32 bit"; break;
611 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
612 type = "20 bit"; break;
613 case PCI_BASE_ADDRESS_MEM_TYPE_64:
614 type = "64 bit";
615
616 reg += 4;
617 pcibios_read_config_dword(bus, devfn, reg, &l);
618 base |= ((u64) l) << 32;
619 break;
620 }
621 len += sprintf(buf + len,
622 "\n %srefetchable %s memory at "
623 "0x%lx.", pref, type,
624 base & PCI_BASE_ADDRESS_MEM_MASK);
625 }
626 }
627
628 len += sprintf(buf + len, "\n");
629 return len;
630 }
631
632
633
634
635
636
637 int get_pci_list(char *buf)
638 {
639 int nprinted, len, size;
640 struct pci_dev *dev;
641 # define MSG "\nwarning: page-size limit reached!\n"
642
643
644 size = PAGE_SIZE - (strlen(MSG) + 1);
645 len = sprintf(buf, "PCI devices found:\n");
646
647 for (dev = pci_devices; dev; dev = dev->next) {
648 nprinted = sprint_dev_config(dev, buf + len, size - len);
649 if (nprinted < 0) {
650 return len + sprintf(buf + len, MSG);
651 }
652 len += nprinted;
653 }
654 return len;
655 }
656
657
658
659
660
661
662 static void *pci_malloc(long size, unsigned long *mem_startp)
663 {
664 void *mem;
665
666 #ifdef DEBUG
667 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
668 #endif
669 mem = (void*) *mem_startp;
670 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
671 memset(mem, 0, size);
672 return mem;
673 }
674
675
676 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
677 {
678 unsigned int devfn, l, max;
679 unsigned char cmd, tmp, hdr_type = 0;
680 struct pci_dev_info *info;
681 struct pci_dev *dev;
682 struct pci_bus *child;
683
684 #ifdef DEBUG
685 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
686 #endif
687
688 max = bus->secondary;
689 for (devfn = 0; devfn < 0xff; ++devfn) {
690 if (PCI_FUNC(devfn) == 0) {
691 pcibios_read_config_byte(bus->number, devfn,
692 PCI_HEADER_TYPE, &hdr_type);
693 } else if (!(hdr_type & 0x80)) {
694
695 continue;
696 }
697
698 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
699 &l);
700
701 if (l == 0xffffffff || l == 0x00000000) {
702 hdr_type = 0;
703 continue;
704 }
705
706 dev = pci_malloc(sizeof(*dev), mem_startp);
707 dev->bus = bus;
708
709
710
711
712
713 dev->next = pci_devices;
714 pci_devices = dev;
715
716 dev->devfn = devfn;
717 dev->vendor = l & 0xffff;
718 dev->device = (l >> 16) & 0xffff;
719
720
721
722
723
724
725 info = pci_lookup_dev(dev->vendor, dev->device);
726 if (!info) {
727 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
728 dev->vendor, dev->device);
729 } else {
730
731 if (info->bridge_type != 0xff) {
732 burst_bridge(bus->number, devfn,
733 info->bridge_type, 1);
734 }
735 }
736
737
738 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
739 &cmd);
740 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
741 cmd | PCI_COMMAND_MASTER);
742 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
743 &tmp);
744 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
745 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
746 cmd);
747
748
749 pcibios_read_config_byte(bus->number, devfn,
750 PCI_INTERRUPT_LINE, &dev->irq);
751
752
753 pcibios_read_config_dword(bus->number, devfn,
754 PCI_CLASS_REVISION, &l);
755 l = l >> 8;
756 dev->class = l;
757
758
759
760
761 dev->sibling = bus->devices;
762 bus->devices = dev;
763
764 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
765 unsigned int buses;
766 unsigned short cr;
767
768
769
770
771 child = pci_malloc(sizeof(*child), mem_startp);
772 child->next = bus->children;
773 bus->children = child;
774 child->self = dev;
775 child->parent = bus;
776
777
778
779
780
781 child->number = child->secondary = ++max;
782 child->primary = bus->secondary;
783 child->subordinate = 0xff;
784
785
786
787
788 pcibios_read_config_word(bus->number, devfn,
789 PCI_COMMAND, &cr);
790 pcibios_write_config_word(bus->number, devfn,
791 PCI_COMMAND, 0x0000);
792 pcibios_write_config_word(bus->number, devfn,
793 PCI_STATUS, 0xffff);
794
795
796
797 pcibios_read_config_dword(bus->number, devfn, 0x18,
798 &buses);
799 buses &= 0xff000000;
800 buses |= (((unsigned int)(child->primary) << 0) |
801 ((unsigned int)(child->secondary) << 8) |
802 ((unsigned int)(child->subordinate) << 16));
803 pcibios_write_config_dword(bus->number, devfn, 0x18,
804 buses);
805
806
807
808 max = scan_bus(child, mem_startp);
809
810
811
812
813 child->subordinate = max;
814 buses = (buses & 0xff00ffff)
815 | ((unsigned int)(child->subordinate) << 16);
816 pcibios_write_config_dword(bus->number, devfn, 0x18,
817 buses);
818 pcibios_write_config_word(bus->number, devfn,
819 PCI_COMMAND, cr);
820 }
821 }
822
823
824
825
826
827
828
829 return max;
830 }
831
832
833 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
834 {
835 mem_start = pcibios_init(mem_start, mem_end);
836
837 if (!pcibios_present()) {
838 printk("pci_init: no BIOS32 detected\n");
839 return mem_start;
840 }
841
842 printk("Probing PCI hardware.\n");
843
844 memset(&pci_root, 0, sizeof(pci_root));
845 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
846
847
848 mem_start = pcibios_fixup(mem_start, mem_end);
849
850 #ifdef DEBUG
851 {
852 int len = get_pci_list((char*)mem_start);
853 if (len) {
854 ((char *) mem_start)[len] = '\0';
855 printk("%s\n", (char *) mem_start);
856 }
857 }
858 #endif
859 return mem_start;
860 }