root/drivers/net/pi2.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. pi0_preprobe
  2. random
  3. wrtscc
  4. rdscc
  5. switchbuffers
  6. hardware_send_packet
  7. setup_rx_dma
  8. setup_tx_dma
  9. tdelay
  10. free_p
  11. a_txint
  12. a_exint
  13. a_rxint
  14. b_rxint
  15. b_txint
  16. b_exint
  17. hw_probe
  18. rts
  19. pi_header
  20. pi_rebuild_header
  21. scc_init
  22. chipset_init
  23. pi_init
  24. valid_dma_page
  25. pi_set_mac_address
  26. get_dma_buffer
  27. pi_probe
  28. pi_open
  29. pi_send_packet
  30. pi_interrupt
  31. pi_close
  32. pi_ioctl
  33. pi_get_stats

   1 /*
   2    pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
   3    Copyright (c) 1994 David Perry
   4 
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License version 2, as
   7    published by the Free Software Foundation.
   8 
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12    General Public License for more details.
  13 
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software Foundation,
  16    Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  17 
  18    The file skeleton.c by Donald Becker was used as a starting point
  19    for this driver.
  20 
  21    Revision History
  22 
  23    April 6, 1994  (dp) Created
  24                        version 0.0 ALPHA
  25    April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
  26                        version 0.1 ALPHA
  27    April 13, 1994 (dp) Included address probing from JPM, autoirq
  28                        version 0.2 ALPHA
  29    April 14, 1994 (ac) Sketched in the NET3 changes.
  30    April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
  31                        instead of kmalloc() to ensure that DMA buffers will
  32                        reside under the 16 meg line.
  33                        version 0.4 ALPHA
  34    April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
  35                        Fixed a nasty problem with DMA.
  36                        version 0.5 ALPHA
  37    June 6, 1994 (ac)   Fixed to match the buffer locking changes. Added a hack to
  38                        fix a funny I see (search for HACK) and fixed the calls in
  39                        init() so it doesn't migrate module based ethernet cards up
  40                        to eth2 Took out the old module ideas as they are no longer
  41                        relevant to the PI driver.
  42    July 16, 1994 (dp)  Fixed the B channel rx overrun problem ac referred to 
  43                        above. Also added a bit of a hack to improve the maximum
  44                        baud rate on the B channel (Search for STUFF2). Included
  45                        ioctl stuff from John Paul Morrison. version 0.6 ALPHA
  46    Feb 9, 1995 (dp)    Updated for 1.1.90 kernel
  47                        version 0.7 ALPHA
  48    Apr 6, 1995 (ac)    Tweaks for NET3 pre snapshot 002 AX.25
  49    April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
  50                        when changing the baud rate or clock mode.
  51                        version 0.8 ALPHA
  52    July 17, 1995 (ac)  Finally polishing of AX25.030+ support
  53          
  54 */
  55 
  56 /* The following #define invokes a hack that will improve performance (baud)
  57    for the B port. The up side is it makes 9600 baud work ok on the B port.
  58    It may do 38400, depending on the host. The down side is it burns up
  59    CPU cycles with ints locked for up to 1 character time, at the beginning
  60    of each transmitted packet. If this causes you to lose sleep, #undefine it.
  61 */
  62 
  63 /*#define STUFF2 1*/
  64 
  65 /* The default configuration */
  66 #define PI_DMA 3
  67 
  68 #define DEF_A_SPEED 0           /* 0 means external clock */
  69 #define DEF_A_TXDELAY 15        /* 15 mS transmit delay */
  70 #define DEF_A_PERSIST 128       /* 50% persistence */
  71 #define DEF_A_SLOTIME 15        /* 15 mS slot time */
  72 #define DEF_A_SQUELDELAY 1      /* 1 mS squelch delay - allows fcs and flag */
  73 #define DEF_A_CLOCKMODE 0       /* clock mode - 0 is normal */
  74 
  75 #define DEF_B_SPEED 1200        /* 1200 baud */
  76 #define DEF_B_TXDELAY 40        /* 400 mS */
  77 #define DEF_B_PERSIST 128       /* 50% */
  78 #define DEF_B_SLOTIME 30        /* 300 mS */
  79 #define DEF_B_SQUELDELAY 3      /* 30 mS */
  80 #define DEF_B_CLOCKMODE 0       /* Normal clock mode */
  81 
  82 struct device *init_etherdev(struct device *dev, int sizeof_private,
  83                              unsigned long *mem_startp);
  84 
  85 static const char *version =
  86 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
  87 
  88 /* The following #define is only really required for the PI card, not
  89    the PI2 - but it's safer to leave it in. */
  90 #define REALLY_SLOW_IO 1
  91 
  92 #define PI2_MODULE 0
  93 
  94 #if PI2_MODULE > 0
  95 #include <linux/modules.h>
  96 #endif
  97 
  98 #include <linux/config.h>
  99 #include <linux/kernel.h>
 100 #include <linux/sched.h>
 101 #include <linux/types.h>
 102 #include <linux/fcntl.h>
 103 #include <linux/interrupt.h>
 104 #include <linux/ptrace.h>
 105 #include <linux/ioport.h>
 106 #include <linux/in.h>
 107 #include <linux/malloc.h>
 108 #include <linux/string.h>
 109 #include <linux/errno.h>
 110 #include <asm/system.h>
 111 #include <asm/bitops.h>
 112 #include <asm/io.h>
 113 #include <asm/dma.h>
 114 #include <asm/segment.h>
 115 #include <linux/inet.h>
 116 #include <linux/netdevice.h>
 117 #include <linux/etherdevice.h>
 118 #include <linux/skbuff.h>
 119 #include <linux/timer.h>
 120 #include <linux/if_arp.h>
 121 #include "pi2.h"
 122 #include "z8530.h"
 123 #include <net/ax25.h>
 124 
 125 
 126 struct mbuf {
 127     struct mbuf *next;
 128     int cnt;
 129     char data[0];
 130 };
 131 
 132 /*
 133  *      The actual devices we will use
 134  */
 135  
 136 /*
 137  *      PI device declarations.
 138  */
 139  
 140 static int pi0_preprobe(struct device *dev){return 0;}  /* Dummy probe function */
     /* [previous][next][first][last][top][bottom][index][help] */
 141 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 142 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 143 
 144  
 145 /* The number of low I/O ports used by the card. */
 146 #define PI_TOTAL_SIZE   8
 147 
 148 
 149 /* Index to functions, as function prototypes. */
 150 
 151 static int pi_probe(struct device *dev, int card_type);
 152 static int pi_open(struct device *dev);
 153 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
 154 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
 155 static int pi_close(struct device *dev);
 156 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 157 static struct enet_statistics *pi_get_stats(struct device *dev);
 158 static void rts(struct pi_local *lp, int x);
 159 static void b_rxint(struct device *dev, struct pi_local *lp);
 160 static void b_txint(struct pi_local *lp);
 161 static void b_exint(struct pi_local *lp);
 162 static void a_rxint(struct device *dev, struct pi_local *lp);
 163 static void a_txint(struct pi_local *lp);
 164 static void a_exint(struct pi_local *lp);
 165 static char *get_dma_buffer(unsigned long *mem_ptr);
 166 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 167 
 168 static char ax25_bcast[7] =
 169 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 170 static char ax25_test[7] =
 171 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 172 
 173 static int ext2_secrm_seed = 152;       /* Random generator base */
 174 
 175 static inline unsigned char random(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 176 {
 177     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
 178                             * 69069l + 1);
 179 }
 180 
 181 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
     /* [previous][next][first][last][top][bottom][index][help] */
 182 {
 183     /* assume caller disables interrupts! */
 184     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 185     outb_p(sccreg, ctl);        /* Select register */
 186     outb_p(val, ctl);           /* Output value */
 187     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 188 }
 189 
 190 static inline int rdscc(int cbase, int ctl, int sccreg)
     /* [previous][next][first][last][top][bottom][index][help] */
 191 {
 192     int retval;
 193 
 194     /* assume caller disables interrupts! */
 195     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 196     outb_p(sccreg, ctl);        /* Select register */
 197     retval = inb_p(ctl);
 198     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 199     return retval;
 200 }
 201 
 202 static void switchbuffers(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 203 {
 204     if (lp->rcvbuf == lp->rxdmabuf1)
 205         lp->rcvbuf = lp->rxdmabuf2;
 206     else
 207         lp->rcvbuf = lp->rxdmabuf1;
 208 }
 209 
 210 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 211 {
 212     char kickflag;
 213     unsigned long flags;
 214 
 215     lp->stats.tx_packets++;
 216 
 217     save_flags(flags);
 218     cli();
 219     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 220     restore_flags(flags);
 221 
 222     skb_queue_tail(&lp->sndq, skb);
 223     if (kickflag) {
 224         /* simulate interrupt to xmit */
 225         switch (lp->base & 2) {
 226         case 2:
 227             a_txint(lp);        /* process interrupt */
 228             break;
 229         case 0:
 230             save_flags(flags);
 231             cli();
 232             if (lp->tstate == IDLE)
 233                 b_txint(lp);
 234             restore_flags(flags);
 235             break;
 236         }
 237     }
 238 }
 239 
 240 static void setup_rx_dma(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 241 {
 242     unsigned long flags;
 243     int cmd;
 244     unsigned long dma_abs;
 245     unsigned dmachan;
 246 
 247     save_flags(flags);
 248     cli();
 249 
 250     dma_abs = (unsigned long) (lp->rcvbuf->data);
 251     dmachan = lp->dmachan;
 252     cmd = lp->base + CTL;
 253 
 254     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 255         panic("PI: RX buffer violates DMA boundary!");
 256 
 257     /* Get ready for RX DMA */
 258     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 259 
 260     disable_dma(dmachan);
 261     clear_dma_ff(dmachan);
 262 
 263     /* Set DMA mode register to single transfers, incrementing address,
 264      *  auto init, writes
 265      */
 266     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 267     set_dma_addr(dmachan, dma_abs);
 268     set_dma_count(dmachan, lp->bufsiz);
 269     enable_dma(dmachan);
 270 
 271     /* If a packet is already coming in, this line is supposed to
 272            avoid receiving a partial packet.
 273      */
 274     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 275 
 276     /* Enable RX dma */
 277     wrtscc(lp->cardbase, cmd, R1,
 278       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 279 
 280     restore_flags(flags);
 281 }
 282 
 283 static void setup_tx_dma(struct pi_local *lp, int length)
     /* [previous][next][first][last][top][bottom][index][help] */
 284 {
 285     unsigned long dma_abs;
 286     unsigned long flags;
 287     unsigned long dmachan;
 288 
 289     save_flags(flags);
 290     cli();
 291 
 292     dmachan = lp->dmachan;
 293     dma_abs = (unsigned long) (lp->txdmabuf);
 294 
 295     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 296         panic("PI: TX buffer violates DMA boundary!");
 297 
 298     disable_dma(dmachan);
 299     /* Set DMA mode register to single transfers, incrementing address,
 300      *  no auto init, reads
 301      */
 302     set_dma_mode(dmachan, DMA_MODE_WRITE);
 303     clear_dma_ff(dmachan);
 304     set_dma_addr(dmachan, dma_abs);
 305     /* output byte count */
 306     set_dma_count(dmachan, length);
 307 
 308     restore_flags(flags);
 309 }
 310 
 311 static void tdelay(struct pi_local *lp, int time)
     /* [previous][next][first][last][top][bottom][index][help] */
 312 {
 313     int port;
 314     unsigned int t1;
 315     unsigned char sc;
 316 
 317     if (lp->base & 2) {         /* If A channel */
 318         sc = SC1;
 319         t1 = time;
 320         port = lp->cardbase + TMR1;
 321     } else {
 322         sc = SC2;
 323         t1 = 10 * time;         /* 10s of milliseconds for the B channel */
 324         port = lp->cardbase + TMR2;
 325         wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
 326     }
 327 
 328     /* Setup timer sc */
 329     outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
 330 
 331     /* times 2 to make millisecs */
 332     outb_p((t1 << 1) & 0xFF, port);
 333     outb_p((t1 >> 7) & 0xFF, port);
 334 
 335     /* Enable correct int for timeout */
 336     wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
 337     wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
 338 }
 339 
 340 static void free_p(struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 341 {
 342         dev_kfree_skb(skb, FREE_WRITE);
 343 }
 344 
 345 static void a_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 346 {
 347     int cmd;
 348     unsigned long flags;
 349 
 350     save_flags(flags);
 351     cli();
 352 
 353     cmd = CTL + lp->base;
 354 
 355     switch (lp->tstate) {
 356     case IDLE:
 357         /* Transmitter idle. Find a frame for transmission */
 358         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 359             rts(lp, OFF);
 360             restore_flags(flags);
 361             return;
 362         }
 363         /* If a buffer to send, we drop thru here */
 364     case DEFER:
 365         /* we may have deferred prev xmit attempt */
 366         /* Check DCD - debounce it
 367          * See Intel Microcommunications Handbook, p2-308
 368          */
 369         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 370         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 371         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 372             lp->tstate = DEFER;
 373             tdelay(lp, 100);
 374             /* defer until DCD transition or timeout */
 375             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 376             restore_flags(flags);
 377             return;
 378         }
 379         if (random() > lp->persist) {
 380             lp->tstate = DEFER;
 381             tdelay(lp, lp->slotime);
 382             restore_flags(flags);
 383             return;
 384         }
 385         /* Assert RTS early minimize collision window */
 386         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 387         rts(lp, ON);            /* Transmitter on */
 388         lp->tstate = ST_TXDELAY;
 389         tdelay(lp, lp->txdelay);
 390         restore_flags(flags);
 391         return;
 392     default:
 393         break;
 394     }                           /* end switch(lp->state) */
 395 
 396     restore_flags(flags);
 397 }                               /*a_txint */
 398 
 399 static void a_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 400 {
 401     unsigned long flags;
 402     int cmd;
 403     char st;
 404     int length;
 405 
 406     save_flags(flags);
 407     cli();                      /* disable interrupts */
 408 
 409     st = rdscc(lp->cardbase, lp->base + CTL, R0);       /* Fetch status */
 410 
 411     /* reset external status latch */
 412     wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
 413     cmd = lp->base + CTL;
 414 
 415     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
 416         setup_rx_dma(lp);
 417         lp->rstate = ACTIVE;
 418     }
 419     switch (lp->tstate) {
 420     case ACTIVE:
 421         free_p(lp->sndbuf);
 422         lp->sndbuf = NULL;
 423         lp->tstate = FLAGOUT;
 424         tdelay(lp, lp->squeldelay);
 425         break;
 426     case FLAGOUT:
 427         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 428             /* Nothing to send - return to receive mode */
 429             lp->tstate = IDLE;
 430             rts(lp, OFF);
 431             restore_flags(flags);
 432             return;
 433         }
 434         /* NOTE - fall through if more to send */
 435     case ST_TXDELAY:
 436         /* Disable DMA chan */
 437         disable_dma(lp->dmachan);
 438 
 439         /* Set up for TX dma */
 440         wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 441 
 442 
 443         /* Get all chars */
 444         /* Strip KISS control byte */
 445         length = lp->sndbuf->len - 1;
 446         memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
 447 
 448 
 449         /* Setup DMA controller for tx */
 450         setup_tx_dma(lp, length);
 451 
 452         /* select transmit interrupts to enable */
 453         /* Allow DMA on chan */
 454         enable_dma(lp->dmachan);
 455 
 456         /* reset CRC, Txint pend*/
 457         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
 458 
 459         /* allow Underrun int only */
 460         wrtscc(lp->cardbase, cmd, R15, TxUIE);
 461 
 462         /* Enable TX DMA */
 463         wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
 464 
 465         /* Send CRC on underrun */
 466         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
 467 
 468 
 469         /* packet going out now */
 470         lp->tstate = ACTIVE;
 471         break;
 472     case DEFER:
 473         /* we have deferred prev xmit attempt
 474          * See Intel Microcommunications Handbook, p2-308
 475          */
 476         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 477         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 478         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 479             lp->tstate = DEFER;
 480             tdelay(lp, 100);
 481             /* Defer until dcd transition or 100mS timeout */
 482             wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
 483             restore_flags(flags);
 484             return;
 485         }
 486         if (random() > lp->persist) {
 487             lp->tstate = DEFER;
 488             tdelay(lp, lp->slotime);
 489             restore_flags(flags);
 490             return;
 491         }
 492         /* Assert RTS early minimize collision window */
 493         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 494         rts(lp, ON);            /* Transmitter on */
 495         lp->tstate = ST_TXDELAY;
 496         tdelay(lp, lp->txdelay);
 497         restore_flags(flags);
 498         return;
 499     }                           /* switch(lp->tstate) */
 500 
 501     restore_flags(flags);
 502 }                               /* a_exint() */
 503 
 504 /* Receive interrupt handler for the A channel
 505  */
 506 static void a_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 507 {
 508     unsigned long flags;
 509     int cmd;
 510     int bytecount;
 511     char rse;
 512     struct sk_buff *skb;
 513     int sksize, pkt_len;
 514     struct mbuf *cur_buf;
 515     unsigned char *cfix;
 516 
 517     save_flags(flags);
 518     cli();                      /* disable interrupts */
 519     cmd = lp->base + CTL;
 520 
 521     rse = rdscc(lp->cardbase, cmd, R1); /* Get special condition bits from R1 */
 522     if (rse & Rx_OVR)
 523         lp->rstate = RXERROR;
 524 
 525     if (rse & END_FR) {
 526         /* If end of frame */
 527         /* figure length of frame from 8237 */
 528         clear_dma_ff(lp->dmachan);
 529         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
 530 
 531         if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
 532             if ((bytecount >= 10) && (rse & CRC_ERR)) {
 533                 lp->stats.rx_crc_errors++;
 534             }
 535             if (lp->rstate == RXERROR) {
 536                 lp->stats.rx_errors++;
 537                 lp->stats.rx_over_errors++;
 538             }
 539             /* Reset buffer pointers */
 540             lp->rstate = ACTIVE;
 541             setup_rx_dma(lp);
 542         } else {
 543             /* Here we have a valid frame */
 544             /* Toss 2 crc bytes , add one for KISS */
 545             pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
 546 
 547             /* Get buffer for next frame */
 548             cur_buf = lp->rcvbuf;
 549             switchbuffers(lp);
 550             setup_rx_dma(lp);
 551 
 552 
 553             /* Malloc up new buffer. */
 554             sksize = pkt_len;
 555 
 556             skb = dev_alloc_skb(sksize);
 557             if (skb == NULL) {
 558                 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 559                 lp->stats.rx_dropped++;
 560                 restore_flags(flags);
 561                 return;
 562             }
 563             skb->dev = dev;
 564 
 565             /* KISS kludge -  prefix with a 0 byte */
 566             cfix=skb_put(skb,pkt_len);
 567             *cfix++=0;
 568             /* 'skb->data' points to the start of sk_buff data area. */
 569             memcpy(cfix, (char *) cur_buf->data,
 570                    pkt_len - 1);
 571             skb->protocol=htons(ETH_P_AX25);
 572             skb->mac.raw=skb->data;
 573             IS_SKB(skb);
 574             netif_rx(skb);
 575             lp->stats.rx_packets++;
 576         }                       /* end good frame */
 577     }                           /* end EOF check */
 578     wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
 579     restore_flags(flags);
 580 }
 581 
 582 static void b_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 583 {
 584     unsigned long flags;
 585     int cmd;
 586     char rse;
 587     struct sk_buff *skb;
 588     int sksize;
 589     int pkt_len;
 590     unsigned char *cfix;
 591 
 592     save_flags(flags);
 593     cli();                      /* disable interrupts */
 594     cmd = CTL + lp->base;
 595 
 596     rse = rdscc(lp->cardbase, cmd, R1); /* get status byte from R1 */
 597 
 598     if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
 599         /* there is a char to be stored
 600          * read special condition bits before reading the data char
 601          */
 602         if (rse & Rx_OVR) {
 603             /* Rx overrun - toss buffer */
 604             /* reset buffer pointers */
 605             lp->rcp = lp->rcvbuf->data;
 606             lp->rcvbuf->cnt = 0;
 607 
 608             lp->rstate = RXERROR;       /* set error flag */
 609             lp->stats.rx_errors++;
 610             lp->stats.rx_over_errors++;
 611         } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
 612             /* Too large -- toss buffer */
 613             /* reset buffer pointers */
 614             lp->rcp = lp->rcvbuf->data;
 615             lp->rcvbuf->cnt = 0;
 616             lp->rstate = TOOBIG;/* when set, chars are not stored */
 617         }
 618         /* ok, we can store the received character now */
 619         if (lp->rstate == ACTIVE) {     /* If no errors... */
 620             *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
 621             lp->rcvbuf->cnt++;  /* bump count */
 622         } else {
 623             /* got to empty FIFO */
 624             (void) rdscc(lp->cardbase, cmd, R8);
 625             wrtscc(lp->cardbase, cmd, R0, ERR_RES);     /* reset err latch */
 626             lp->rstate = ACTIVE;
 627         }
 628     }
 629     if (rse & END_FR) {
 630         /* END OF FRAME -- Make sure Rx was active */
 631         if (lp->rcvbuf->cnt > 0) {
 632             if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
 633                 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
 634                     lp->stats.rx_crc_errors++;
 635                 }
 636                 lp->rcp = lp->rcvbuf->data;
 637                 lp->rcvbuf->cnt = 0;
 638             } else {
 639                 /* Here we have a valid frame */
 640                 pkt_len = lp->rcvbuf->cnt -= 2; /* Toss 2 crc bytes */
 641                 pkt_len += 1;   /* Make room for KISS control byte */
 642 
 643                 /* Malloc up new buffer. */
 644                 sksize = pkt_len;
 645                 skb = dev_alloc_skb(sksize);
 646                 if (skb == NULL) {
 647                     printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 648                     lp->stats.rx_dropped++;
 649                     restore_flags(flags);
 650                     return;
 651                 }
 652                 skb->dev = dev;
 653 
 654                 /* KISS kludge -  prefix with a 0 byte */
 655                 cfix=skb_put(skb,pkt_len);
 656                 *cfix++=0;
 657                 /* 'skb->data' points to the start of sk_buff data area. */
 658                 memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
 659                 skb->protocol=ntohs(ETH_P_AX25);
 660                 IS_SKB(skb);
 661                 netif_rx(skb);
 662                 lp->stats.rx_packets++;
 663                 /* packet queued - initialize buffer for next frame */
 664                 lp->rcp = lp->rcvbuf->data;
 665                 lp->rcvbuf->cnt = 0;
 666 
 667             }                   /* end good frame queued */
 668         }                       /* end check for active receive upon EOF */
 669         lp->rstate = ACTIVE;    /* and clear error status */
 670     }                           /* end EOF check */
 671     restore_flags(flags);
 672 }
 673 
 674 
 675 static void b_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 676 {
 677     unsigned long flags;
 678     int cmd;
 679     unsigned char c;
 680 
 681     save_flags(flags);
 682     cli();
 683     cmd = CTL + lp->base;
 684 
 685     switch (lp->tstate) {
 686     case CRCOUT:
 687         lp->tstate = FLAGOUT;
 688         tdelay(lp, lp->squeldelay);
 689         restore_flags(flags);
 690         return;
 691     case IDLE:
 692         /* Transmitter idle. Find a frame for transmission */
 693         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 694             /* Nothing to send - return to receive mode
 695              * Tx OFF now - flag should have gone
 696              */
 697             rts(lp, OFF);
 698          
 699             restore_flags(flags);
 700             return;
 701         }
 702         lp->txptr = lp->sndbuf->data;
 703         lp->txptr++;            /* Ignore KISS control byte */
 704         lp->txcnt = (int) lp->sndbuf->len - 1;
 705         /* If a buffer to send, we drop thru here */
 706     case DEFER:         /* we may have deferred prev xmit attempt */
 707         /* Check DCD - debounce it */
 708         /* See Intel Microcommunications Handbook, p2-308 */
 709         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 710         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 711         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 712             lp->tstate = DEFER;
 713             tdelay(lp, 100);
 714             /* defer until DCD transition or timeout */
 715             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 716             restore_flags(flags);
 717             return;
 718         }
 719         if (random() > lp->persist) {
 720             lp->tstate = DEFER;
 721             tdelay(lp, lp->slotime);
 722             restore_flags(flags);
 723             return;
 724         }
 725         rts(lp, ON);            /* Transmitter on */
 726         lp->tstate = ST_TXDELAY;
 727         tdelay(lp, lp->txdelay);
 728         restore_flags(flags);
 729         return;
 730 
 731     case ACTIVE:
 732         /* Here we are actively sending a frame */
 733         if (lp->txcnt--) {
 734             c = *lp->txptr++;
 735             /* next char is gone */
 736             wrtscc(lp->cardbase, cmd, R8, c);
 737             /* stuffing a char satisfies Interrupt condition */
 738         } else {
 739             /* No more to send */
 740             free_p(lp->sndbuf);
 741             lp->sndbuf = NULL;
 742             if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
 743                 /* Did we underrun? */
 744                 /* unexpected underrun */
 745                 lp->stats.tx_errors++;
 746                 lp->stats.tx_fifo_errors++;
 747                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 748                 lp->tstate = FLAGOUT;
 749                 tdelay(lp, lp->squeldelay);
 750                 restore_flags(flags);
 751                 return;
 752             }
 753             lp->tstate = UNDERRUN;      /* Now we expect to underrun */
 754             /* Send flags on underrun */
 755             if (lp->speed) {    /* If internally clocked */
 756                 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
 757             } else {
 758                 wrtscc(lp->cardbase, cmd, R10, CRCPS);
 759             }
 760             wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);    /* reset Tx Int Pend */
 761         }
 762         restore_flags(flags);
 763         return;                 /* back to wait for interrupt */
 764     }                           /* end switch */
 765     restore_flags(flags);
 766 }
 767 
 768 /* Pi SIO External/Status interrupts (for the B channel)
 769  * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
 770  * Receiver automatically goes to Hunt on an abort.
 771  *
 772  * If the Tx Underrun interrupt hits, change state and
 773  * issue a reset command for it, and return.
 774  */
 775 static void b_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 776 {
 777     unsigned long flags;
 778     char st;
 779     int cmd;
 780     char c;
 781 
 782     cmd = CTL + lp->base;
 783     save_flags(flags);
 784     cli();                      /* disable interrupts */
 785     st = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
 786     /* reset external status latch */
 787     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 788 
 789 
 790     switch (lp->tstate) {
 791     case ACTIVE:                /* Unexpected underrun */
 792         free_p(lp->sndbuf);
 793         lp->sndbuf = NULL;
 794         wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 795         lp->tstate = FLAGOUT;
 796         lp->stats.tx_errors++;
 797         lp->stats.tx_fifo_errors++;
 798         tdelay(lp, lp->squeldelay);
 799         restore_flags(flags);
 800         return;
 801     case UNDERRUN:
 802         lp->tstate = CRCOUT;
 803         restore_flags(flags);
 804         return;
 805     case FLAGOUT:
 806         /* Find a frame for transmission */
 807         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 808             /* Nothing to send - return to receive mode
 809              * Tx OFF now - flag should have gone
 810              */
 811             rts(lp, OFF);
 812             lp->tstate = IDLE;
 813             restore_flags(flags);
 814             return;
 815         }
 816         lp->txptr = lp->sndbuf->data;
 817         lp->txptr++;            /* Ignore KISS control byte */
 818         lp->txcnt = (int) lp->sndbuf->len - 1;
 819         /* Get first char to send */
 820         lp->txcnt--;
 821         c = *lp->txptr++;
 822         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 823 
 824         /* Send abort on underrun */
 825         if (lp->speed) {        /* If internally clocked */
 826             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 827         } else {
 828             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 829         }
 830 
 831         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 832         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 833 
 834 #ifdef STUFF2
 835         /* stuff an extra one if we can */
 836         if (lp->txcnt) {
 837             lp->txcnt--;
 838             c = *lp->txptr++;
 839             /* Wait for tx buffer empty */
 840             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 841                 ;   
 842             wrtscc(lp->cardbase, cmd, R8, c);
 843         }
 844 #endif
 845 
 846         /* select transmit interrupts to enable */
 847 
 848         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 849         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 850         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);       /* Tx/Ext ints */
 851 
 852         lp->tstate = ACTIVE;    /* char going out now */
 853         restore_flags(flags);
 854         return;
 855 
 856     case DEFER:
 857         /* Check DCD - debounce it
 858          * See Intel Microcommunications Handbook, p2-308
 859          */
 860         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 861         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 862         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 863             lp->tstate = DEFER;
 864             tdelay(lp, 100);
 865             /* defer until DCD transition or timeout */
 866             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 867             restore_flags(flags);
 868             return;
 869         }
 870         if (random() > lp->persist) {
 871             lp->tstate = DEFER;
 872             tdelay(lp, lp->slotime);
 873             restore_flags(flags);
 874             return;
 875         }
 876         rts(lp, ON);            /* Transmitter on */
 877         lp->tstate = ST_TXDELAY;
 878         tdelay(lp, lp->txdelay);
 879         restore_flags(flags);
 880         return;
 881 
 882     case ST_TXDELAY:
 883 
 884         /* Get first char to send */
 885         lp->txcnt--;
 886         c = *lp->txptr++;
 887         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 888 
 889         /* Send abort on underrun */
 890         if (lp->speed) {        /* If internally clocked */
 891             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 892         } else {
 893             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 894         }
 895 
 896         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 897         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 898 
 899 #ifdef STUFF2
 900         /* stuff an extra one if we can */
 901         if (lp->txcnt) {
 902             lp->txcnt--;
 903             c = *lp->txptr++;
 904             /* Wait for tx buffer empty */
 905             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 906                 ;   
 907             wrtscc(lp->cardbase, cmd, R8, c);
 908         }
 909 #endif
 910 
 911         /* select transmit interrupts to enable */
 912 
 913         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 914         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 915         /* Tx/Extern ints on */
 916         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
 917 
 918         lp->tstate = ACTIVE;    /* char going out now */
 919         restore_flags(flags);
 920         return;
 921     }
 922 
 923     /* Receive Mode only
 924      * This triggers when hunt mode is entered, & since an ABORT
 925      * automatically enters hunt mode, we use that to clean up
 926      * any waiting garbage
 927      */
 928     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
 929         (void) rdscc(lp->cardbase, cmd, R8);
 930         (void) rdscc(lp->cardbase, cmd, R8);
 931         (void) rdscc(lp->cardbase, cmd, R8);
 932         lp->rcp = lp->rcvbuf->data;
 933         lp->rcvbuf->cnt = 0;    /* rewind on DCD transition */
 934     }
 935     restore_flags(flags);
 936 }
 937 
 938 /* Probe for a PI card. */
 939 /* This routine also initializes the timer chip */
 940 
 941 static int hw_probe(int ioaddr)
     /* [previous][next][first][last][top][bottom][index][help] */
 942 {
 943     int time = 1000;            /* Number of milliseconds for test */
 944     unsigned long start_time, end_time;
 945 
 946     int base, tmr0, tmr1, tmrcmd;
 947     int a = 1;
 948     int b = 1;
 949 
 950     base = ioaddr & 0x3f0;
 951     tmr0 = TMR0 + base;
 952     tmr1 = TMR1 + base;
 953     tmrcmd = TMRCMD + base;
 954 
 955     /* Set up counter chip timer 0 for 500 uS period square wave */
 956     /* assuming a 3.68 mhz clock for now */
 957     outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 958     outb_p(922 & 0xFF, tmr0);
 959     outb_p(922 >> 8, tmr0);
 960 
 961     /* Setup timer control word for timer 1*/
 962     outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
 963     outb_p((time << 1) & 0xFF, tmr1);
 964     outb_p((time >> 7) & 0XFF, tmr1);
 965 
 966     /* wait until counter reg is loaded */
 967     do {
 968         /* Latch count for reading */
 969         outb_p(SC1, tmrcmd);
 970         a = inb_p(tmr1);
 971         b = inb_p(tmr1);
 972     } while (b == 0);
 973     start_time = jiffies;
 974     while (b != 0) {
 975         /* Latch count for reading */
 976         outb_p(SC1, tmrcmd);
 977         a = inb_p(tmr1);
 978         b = inb_p(tmr1);
 979         end_time = jiffies;
 980         /* Don't wait forever - there may be no card here */
 981         if ((end_time - start_time) > 200)
 982             return 0;           /* No card found */
 983     }
 984     end_time = jiffies;
 985     /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
 986     if ((end_time - start_time) > 65) {
 987         return (1);             /* PI card found */
 988     } else {
 989         /* Faster crystal - tmr0 needs adjusting */
 990         /* Set up counter chip */
 991         /* 500 uS square wave */
 992         outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 993         outb_p(1844 & 0xFF, tmr0);
 994         outb_p(1844 >> 8, tmr0);
 995         return (2);             /* PI2 card found */
 996     }
 997 }
 998 
 999 static void rts(struct pi_local *lp, int x)
     /* [previous][next][first][last][top][bottom][index][help] */
1000 {
1001     int tc;
1002     long br;
1003     int cmd;
1004     int dummy;
1005 
1006     /* assumes interrupts are off */
1007     cmd = CTL + lp->base;
1008 
1009     /* Reprogram BRG and turn on transmitter to send flags */
1010     if (x == ON) {              /* Turn Tx ON and Receive OFF */
1011         /* Exints off first to avoid abort int */
1012         wrtscc(lp->cardbase, cmd, R15, 0);
1013         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Rx off */
1014         lp->rstate = IDLE;
1015         if (cmd & 2) {          /* if channel a */
1016             /* Set up for TX dma */
1017             wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1018         } else {
1019             wrtscc(lp->cardbase, cmd, R1, 0);   /* No interrupts */
1020         }
1021 
1022         if (!lp->clockmode) {
1023             if (lp->speed) {    /* if internally clocked */
1024                 br = lp->speed; /* get desired speed */
1025                 tc = (lp->xtal / br) - 2;       /* calc 1X BRG divisor */
1026                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1027                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1028             }
1029         }
1030         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1031         /* Transmitter now on */
1032     } else {                    /* Tx OFF and Rx ON */
1033         lp->tstate = IDLE;
1034         wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);       /*  TX off */
1035 
1036         if (!lp->clockmode) {
1037             if (lp->speed) {    /* if internally clocked */
1038                 /* Reprogram BRG for 32x clock for receive DPLL */
1039                 /* BRG off, keep Pclk source */
1040                 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1041                 br = lp->speed; /* get desired speed */
1042                 /* calc 32X BRG divisor */
1043                 tc = ((lp->xtal / 32) / br) - 2;
1044                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1045                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1046                 /* SEARCH mode, BRG source */
1047                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1048                 /* Enable the BRG */
1049                 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1050             }
1051         }
1052         /* Flush rx fifo */
1053         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Make sure rx is off */
1054         wrtscc(lp->cardbase, cmd, R0, ERR_RES); /* reset err latch */
1055         dummy = rdscc(lp->cardbase, cmd, R1);   /* get status byte from R1 */
1056         (void) rdscc(lp->cardbase, cmd, R8);
1057         (void) rdscc(lp->cardbase, cmd, R8);
1058 
1059         (void) rdscc(lp->cardbase, cmd, R8);
1060 
1061         /* Now, turn on the receiver and hunt for a flag */
1062         wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1063         lp->rstate = ACTIVE;    /* Normal state */
1064 
1065         if (cmd & 2) {          /* if channel a */
1066             setup_rx_dma(lp);
1067         } else {
1068             /* reset buffer pointers */
1069             lp->rcp = lp->rcvbuf->data;
1070             lp->rcvbuf->cnt = 0;
1071             wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1072         }
1073         wrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
1074     }
1075 }
1076 
1077 /* Fill in the MAC-level header. */
1078 static int pi_header(struct sk_buff *skb, struct device *dev, unsigned short type,
     /* [previous][next][first][last][top][bottom][index][help] */
1079              void *daddr, void *saddr, unsigned len)
1080 {
1081     return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
1082 }
1083 
1084 /* Rebuild the MAC-level header. */
1085 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /* [previous][next][first][last][top][bottom][index][help] */
1086                              struct sk_buff *skb)
1087 {
1088     return ax25_rebuild_header(buff, dev, raddr, skb);
1089 }
1090 
1091 static void scc_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1092 {
1093     unsigned long flags;
1094     struct pi_local *lp = (struct pi_local *) dev->priv;
1095 
1096     int tc;
1097     long br;
1098     register int cmd;
1099 
1100     /* Initialize 8530 channel for SDLC operation */
1101 
1102     cmd = CTL + lp->base;
1103     save_flags(flags);
1104     cli();
1105 
1106     switch (cmd & CHANA) {
1107     case CHANA:
1108         wrtscc(lp->cardbase, cmd, R9, CHRA);    /* Reset channel A */
1109         wrtscc(lp->cardbase, cmd, R2, 0xff);    /* Initialize interrupt vector */
1110         break;
1111     default:
1112         wrtscc(lp->cardbase, cmd, R9, CHRB);    /* Reset channel B */
1113         break;
1114     }
1115 
1116     /* Deselect all Rx and Tx interrupts */
1117     wrtscc(lp->cardbase, cmd, R1, 0);
1118 
1119     /* Turn off external interrupts (like CTS/CD) */
1120     wrtscc(lp->cardbase, cmd, R15, 0);
1121 
1122     /* X1 clock, SDLC mode */
1123     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1124 
1125     /* Tx/Rx parameters */
1126     if (lp->speed) {            /* Use internal clocking */
1127         wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1128         if (!lp->clockmode)
1129             /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1130             wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1131         else
1132             /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1133             wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1134     } else {                    /* Use external clocking */
1135         wrtscc(lp->cardbase, cmd, R10, CRCPS);
1136         /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1137         wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1138     }
1139 
1140     /* Null out SDLC start address */
1141     wrtscc(lp->cardbase, cmd, R6, 0);
1142 
1143     /* SDLC flag */
1144     wrtscc(lp->cardbase, cmd, R7, FLAG);
1145 
1146     /* Set up the Transmitter but don't enable it
1147      *  DTR, 8 bit TX chars only
1148      */
1149     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1150 
1151     /* Receiver initial setup */
1152     wrtscc(lp->cardbase, cmd, R3, Rx8); /* 8 bits/char */
1153 
1154     /* Setting up BRG now - turn it off first */
1155     wrtscc(lp->cardbase, cmd, R14, BRSRC);      /* BRG off, keep Pclk source */
1156 
1157     /* set the 32x time constant for the BRG in Receive mode */
1158 
1159     if (lp->speed) {
1160         br = lp->speed;         /* get desired speed */
1161         tc = ((lp->xtal / 32) / br) - 2;        /* calc 32X BRG divisor */
1162     } else {
1163         tc = 14;
1164     }
1165 
1166     wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
1167     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);   /* upper byte */
1168 
1169     /* Following subroutine sets up and ENABLES the receiver */
1170     rts(lp, OFF);               /* TX OFF and RX ON */
1171 
1172     if (lp->speed) {
1173         /* DPLL frm BRG, BRG src PCLK */
1174         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1175     } else {
1176         /* DPLL frm rtxc,BRG src PCLK */
1177         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1178     }
1179     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);     /* SEARCH mode, keep BRG src */
1180     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
1181 
1182     if (!(cmd & 2))             /* if channel b */
1183         wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1184 
1185     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
1186 
1187     /* Now, turn on the receiver and hunt for a flag */
1188     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1189 
1190     restore_flags(flags);
1191 }
1192 
1193 static void chipset_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1194 {
1195     int cardbase;
1196     unsigned long flags;
1197 
1198     cardbase = dev->base_addr & 0x3f0;
1199 
1200     save_flags(flags);
1201     cli();
1202     wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES); /* Hardware reset */
1203     /* Disable interrupts with master interrupt ctrl reg */
1204     wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1205     restore_flags(flags);
1206 
1207 }
1208 
1209 
1210 unsigned long pi_init(unsigned long mem_start, unsigned long mem_end)
     /* [previous][next][first][last][top][bottom][index][help] */
1211 {
1212     int *port;
1213     int ioaddr = 0;
1214     int card_type = 0;
1215     int ports[] =
1216     {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1217 
1218     printk(version);
1219 
1220     /* Only one card supported for now */
1221     for (port = &ports[0]; *port && !card_type; port++) {
1222         ioaddr = *port;
1223 
1224         if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1225             printk("PI: Probing for card at address %#3x\n",ioaddr);
1226             card_type = hw_probe(ioaddr);
1227         }
1228     }
1229 
1230     switch (card_type) {
1231     case 1:
1232         printk("PI: Found a PI card at address %#3x\n", ioaddr);
1233         break;
1234     case 2:
1235         printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1236         break;
1237     default:
1238         printk("PI: ERROR: No card found\n");
1239         return mem_start;
1240     }
1241 
1242     /* Link a couple of device structures into the chain */
1243     /* For the A port */
1244     /* Allocate space for 4 buffers even though we only need 3,
1245        because one of them may cross a DMA page boundary and
1246        be rejected by get_dma_buffer().
1247     */
1248     register_netdev(&pi0a);
1249     
1250     pi0a.priv=(void *)mem_start;
1251     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1252                          + 8;   /* for alignment */
1253                         
1254     pi0a.dma = PI_DMA;
1255     pi0a.base_addr = ioaddr + 2;
1256     pi0a.irq = 0;
1257 
1258     /* And the B port */
1259     register_netdev(&pi0b);
1260     pi0b.base_addr = ioaddr;
1261     pi0b.irq = 0;
1262     pi0b.priv=(void *)mem_start;
1263     mem_start+=sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4
1264                          + 8;   /* for alignment */
1265 
1266     /* Now initialize them */
1267     pi_probe(&pi0a, card_type);
1268     pi_probe(&pi0b, card_type);
1269 
1270     pi0b.irq = pi0a.irq;        /* IRQ is shared */
1271     
1272     return mem_start;
1273 }
1274 
1275 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
     /* [previous][next][first][last][top][bottom][index][help] */
1276 {
1277     if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1278         return 1;
1279     else
1280         return 0;
1281 }
1282 
1283 static int pi_set_mac_address(struct device *dev, void *addr)
     /* [previous][next][first][last][top][bottom][index][help] */
1284 {
1285     memcpy(dev->dev_addr, addr, 7);     /* addr is an AX.25 shifted ASCII */
1286     return 0;                   /* mac address */
1287 }
1288 
1289 /* Allocate a buffer which does not cross a DMA page boundary */
1290 static char *
1291 get_dma_buffer(unsigned long *mem_ptr)
     /* [previous][next][first][last][top][bottom][index][help] */
1292 {
1293     char *ret;
1294 
1295     ret = (char *)*mem_ptr;
1296 
1297     if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1298         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1299         ret = (char *)*mem_ptr;
1300     }
1301     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1302     return (ret);
1303 }
1304 
1305 static int pi_probe(struct device *dev, int card_type)
     /* [previous][next][first][last][top][bottom][index][help] */
1306 {
1307     short ioaddr;
1308     struct pi_local *lp;
1309     int i;
1310     unsigned long flags;
1311     unsigned long mem_ptr;
1312 
1313     ioaddr = dev->base_addr;
1314 
1315     /* Initialize the device structure. */
1316     /* Must be done before chipset_init */
1317     /* Make certain the data structures used by the PI2 are aligned. */
1318     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1319     lp = (struct pi_local *) dev->priv;
1320 
1321     memset(dev->priv, 0, sizeof(struct pi_local));
1322 
1323     /* Allocate some buffers which do not cross DMA page boundaries */
1324     mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1325     lp->txdmabuf = get_dma_buffer(&mem_ptr);
1326     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1327     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1328 
1329     /* Initialize rx buffer */
1330     lp->rcvbuf = lp->rxdmabuf1;
1331     lp->rcp = lp->rcvbuf->data;
1332     lp->rcvbuf->cnt = 0;
1333 
1334     /* Initialize the transmit queue head structure */
1335     skb_queue_head_init(&lp->sndq);
1336 
1337     /* These need to be initialized before scc_init is called. */
1338     if (card_type == 1)
1339         lp->xtal = (unsigned long) SINGLE / 2;
1340     else
1341         lp->xtal = (unsigned long) DOUBLE / 2;
1342     lp->base = dev->base_addr;
1343     lp->cardbase = dev->base_addr & 0x3f0;
1344     if (dev->base_addr & CHANA) {
1345         lp->speed = DEF_A_SPEED;
1346         /* default channel access Params */
1347         lp->txdelay = DEF_A_TXDELAY;
1348         lp->persist = DEF_A_PERSIST;
1349         lp->slotime = DEF_A_SLOTIME;
1350         lp->squeldelay = DEF_A_SQUELDELAY;
1351         lp->clockmode = DEF_A_CLOCKMODE;
1352 
1353     } else {
1354         lp->speed = DEF_B_SPEED;
1355         /* default channel access Params */
1356         lp->txdelay = DEF_B_TXDELAY;
1357         lp->persist = DEF_B_PERSIST;
1358         lp->slotime = DEF_B_SLOTIME;
1359         lp->squeldelay = DEF_B_SQUELDELAY;
1360         lp->clockmode = DEF_B_CLOCKMODE;
1361     }
1362     lp->bufsiz = DMA_BUFF_SIZE;
1363     lp->tstate = IDLE;
1364 
1365     chipset_init(dev);
1366 
1367     if (dev->base_addr & CHANA) {       /* Do these things only for the A port */
1368         /* Note that a single IRQ services 2 devices (A and B channels) */
1369 
1370         lp->dmachan = dev->dma;
1371         if (lp->dmachan < 1 || lp->dmachan > 3)
1372             printk("PI: DMA channel %d out of range\n", lp->dmachan);
1373 
1374         /* chipset_init() was already called */
1375 
1376         if (dev->irq < 2) {
1377             autoirq_setup(0);
1378             save_flags(flags);
1379             cli();
1380             wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1381             /* enable PI card interrupts */
1382             wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1383             restore_flags(flags);
1384             /* request a timer interrupt for 1 mS hence */
1385             tdelay(lp, 1);
1386             /* 20 "jiffies" should be plenty of time... */
1387             dev->irq = autoirq_report(20);
1388             if (!dev->irq) {
1389                 printk(". Failed to detect IRQ line.\n");
1390             }
1391             save_flags(flags);
1392             cli();
1393             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);     /* Hardware reset */
1394             /* Disable interrupts with master interrupt ctrl reg */
1395             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1396             restore_flags(flags);
1397         }
1398 
1399         printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1400                dev->irq, dev->dma);
1401 
1402         /* This board has jumpered interrupts. Snarf the interrupt vector
1403                    now.  There is no point in waiting since no other device can use
1404                    the interrupt, and this marks the 'irqaction' as busy. */
1405         {
1406             int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1407             if (irqval) {
1408                 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1409                        dev->irq, irqval);
1410                 return EAGAIN;
1411             }
1412         }
1413 
1414         /* Grab the region */
1415         snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1416 
1417 
1418     }                           /* Only for A port */
1419     dev->open = pi_open;
1420     dev->stop = pi_close;
1421     dev->do_ioctl = pi_ioctl;
1422     dev->hard_start_xmit = pi_send_packet;
1423     dev->get_stats = pi_get_stats;
1424 
1425     /* Fill in the fields of the device structure */
1426     for (i = 0; i < DEV_NUMBUFFS; i++)
1427         skb_queue_head_init(&dev->buffs[i]);
1428 
1429 
1430     dev->hard_header = pi_header;
1431     dev->rebuild_header = pi_rebuild_header;
1432     dev->set_mac_address = pi_set_mac_address;
1433 
1434     dev->type = ARPHRD_AX25;                    /* AF_AX25 device */
1435     dev->hard_header_len = 73;                  /* We do digipeaters now */
1436     dev->mtu = 1500;                            /* eth_mtu is the default */
1437     dev->addr_len = 7;                          /* sizeof an ax.25 address */
1438     memcpy(dev->broadcast, ax25_bcast, 7);
1439     memcpy(dev->dev_addr, ax25_test, 7);
1440 
1441     /* New-style flags. */
1442     dev->flags = 0;
1443     dev->family = AF_INET;
1444     dev->pa_addr = 0;
1445     dev->pa_brdaddr = 0;
1446     dev->pa_mask = 0;
1447     dev->pa_alen = 4;
1448 
1449     return 0;
1450 }
1451 
1452 /* Open/initialize the board.  This is called (in the current kernel)
1453    sometime after booting when the 'ifconfig' program is run.
1454 
1455    This routine should set everything up anew at each open, even
1456    registers that "should" only need to be set once at boot, so that
1457    there is non-reboot way to recover if something goes wrong.
1458    */
1459 static int pi_open(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1460 {
1461     unsigned long flags;
1462     static first_time = 1;
1463 
1464     struct pi_local *lp = (struct pi_local *) dev->priv;
1465 
1466     if (dev->base_addr & 2) {   /* if A channel */
1467         if (first_time) {
1468             if (request_dma(dev->dma,"pi2")) {
1469                 free_irq(dev->irq);
1470                 return -EAGAIN;
1471             }
1472             irq2dev_map[dev->irq] = dev;
1473         }
1474         /* Reset the hardware here. */
1475         chipset_init(dev);
1476     }
1477     lp->tstate = IDLE;
1478 
1479     if (dev->base_addr & 2) {   /* if A channel */
1480         scc_init(dev);          /* Called once for each channel */
1481         scc_init(dev->next);
1482     }
1483     /* master interrupt enable */
1484     save_flags(flags);
1485     cli();
1486     wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1487     restore_flags(flags);
1488 
1489     lp->open_time = jiffies;
1490 
1491     dev->tbusy = 0;
1492     dev->interrupt = 0;
1493     dev->start = 1;
1494     first_time = 0;
1495     return 0;
1496 }
1497 
1498 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1499 {
1500     struct pi_local *lp = (struct pi_local *) dev->priv;
1501 
1502     /* If some higher layer thinks we've missed an tx-done interrupt
1503            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
1504            itself. */
1505     if (skb == NULL) {
1506         dev_tint(dev);
1507         return 0;
1508     }
1509     hardware_send_packet(lp, skb);
1510     dev->trans_start = jiffies;
1511 
1512     return 0;
1513 }
1514 
1515 /* The typical workload of the driver:
1516    Handle the network interface interrupts. */
1517 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
1518 {
1519 /*    int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1520     struct pi_local *lp;
1521     int st;
1522     unsigned long flags;
1523 
1524 /*    dev_b = dev_a->next;       Relies on the order defined in Space.c */
1525 
1526 #if 0
1527     if (dev_a == NULL) {
1528         printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1529         return;
1530     }
1531 #endif    
1532     /* Read interrupt status register (only valid from channel A)
1533      * Process all pending interrupts in while loop
1534      */
1535     lp = (struct pi_local *) pi0a.priv; /* Assume channel A */
1536     while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1537         if (st & CHBTxIP) {
1538             /* Channel B Transmit Int Pending */
1539             lp = (struct pi_local *) pi0b.priv;
1540             b_txint(lp);
1541         } else if (st & CHARxIP) {
1542             /* Channel A Rcv Interrupt Pending */
1543             lp = (struct pi_local *) pi0a.priv;
1544             a_rxint(&pi0a, lp);
1545         } else if (st & CHATxIP) {
1546             /* Channel A Transmit Int Pending */
1547             lp = (struct pi_local *) pi0a.priv;
1548             a_txint(lp);
1549         } else if (st & CHAEXT) {
1550             /* Channel A External Status Int */
1551             lp = (struct pi_local *) pi0a.priv;
1552             a_exint(lp);
1553         } else if (st & CHBRxIP) {
1554             /* Channel B Rcv Interrupt Pending */
1555             lp = (struct pi_local *) pi0b.priv;
1556             b_rxint(&pi0b, lp);
1557         } else if (st & CHBEXT) {
1558             /* Channel B External Status Int */
1559             lp = (struct pi_local *) pi0b.priv;
1560             b_exint(lp);
1561         }
1562         /* Reset highest interrupt under service */
1563         save_flags(flags);
1564         cli();
1565         wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1566         restore_flags(flags);
1567     }                           /* End of while loop on int processing */
1568     return;
1569 }
1570 
1571 /* The inverse routine to pi_open(). */
1572 static int pi_close(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1573 {
1574     unsigned long flags;
1575     struct pi_local *lp;
1576     struct sk_buff *ptr;
1577 
1578     save_flags(flags);
1579     cli();
1580 
1581     lp = (struct pi_local *) dev->priv;
1582     ptr = NULL;
1583 
1584     chipset_init(dev);          /* reset the scc */
1585     disable_dma(lp->dmachan);
1586 
1587     lp->open_time = 0;
1588 
1589     dev->tbusy = 1;
1590     dev->start = 0;
1591 
1592     /* Free any buffers left in the hardware transmit queue */
1593     while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1594         free_p(ptr);
1595 
1596     restore_flags(flags);
1597     return 0;
1598 }
1599 
1600 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /* [previous][next][first][last][top][bottom][index][help] */
1601 {
1602     unsigned long flags;
1603     struct pi_req rq;
1604     struct pi_local *lp = (struct pi_local *) dev->priv;
1605 
1606     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1607     if (ret)
1608         return ret;
1609         
1610     if(cmd!=SIOCDEVPRIVATE)
1611         return -EINVAL;
1612 
1613     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1614 
1615     switch (rq.cmd) {
1616     case SIOCSPIPARAM:
1617 
1618         if (!suser())
1619             return -EPERM;
1620         save_flags(flags);
1621         cli();
1622         lp->txdelay = rq.txdelay;
1623         lp->persist = rq.persist;
1624         lp->slotime = rq.slotime;
1625         lp->squeldelay = rq.squeldelay;
1626         lp->clockmode = rq.clockmode;
1627         lp->speed = rq.speed;
1628         pi_open(&pi0a); /* both channels get reset %%% */
1629         restore_flags(flags);
1630         ret = 0;
1631         break;
1632 
1633     case SIOCSPIDMA:
1634 
1635         if (!suser())
1636             return -EPERM;
1637         ret = 0;
1638         if (dev->base_addr & 2) {   /* if A channel */
1639            if (rq.dmachan < 1 || rq.dmachan > 3)
1640                 return -EINVAL;
1641            save_flags(flags);
1642            cli();
1643            pi_close(dev);
1644            free_dma(lp->dmachan);
1645            dev->dma = lp->dmachan = rq.dmachan;
1646            if (request_dma(lp->dmachan,"pi2")) 
1647                 ret = -EAGAIN;
1648            pi_open(dev);
1649            restore_flags(flags);
1650         }
1651         break;
1652 
1653     case SIOCSPIIRQ:
1654         ret = -EINVAL;      /* add this later */
1655         break;
1656 
1657     case SIOCGPIPARAM:
1658     case SIOCGPIDMA:
1659     case SIOCGPIIRQ:
1660 
1661         rq.speed = lp->speed;
1662         rq.txdelay = lp->txdelay;
1663         rq.persist = lp->persist;
1664         rq.slotime = lp->slotime;
1665         rq.squeldelay = lp->squeldelay;
1666         rq.clockmode = lp->clockmode;
1667         rq.dmachan = lp->dmachan;
1668         rq.irq = dev->irq;
1669         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1670         ret = 0;
1671         break;
1672 
1673     default:
1674         ret = -EINVAL;
1675     }
1676     return ret;
1677 }
1678 
1679 /* Get the current statistics.  This may be called with the card open or
1680    closed. */
1681 static struct netstats *
1682  pi_get_stats(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1683 {
1684     struct pi_local *lp = (struct pi_local *) dev->priv;
1685 
1686     return &lp->stats;
1687 }
1688 
1689 
1690 /*
1691  * Local variables:
1692  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1693  *  version-control: t
1694  *  kept-new-versions: 5
1695  *  tab-width: 4
1696  * End:
1697  */

/* [previous][next][first][last][top][bottom][index][help] */