root/drivers/net/pi2.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. pi0_preprobe
  2. random
  3. wrtscc
  4. rdscc
  5. switchbuffers
  6. hardware_send_packet
  7. setup_rx_dma
  8. setup_tx_dma
  9. tdelay
  10. free_p
  11. a_txint
  12. a_exint
  13. a_rxint
  14. b_rxint
  15. b_txint
  16. b_exint
  17. hw_probe
  18. rts
  19. pi_header
  20. pi_rebuild_header
  21. scc_init
  22. chipset_init
  23. pi_init
  24. valid_dma_page
  25. pi_set_mac_address
  26. get_dma_buffer
  27. pi_probe
  28. pi_open
  29. pi_send_packet
  30. pi_interrupt
  31. pi_close
  32. pi_ioctl
  33. pi_get_stats

   1 /*
   2    pi2.c: Driver for the Ottawa Amateur Radio Club PI and PI2 interface.
   3    Copyright (c) 1994 David Perry
   4 
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License version 2, as
   7    published by the Free Software Foundation.
   8 
   9    This program is distributed in the hope that it will be useful, but
  10    WITHOUT ANY WARRANTY; without even the implied warranty of
  11    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12    General Public License for more details.
  13 
  14    You should have received a copy of the GNU General Public License
  15    along with this program; if not, write to the Free Software Foundation,
  16    Inc., 675 Mass Ave, Cambridge MA 02139, USA.
  17 
  18    The file skeleton.c by Donald Becker was used as a starting point
  19    for this driver.
  20 
  21    Revision History
  22 
  23    April 6, 1994  (dp) Created
  24                        version 0.0 ALPHA
  25    April 10, 1994 (dp) Included cleanup, suggestions from J. P. Morrison.
  26                        version 0.1 ALPHA
  27    April 13, 1994 (dp) Included address probing from JPM, autoirq
  28                        version 0.2 ALPHA
  29    April 14, 1994 (ac) Sketched in the NET3 changes.
  30    April 17, 1994 (dp) Finished the NET3 changes. Used init_etherdev()
  31                        instead of kmalloc() to ensure that DMA buffers will
  32                        reside under the 16 meg line.
  33                        version 0.4 ALPHA
  34    April 18, 1994 (dp) Now using the kernel provided sk_buff handling functions.
  35                        Fixed a nasty problem with DMA.
  36                        version 0.5 ALPHA
  37    June 6, 1994 (ac)   Fixed to match the buffer locking changes. Added a hack to
  38                        fix a funny I see (search for HACK) and fixed the calls in
  39                        init() so it doesn't migrate module based ethernet cards up
  40                        to eth2 Took out the old module ideas as they are no longer
  41                        relevant to the PI driver.
  42    July 16, 1994 (dp)  Fixed the B channel rx overrun problem ac referred to 
  43                        above. Also added a bit of a hack to improve the maximum
  44                        baud rate on the B channel (Search for STUFF2). Included
  45                        ioctl stuff from John Paul Morrison. version 0.6 ALPHA
  46    Feb 9, 1995 (dp)    Updated for 1.1.90 kernel
  47                        version 0.7 ALPHA
  48    Apr 6, 1995 (ac)    Tweaks for NET3 pre snapshot 002 AX.25
  49    April 23, 1995 (dp) Fixed ioctl so it works properly with piconfig program
  50                        when changing the baud rate or clock mode.
  51                        version 0.8 ALPHA
  52    July 17, 1995 (ac)  Finally polishing of AX25.030+ support
  53          
  54 */
  55 
  56 /* The following #define invokes a hack that will improve performance (baud)
  57    for the B port. The up side is it makes 9600 baud work ok on the B port.
  58    It may do 38400, depending on the host. The down side is it burns up
  59    CPU cycles with ints locked for up to 1 character time, at the beginning
  60    of each transmitted packet. If this causes you to lose sleep, #undefine it.
  61 */
  62 
  63 /*#define STUFF2 1*/
  64 
  65 /* The default configuration */
  66 #define PI_DMA 3
  67 
  68 #define DEF_A_SPEED 0           /* 0 means external clock */
  69 #define DEF_A_TXDELAY 15        /* 15 mS transmit delay */
  70 #define DEF_A_PERSIST 128       /* 50% persistence */
  71 #define DEF_A_SLOTIME 15        /* 15 mS slot time */
  72 #define DEF_A_SQUELDELAY 1      /* 1 mS squelch delay - allows fcs and flag */
  73 #define DEF_A_CLOCKMODE 0       /* clock mode - 0 is normal */
  74 
  75 #define DEF_B_SPEED 1200        /* 1200 baud */
  76 #define DEF_B_TXDELAY 40        /* 400 mS */
  77 #define DEF_B_PERSIST 128       /* 50% */
  78 #define DEF_B_SLOTIME 30        /* 300 mS */
  79 #define DEF_B_SQUELDELAY 3      /* 30 mS */
  80 #define DEF_B_CLOCKMODE 0       /* Normal clock mode */
  81 
  82 static const char *version =
  83 "PI: V0.8 ALPHA April 23 1995 David Perry (dp@hydra.carleton.ca)\n";
  84 
  85 /* The following #define is only really required for the PI card, not
  86    the PI2 - but it's safer to leave it in. */
  87 #define REALLY_SLOW_IO 1
  88 
  89 #define PI2_MODULE 0
  90 
  91 #if PI2_MODULE > 0
  92 #include <linux/modules.h>
  93 #endif
  94 
  95 #include <linux/config.h>
  96 #include <linux/kernel.h>
  97 #include <linux/sched.h>
  98 #include <linux/types.h>
  99 #include <linux/fcntl.h>
 100 #include <linux/interrupt.h>
 101 #include <linux/ptrace.h>
 102 #include <linux/ioport.h>
 103 #include <linux/in.h>
 104 #include <linux/malloc.h>
 105 #include <linux/string.h>
 106 #include <linux/errno.h>
 107 #include <asm/system.h>
 108 #include <asm/bitops.h>
 109 #include <asm/io.h>
 110 #include <asm/dma.h>
 111 #include <asm/segment.h>
 112 #include <linux/inet.h>
 113 #include <linux/netdevice.h>
 114 #include <linux/etherdevice.h>
 115 #include <linux/skbuff.h>
 116 #include <linux/timer.h>
 117 #include <linux/if_arp.h>
 118 #include "pi2.h"
 119 #include "z8530.h"
 120 #include <net/ax25.h>
 121 
 122 
 123 struct mbuf {
 124     struct mbuf *next;
 125     int cnt;
 126     char data[0];
 127 };
 128 
 129 /*
 130  *      The actual devices we will use
 131  */
 132  
 133 /*
 134  *      PI device declarations.
 135  */
 136  
 137 static int pi0_preprobe(struct device *dev){return 0;}  /* Dummy probe function */
     /* [previous][next][first][last][top][bottom][index][help] */
 138 static struct device pi0a = { "pi0a", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 139 static struct device pi0b = { "pi0b", 0, 0, 0, 0, 0, 0, 0, 0, 0, NULL, pi0_preprobe };
 140 
 141  
 142 /* The number of low I/O ports used by the card. */
 143 #define PI_TOTAL_SIZE   8
 144 
 145 
 146 /* Index to functions, as function prototypes. */
 147 
 148 static int pi_probe(struct device *dev, int card_type);
 149 static int pi_open(struct device *dev);
 150 static int pi_send_packet(struct sk_buff *skb, struct device *dev);
 151 static void pi_interrupt(int reg_ptr, struct pt_regs *regs);
 152 static int pi_close(struct device *dev);
 153 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd);
 154 static struct enet_statistics *pi_get_stats(struct device *dev);
 155 static void rts(struct pi_local *lp, int x);
 156 static void b_rxint(struct device *dev, struct pi_local *lp);
 157 static void b_txint(struct pi_local *lp);
 158 static void b_exint(struct pi_local *lp);
 159 static void a_rxint(struct device *dev, struct pi_local *lp);
 160 static void a_txint(struct pi_local *lp);
 161 static void a_exint(struct pi_local *lp);
 162 static char *get_dma_buffer(unsigned long *mem_ptr);
 163 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize);
 164 
 165 static char ax25_bcast[7] =
 166 {'Q' << 1, 'S' << 1, 'T' << 1, ' ' << 1, ' ' << 1, ' ' << 1, '0' << 1};
 167 static char ax25_test[7] =
 168 {'L' << 1, 'I' << 1, 'N' << 1, 'U' << 1, 'X' << 1, ' ' << 1, '1' << 1};
 169 
 170 static int ext2_secrm_seed = 152;       /* Random generator base */
 171 
 172 static inline unsigned char random(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 173 {
 174     return (unsigned char) (ext2_secrm_seed = ext2_secrm_seed
 175                             * 69069l + 1);
 176 }
 177 
 178 static inline void wrtscc(int cbase, int ctl, int sccreg, int val)
     /* [previous][next][first][last][top][bottom][index][help] */
 179 {
 180     /* assume caller disables interrupts! */
 181     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 182     outb_p(sccreg, ctl);        /* Select register */
 183     outb_p(val, ctl);           /* Output value */
 184     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 185 }
 186 
 187 static inline int rdscc(int cbase, int ctl, int sccreg)
     /* [previous][next][first][last][top][bottom][index][help] */
 188 {
 189     int retval;
 190 
 191     /* assume caller disables interrupts! */
 192     outb_p(0, cbase + DMAEN);   /* Disable DMA while we touch the scc */
 193     outb_p(sccreg, ctl);        /* Select register */
 194     retval = inb_p(ctl);
 195     outb_p(1, cbase + DMAEN);   /* Enable DMA */
 196     return retval;
 197 }
 198 
 199 static void switchbuffers(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 200 {
 201     if (lp->rcvbuf == lp->rxdmabuf1)
 202         lp->rcvbuf = lp->rxdmabuf2;
 203     else
 204         lp->rcvbuf = lp->rxdmabuf1;
 205 }
 206 
 207 static void hardware_send_packet(struct pi_local *lp, struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 208 {
 209     char kickflag;
 210     unsigned long flags;
 211 
 212     lp->stats.tx_packets++;
 213 
 214     save_flags(flags);
 215     cli();
 216     kickflag = (skb_peek(&lp->sndq) == NULL) && (lp->sndbuf == NULL);
 217     restore_flags(flags);
 218 
 219     skb_queue_tail(&lp->sndq, skb);
 220     if (kickflag) {
 221         /* simulate interrupt to xmit */
 222         switch (lp->base & 2) {
 223         case 2:
 224             a_txint(lp);        /* process interrupt */
 225             break;
 226         case 0:
 227             save_flags(flags);
 228             cli();
 229             if (lp->tstate == IDLE)
 230                 b_txint(lp);
 231             restore_flags(flags);
 232             break;
 233         }
 234     }
 235 }
 236 
 237 static void setup_rx_dma(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 238 {
 239     unsigned long flags;
 240     int cmd;
 241     unsigned long dma_abs;
 242     unsigned dmachan;
 243 
 244     save_flags(flags);
 245     cli();
 246 
 247     dma_abs = (unsigned long) (lp->rcvbuf->data);
 248     dmachan = lp->dmachan;
 249     cmd = lp->base + CTL;
 250 
 251     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 252         panic("PI: RX buffer violates DMA boundary!");
 253 
 254     /* Get ready for RX DMA */
 255     wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 256 
 257     disable_dma(dmachan);
 258     clear_dma_ff(dmachan);
 259 
 260     /* Set DMA mode register to single transfers, incrementing address,
 261      *  auto init, writes
 262      */
 263     set_dma_mode(dmachan, DMA_MODE_READ | 0x10);
 264     set_dma_addr(dmachan, dma_abs);
 265     set_dma_count(dmachan, lp->bufsiz);
 266     enable_dma(dmachan);
 267 
 268     /* If a packet is already coming in, this line is supposed to
 269            avoid receiving a partial packet.
 270      */
 271     wrtscc(lp->cardbase, cmd, R0, RES_Rx_CRC);
 272 
 273     /* Enable RX dma */
 274     wrtscc(lp->cardbase, cmd, R1,
 275       WT_RDY_ENAB | WT_FN_RDYFN | WT_RDY_RT | INT_ERR_Rx | EXT_INT_ENAB);
 276 
 277     restore_flags(flags);
 278 }
 279 
 280 static void setup_tx_dma(struct pi_local *lp, int length)
     /* [previous][next][first][last][top][bottom][index][help] */
 281 {
 282     unsigned long dma_abs;
 283     unsigned long flags;
 284     unsigned long dmachan;
 285 
 286     save_flags(flags);
 287     cli();
 288 
 289     dmachan = lp->dmachan;
 290     dma_abs = (unsigned long) (lp->txdmabuf);
 291 
 292     if(!valid_dma_page(dma_abs, DMA_BUFF_SIZE + sizeof(struct mbuf)))
 293         panic("PI: TX buffer violates DMA boundary!");
 294 
 295     disable_dma(dmachan);
 296     /* Set DMA mode register to single transfers, incrementing address,
 297      *  no auto init, reads
 298      */
 299     set_dma_mode(dmachan, DMA_MODE_WRITE);
 300     clear_dma_ff(dmachan);
 301     set_dma_addr(dmachan, dma_abs);
 302     /* output byte count */
 303     set_dma_count(dmachan, length);
 304 
 305     restore_flags(flags);
 306 }
 307 
 308 static void tdelay(struct pi_local *lp, int time)
     /* [previous][next][first][last][top][bottom][index][help] */
 309 {
 310     int port;
 311     unsigned int t1;
 312     unsigned char sc;
 313 
 314     if (lp->base & 2) {         /* If A channel */
 315         sc = SC1;
 316         t1 = time;
 317         port = lp->cardbase + TMR1;
 318     } else {
 319         sc = SC2;
 320         t1 = 10 * time;         /* 10s of milliseconds for the B channel */
 321         port = lp->cardbase + TMR2;
 322         wrtscc(lp->cardbase, lp->base + CTL, R1, INT_ALL_Rx | EXT_INT_ENAB);
 323     }
 324 
 325     /* Setup timer sc */
 326     outb_p(sc | LSB_MSB | MODE0, lp->cardbase + TMRCMD);
 327 
 328     /* times 2 to make millisecs */
 329     outb_p((t1 << 1) & 0xFF, port);
 330     outb_p((t1 >> 7) & 0xFF, port);
 331 
 332     /* Enable correct int for timeout */
 333     wrtscc(lp->cardbase, lp->base + CTL, R15, CTSIE);
 334     wrtscc(lp->cardbase, lp->base + CTL, R0, RES_EXT_INT);
 335 }
 336 
 337 static void free_p(struct sk_buff *skb)
     /* [previous][next][first][last][top][bottom][index][help] */
 338 {
 339         dev_kfree_skb(skb, FREE_WRITE);
 340 }
 341 
 342 static void a_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 343 {
 344     int cmd;
 345     unsigned long flags;
 346 
 347     save_flags(flags);
 348     cli();
 349 
 350     cmd = CTL + lp->base;
 351 
 352     switch (lp->tstate) {
 353     case IDLE:
 354         /* Transmitter idle. Find a frame for transmission */
 355         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 356             rts(lp, OFF);
 357             restore_flags(flags);
 358             return;
 359         }
 360         /* If a buffer to send, we drop thru here */
 361     case DEFER:
 362         /* we may have deferred prev xmit attempt */
 363         /* Check DCD - debounce it
 364          * See Intel Microcommunications Handbook, p2-308
 365          */
 366         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 367         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 368         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 369             lp->tstate = DEFER;
 370             tdelay(lp, 100);
 371             /* defer until DCD transition or timeout */
 372             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 373             restore_flags(flags);
 374             return;
 375         }
 376         if (random() > lp->persist) {
 377             lp->tstate = DEFER;
 378             tdelay(lp, lp->slotime);
 379             restore_flags(flags);
 380             return;
 381         }
 382         /* Assert RTS early minimize collision window */
 383         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 384         rts(lp, ON);            /* Transmitter on */
 385         lp->tstate = ST_TXDELAY;
 386         tdelay(lp, lp->txdelay);
 387         restore_flags(flags);
 388         return;
 389     default:
 390         break;
 391     }                           /* end switch(lp->state) */
 392 
 393     restore_flags(flags);
 394 }                               /*a_txint */
 395 
 396 static void a_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 397 {
 398     unsigned long flags;
 399     int cmd;
 400     char st;
 401     int length;
 402 
 403     save_flags(flags);
 404     cli();                      /* disable interrupts */
 405 
 406     st = rdscc(lp->cardbase, lp->base + CTL, R0);       /* Fetch status */
 407 
 408     /* reset external status latch */
 409     wrtscc(lp->cardbase, CTL + lp->base, R0, RES_EXT_INT);
 410     cmd = lp->base + CTL;
 411 
 412     if ((lp->rstate >= ACTIVE) && (st & BRK_ABRT)) {
 413         setup_rx_dma(lp);
 414         lp->rstate = ACTIVE;
 415     }
 416     switch (lp->tstate) {
 417     case ACTIVE:
 418         free_p(lp->sndbuf);
 419         lp->sndbuf = NULL;
 420         lp->tstate = FLAGOUT;
 421         tdelay(lp, lp->squeldelay);
 422         break;
 423     case FLAGOUT:
 424         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 425             /* Nothing to send - return to receive mode */
 426             lp->tstate = IDLE;
 427             rts(lp, OFF);
 428             restore_flags(flags);
 429             return;
 430         }
 431         /* NOTE - fall through if more to send */
 432     case ST_TXDELAY:
 433         /* Disable DMA chan */
 434         disable_dma(lp->dmachan);
 435 
 436         /* Set up for TX dma */
 437         wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
 438 
 439 
 440         /* Get all chars */
 441         /* Strip KISS control byte */
 442         length = lp->sndbuf->len - 1;
 443         memcpy(lp->txdmabuf, &lp->sndbuf->data[1], length);
 444 
 445 
 446         /* Setup DMA controller for tx */
 447         setup_tx_dma(lp, length);
 448 
 449         /* select transmit interrupts to enable */
 450         /* Allow DMA on chan */
 451         enable_dma(lp->dmachan);
 452 
 453         /* reset CRC, Txint pend*/
 454         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC | RES_Tx_P);
 455 
 456         /* allow Underrun int only */
 457         wrtscc(lp->cardbase, cmd, R15, TxUIE);
 458 
 459         /* Enable TX DMA */
 460         wrtscc(lp->cardbase, cmd, R1, WT_RDY_ENAB | WT_FN_RDYFN | EXT_INT_ENAB);
 461 
 462         /* Send CRC on underrun */
 463         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);
 464 
 465 
 466         /* packet going out now */
 467         lp->tstate = ACTIVE;
 468         break;
 469     case DEFER:
 470         /* we have deferred prev xmit attempt
 471          * See Intel Microcommunications Handbook, p2-308
 472          */
 473         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 474         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 475         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 476             lp->tstate = DEFER;
 477             tdelay(lp, 100);
 478             /* Defer until dcd transition or 100mS timeout */
 479             wrtscc(lp->cardbase, CTL + lp->base, R15, CTSIE | DCDIE);
 480             restore_flags(flags);
 481             return;
 482         }
 483         if (random() > lp->persist) {
 484             lp->tstate = DEFER;
 485             tdelay(lp, lp->slotime);
 486             restore_flags(flags);
 487             return;
 488         }
 489         /* Assert RTS early minimize collision window */
 490         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | Tx8);
 491         rts(lp, ON);            /* Transmitter on */
 492         lp->tstate = ST_TXDELAY;
 493         tdelay(lp, lp->txdelay);
 494         restore_flags(flags);
 495         return;
 496     }                           /* switch(lp->tstate) */
 497 
 498     restore_flags(flags);
 499 }                               /* a_exint() */
 500 
 501 /* Receive interrupt handler for the A channel
 502  */
 503 static void a_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 504 {
 505     unsigned long flags;
 506     int cmd;
 507     int bytecount;
 508     char rse;
 509     struct sk_buff *skb;
 510     int sksize, pkt_len;
 511     struct mbuf *cur_buf;
 512     unsigned char *cfix;
 513 
 514     save_flags(flags);
 515     cli();                      /* disable interrupts */
 516     cmd = lp->base + CTL;
 517 
 518     rse = rdscc(lp->cardbase, cmd, R1); /* Get special condition bits from R1 */
 519     if (rse & Rx_OVR)
 520         lp->rstate = RXERROR;
 521 
 522     if (rse & END_FR) {
 523         /* If end of frame */
 524         /* figure length of frame from 8237 */
 525         clear_dma_ff(lp->dmachan);
 526         bytecount = lp->bufsiz - get_dma_residue(lp->dmachan);
 527 
 528         if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (bytecount < 10)) {
 529             if ((bytecount >= 10) && (rse & CRC_ERR)) {
 530                 lp->stats.rx_crc_errors++;
 531             }
 532             if (lp->rstate == RXERROR) {
 533                 lp->stats.rx_errors++;
 534                 lp->stats.rx_over_errors++;
 535             }
 536             /* Reset buffer pointers */
 537             lp->rstate = ACTIVE;
 538             setup_rx_dma(lp);
 539         } else {
 540             /* Here we have a valid frame */
 541             /* Toss 2 crc bytes , add one for KISS */
 542             pkt_len = lp->rcvbuf->cnt = bytecount - 2 + 1;
 543 
 544             /* Get buffer for next frame */
 545             cur_buf = lp->rcvbuf;
 546             switchbuffers(lp);
 547             setup_rx_dma(lp);
 548 
 549 
 550             /* Malloc up new buffer. */
 551             sksize = pkt_len;
 552 
 553             skb = dev_alloc_skb(sksize);
 554             if (skb == NULL) {
 555                 printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 556                 lp->stats.rx_dropped++;
 557                 restore_flags(flags);
 558                 return;
 559             }
 560             skb->dev = dev;
 561 
 562             /* KISS kludge -  prefix with a 0 byte */
 563             cfix=skb_put(skb,pkt_len);
 564             *cfix++=0;
 565             /* 'skb->data' points to the start of sk_buff data area. */
 566             memcpy(cfix, (char *) cur_buf->data,
 567                    pkt_len - 1);
 568             skb->protocol=htons(ETH_P_AX25);
 569             skb->mac.raw=skb->data;
 570             IS_SKB(skb);
 571             netif_rx(skb);
 572             lp->stats.rx_packets++;
 573         }                       /* end good frame */
 574     }                           /* end EOF check */
 575     wrtscc(lp->cardbase, lp->base + CTL, R0, ERR_RES);  /* error reset */
 576     restore_flags(flags);
 577 }
 578 
 579 static void b_rxint(struct device *dev, struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 580 {
 581     unsigned long flags;
 582     int cmd;
 583     char rse;
 584     struct sk_buff *skb;
 585     int sksize;
 586     int pkt_len;
 587     unsigned char *cfix;
 588 
 589     save_flags(flags);
 590     cli();                      /* disable interrupts */
 591     cmd = CTL + lp->base;
 592 
 593     rse = rdscc(lp->cardbase, cmd, R1); /* get status byte from R1 */
 594 
 595     if ((rdscc(lp->cardbase, cmd, R0)) & Rx_CH_AV) {
 596         /* there is a char to be stored
 597          * read special condition bits before reading the data char
 598          */
 599         if (rse & Rx_OVR) {
 600             /* Rx overrun - toss buffer */
 601             /* reset buffer pointers */
 602             lp->rcp = lp->rcvbuf->data;
 603             lp->rcvbuf->cnt = 0;
 604 
 605             lp->rstate = RXERROR;       /* set error flag */
 606             lp->stats.rx_errors++;
 607             lp->stats.rx_over_errors++;
 608         } else if (lp->rcvbuf->cnt >= lp->bufsiz) {
 609             /* Too large -- toss buffer */
 610             /* reset buffer pointers */
 611             lp->rcp = lp->rcvbuf->data;
 612             lp->rcvbuf->cnt = 0;
 613             lp->rstate = TOOBIG;/* when set, chars are not stored */
 614         }
 615         /* ok, we can store the received character now */
 616         if (lp->rstate == ACTIVE) {     /* If no errors... */
 617             *lp->rcp++ = rdscc(lp->cardbase, cmd, R8);  /* char to rcv buff */
 618             lp->rcvbuf->cnt++;  /* bump count */
 619         } else {
 620             /* got to empty FIFO */
 621             (void) rdscc(lp->cardbase, cmd, R8);
 622             wrtscc(lp->cardbase, cmd, R0, ERR_RES);     /* reset err latch */
 623             lp->rstate = ACTIVE;
 624         }
 625     }
 626     if (rse & END_FR) {
 627         /* END OF FRAME -- Make sure Rx was active */
 628         if (lp->rcvbuf->cnt > 0) {
 629             if ((rse & CRC_ERR) || (lp->rstate > ACTIVE) || (lp->rcvbuf->cnt < 10)) {
 630                 if ((lp->rcvbuf->cnt >= 10) && (rse & CRC_ERR)) {
 631                     lp->stats.rx_crc_errors++;
 632                 }
 633                 lp->rcp = lp->rcvbuf->data;
 634                 lp->rcvbuf->cnt = 0;
 635             } else {
 636                 /* Here we have a valid frame */
 637                 pkt_len = lp->rcvbuf->cnt -= 2; /* Toss 2 crc bytes */
 638                 pkt_len += 1;   /* Make room for KISS control byte */
 639 
 640                 /* Malloc up new buffer. */
 641                 sksize = pkt_len;
 642                 skb = dev_alloc_skb(sksize);
 643                 if (skb == NULL) {
 644                     printk("PI: %s: Memory squeeze, dropping packet.\n", dev->name);
 645                     lp->stats.rx_dropped++;
 646                     restore_flags(flags);
 647                     return;
 648                 }
 649                 skb->dev = dev;
 650 
 651                 /* KISS kludge -  prefix with a 0 byte */
 652                 cfix=skb_put(skb,pkt_len);
 653                 *cfix++=0;
 654                 /* 'skb->data' points to the start of sk_buff data area. */
 655                 memcpy(cfix, lp->rcvbuf->data, pkt_len - 1);
 656                 skb->protocol=ntohs(ETH_P_AX25);
 657                 skb->mac.raw=skb->data;
 658                 IS_SKB(skb);
 659                 netif_rx(skb);
 660                 lp->stats.rx_packets++;
 661                 /* packet queued - initialize buffer for next frame */
 662                 lp->rcp = lp->rcvbuf->data;
 663                 lp->rcvbuf->cnt = 0;
 664 
 665             }                   /* end good frame queued */
 666         }                       /* end check for active receive upon EOF */
 667         lp->rstate = ACTIVE;    /* and clear error status */
 668     }                           /* end EOF check */
 669     restore_flags(flags);
 670 }
 671 
 672 
 673 static void b_txint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 674 {
 675     unsigned long flags;
 676     int cmd;
 677     unsigned char c;
 678 
 679     save_flags(flags);
 680     cli();
 681     cmd = CTL + lp->base;
 682 
 683     switch (lp->tstate) {
 684     case CRCOUT:
 685         lp->tstate = FLAGOUT;
 686         tdelay(lp, lp->squeldelay);
 687         restore_flags(flags);
 688         return;
 689     case IDLE:
 690         /* Transmitter idle. Find a frame for transmission */
 691         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 692             /* Nothing to send - return to receive mode
 693              * Tx OFF now - flag should have gone
 694              */
 695             rts(lp, OFF);
 696          
 697             restore_flags(flags);
 698             return;
 699         }
 700         lp->txptr = lp->sndbuf->data;
 701         lp->txptr++;            /* Ignore KISS control byte */
 702         lp->txcnt = (int) lp->sndbuf->len - 1;
 703         /* If a buffer to send, we drop thru here */
 704     case DEFER:         /* we may have deferred prev xmit attempt */
 705         /* Check DCD - debounce it */
 706         /* See Intel Microcommunications Handbook, p2-308 */
 707         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 708         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 709         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 710             lp->tstate = DEFER;
 711             tdelay(lp, 100);
 712             /* defer until DCD transition or timeout */
 713             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 714             restore_flags(flags);
 715             return;
 716         }
 717         if (random() > lp->persist) {
 718             lp->tstate = DEFER;
 719             tdelay(lp, lp->slotime);
 720             restore_flags(flags);
 721             return;
 722         }
 723         rts(lp, ON);            /* Transmitter on */
 724         lp->tstate = ST_TXDELAY;
 725         tdelay(lp, lp->txdelay);
 726         restore_flags(flags);
 727         return;
 728 
 729     case ACTIVE:
 730         /* Here we are actively sending a frame */
 731         if (lp->txcnt--) {
 732             c = *lp->txptr++;
 733             /* next char is gone */
 734             wrtscc(lp->cardbase, cmd, R8, c);
 735             /* stuffing a char satisfies Interrupt condition */
 736         } else {
 737             /* No more to send */
 738             free_p(lp->sndbuf);
 739             lp->sndbuf = NULL;
 740             if ((rdscc(lp->cardbase, cmd, R0) & 0x40)) {
 741                 /* Did we underrun? */
 742                 /* unexpected underrun */
 743                 lp->stats.tx_errors++;
 744                 lp->stats.tx_fifo_errors++;
 745                 wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 746                 lp->tstate = FLAGOUT;
 747                 tdelay(lp, lp->squeldelay);
 748                 restore_flags(flags);
 749                 return;
 750             }
 751             lp->tstate = UNDERRUN;      /* Now we expect to underrun */
 752             /* Send flags on underrun */
 753             if (lp->speed) {    /* If internally clocked */
 754                 wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
 755             } else {
 756                 wrtscc(lp->cardbase, cmd, R10, CRCPS);
 757             }
 758             wrtscc(lp->cardbase, cmd, R0, RES_Tx_P);    /* reset Tx Int Pend */
 759         }
 760         restore_flags(flags);
 761         return;                 /* back to wait for interrupt */
 762     }                           /* end switch */
 763     restore_flags(flags);
 764 }
 765 
 766 /* Pi SIO External/Status interrupts (for the B channel)
 767  * This can be caused by a receiver abort, or a Tx UNDERRUN/EOM.
 768  * Receiver automatically goes to Hunt on an abort.
 769  *
 770  * If the Tx Underrun interrupt hits, change state and
 771  * issue a reset command for it, and return.
 772  */
 773 static void b_exint(struct pi_local *lp)
     /* [previous][next][first][last][top][bottom][index][help] */
 774 {
 775     unsigned long flags;
 776     char st;
 777     int cmd;
 778     char c;
 779 
 780     cmd = CTL + lp->base;
 781     save_flags(flags);
 782     cli();                      /* disable interrupts */
 783     st = rdscc(lp->cardbase, cmd, R0);  /* Fetch status */
 784     /* reset external status latch */
 785     wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 786 
 787 
 788     switch (lp->tstate) {
 789     case ACTIVE:                /* Unexpected underrun */
 790         free_p(lp->sndbuf);
 791         lp->sndbuf = NULL;
 792         wrtscc(lp->cardbase, cmd, R0, SEND_ABORT);
 793         lp->tstate = FLAGOUT;
 794         lp->stats.tx_errors++;
 795         lp->stats.tx_fifo_errors++;
 796         tdelay(lp, lp->squeldelay);
 797         restore_flags(flags);
 798         return;
 799     case UNDERRUN:
 800         lp->tstate = CRCOUT;
 801         restore_flags(flags);
 802         return;
 803     case FLAGOUT:
 804         /* Find a frame for transmission */
 805         if ((lp->sndbuf = skb_dequeue(&lp->sndq)) == NULL) {
 806             /* Nothing to send - return to receive mode
 807              * Tx OFF now - flag should have gone
 808              */
 809             rts(lp, OFF);
 810             lp->tstate = IDLE;
 811             restore_flags(flags);
 812             return;
 813         }
 814         lp->txptr = lp->sndbuf->data;
 815         lp->txptr++;            /* Ignore KISS control byte */
 816         lp->txcnt = (int) lp->sndbuf->len - 1;
 817         /* Get first char to send */
 818         lp->txcnt--;
 819         c = *lp->txptr++;
 820         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 821 
 822         /* Send abort on underrun */
 823         if (lp->speed) {        /* If internally clocked */
 824             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 825         } else {
 826             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 827         }
 828 
 829         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 830         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 831 
 832 #ifdef STUFF2
 833         /* stuff an extra one if we can */
 834         if (lp->txcnt) {
 835             lp->txcnt--;
 836             c = *lp->txptr++;
 837             /* Wait for tx buffer empty */
 838             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 839                 ;   
 840             wrtscc(lp->cardbase, cmd, R8, c);
 841         }
 842 #endif
 843 
 844         /* select transmit interrupts to enable */
 845 
 846         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 847         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 848         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);       /* Tx/Ext ints */
 849 
 850         lp->tstate = ACTIVE;    /* char going out now */
 851         restore_flags(flags);
 852         return;
 853 
 854     case DEFER:
 855         /* Check DCD - debounce it
 856          * See Intel Microcommunications Handbook, p2-308
 857          */
 858         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 859         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 860         if ((rdscc(lp->cardbase, cmd, R0) & DCD) != 0) {
 861             lp->tstate = DEFER;
 862             tdelay(lp, 100);
 863             /* defer until DCD transition or timeout */
 864             wrtscc(lp->cardbase, cmd, R15, CTSIE | DCDIE);
 865             restore_flags(flags);
 866             return;
 867         }
 868         if (random() > lp->persist) {
 869             lp->tstate = DEFER;
 870             tdelay(lp, lp->slotime);
 871             restore_flags(flags);
 872             return;
 873         }
 874         rts(lp, ON);            /* Transmitter on */
 875         lp->tstate = ST_TXDELAY;
 876         tdelay(lp, lp->txdelay);
 877         restore_flags(flags);
 878         return;
 879 
 880     case ST_TXDELAY:
 881 
 882         /* Get first char to send */
 883         lp->txcnt--;
 884         c = *lp->txptr++;
 885         wrtscc(lp->cardbase, cmd, R0, RES_Tx_CRC);      /* reset for next frame */
 886 
 887         /* Send abort on underrun */
 888         if (lp->speed) {        /* If internally clocked */
 889             wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI | ABUNDER);
 890         } else {
 891             wrtscc(lp->cardbase, cmd, R10, CRCPS | ABUNDER);
 892         }
 893 
 894         wrtscc(lp->cardbase, cmd, R8, c);       /* First char out now */
 895         wrtscc(lp->cardbase, cmd, R0, RES_EOM_L);       /* Reset end of message latch */
 896 
 897 #ifdef STUFF2
 898         /* stuff an extra one if we can */
 899         if (lp->txcnt) {
 900             lp->txcnt--;
 901             c = *lp->txptr++;
 902             /* Wait for tx buffer empty */
 903             while((rdscc(lp->cardbase, cmd, R0) & 0x04) == 0)
 904                 ;   
 905             wrtscc(lp->cardbase, cmd, R8, c);
 906         }
 907 #endif
 908 
 909         /* select transmit interrupts to enable */
 910 
 911         wrtscc(lp->cardbase, cmd, R15, TxUIE);  /* allow Underrun int only */
 912         wrtscc(lp->cardbase, cmd, R0, RES_EXT_INT);
 913         /* Tx/Extern ints on */
 914         wrtscc(lp->cardbase, cmd, R1, TxINT_ENAB | EXT_INT_ENAB);
 915 
 916         lp->tstate = ACTIVE;    /* char going out now */
 917         restore_flags(flags);
 918         return;
 919     }
 920 
 921     /* Receive Mode only
 922      * This triggers when hunt mode is entered, & since an ABORT
 923      * automatically enters hunt mode, we use that to clean up
 924      * any waiting garbage
 925      */
 926     if ((lp->rstate == ACTIVE) && (st & BRK_ABRT)) {
 927         (void) rdscc(lp->cardbase, cmd, R8);
 928         (void) rdscc(lp->cardbase, cmd, R8);
 929         (void) rdscc(lp->cardbase, cmd, R8);
 930         lp->rcp = lp->rcvbuf->data;
 931         lp->rcvbuf->cnt = 0;    /* rewind on DCD transition */
 932     }
 933     restore_flags(flags);
 934 }
 935 
 936 /* Probe for a PI card. */
 937 /* This routine also initializes the timer chip */
 938 
 939 static int hw_probe(int ioaddr)
     /* [previous][next][first][last][top][bottom][index][help] */
 940 {
 941     int time = 1000;            /* Number of milliseconds for test */
 942     unsigned long start_time, end_time;
 943 
 944     int base, tmr0, tmr1, tmrcmd;
 945     int a = 1;
 946     int b = 1;
 947 
 948     base = ioaddr & 0x3f0;
 949     tmr0 = TMR0 + base;
 950     tmr1 = TMR1 + base;
 951     tmrcmd = TMRCMD + base;
 952 
 953     /* Set up counter chip timer 0 for 500 uS period square wave */
 954     /* assuming a 3.68 mhz clock for now */
 955     outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 956     outb_p(922 & 0xFF, tmr0);
 957     outb_p(922 >> 8, tmr0);
 958 
 959     /* Setup timer control word for timer 1*/
 960     outb_p(SC1 | LSB_MSB | MODE0, tmrcmd);
 961     outb_p((time << 1) & 0xFF, tmr1);
 962     outb_p((time >> 7) & 0XFF, tmr1);
 963 
 964     /* wait until counter reg is loaded */
 965     do {
 966         /* Latch count for reading */
 967         outb_p(SC1, tmrcmd);
 968         a = inb_p(tmr1);
 969         b = inb_p(tmr1);
 970     } while (b == 0);
 971     start_time = jiffies;
 972     while (b != 0) {
 973         /* Latch count for reading */
 974         outb_p(SC1, tmrcmd);
 975         a = inb_p(tmr1);
 976         b = inb_p(tmr1);
 977         end_time = jiffies;
 978         /* Don't wait forever - there may be no card here */
 979         if ((end_time - start_time) > 200)
 980             return 0;           /* No card found */
 981     }
 982     end_time = jiffies;
 983     /* 87 jiffies, for a 3.68 mhz clock, half that for a double speed clock */
 984     if ((end_time - start_time) > 65) {
 985         return (1);             /* PI card found */
 986     } else {
 987         /* Faster crystal - tmr0 needs adjusting */
 988         /* Set up counter chip */
 989         /* 500 uS square wave */
 990         outb_p(SC0 | LSB_MSB | MODE3, tmrcmd);
 991         outb_p(1844 & 0xFF, tmr0);
 992         outb_p(1844 >> 8, tmr0);
 993         return (2);             /* PI2 card found */
 994     }
 995 }
 996 
 997 static void rts(struct pi_local *lp, int x)
     /* [previous][next][first][last][top][bottom][index][help] */
 998 {
 999     int tc;
1000     long br;
1001     int cmd;
1002     int dummy;
1003 
1004     /* assumes interrupts are off */
1005     cmd = CTL + lp->base;
1006 
1007     /* Reprogram BRG and turn on transmitter to send flags */
1008     if (x == ON) {              /* Turn Tx ON and Receive OFF */
1009         /* Exints off first to avoid abort int */
1010         wrtscc(lp->cardbase, cmd, R15, 0);
1011         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Rx off */
1012         lp->rstate = IDLE;
1013         if (cmd & 2) {          /* if channel a */
1014             /* Set up for TX dma */
1015             wrtscc(lp->cardbase, cmd, R1, WT_FN_RDYFN | EXT_INT_ENAB);
1016         } else {
1017             wrtscc(lp->cardbase, cmd, R1, 0);   /* No interrupts */
1018         }
1019 
1020         if (!lp->clockmode) {
1021             if (lp->speed) {    /* if internally clocked */
1022                 br = lp->speed; /* get desired speed */
1023                 tc = (lp->xtal / br) - 2;       /* calc 1X BRG divisor */
1024                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1025                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1026             }
1027         }
1028         wrtscc(lp->cardbase, cmd, R5, TxCRC_ENAB | RTS | TxENAB | Tx8 | DTR);
1029         /* Transmitter now on */
1030     } else {                    /* Tx OFF and Rx ON */
1031         lp->tstate = IDLE;
1032         wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);       /*  TX off */
1033 
1034         if (!lp->clockmode) {
1035             if (lp->speed) {    /* if internally clocked */
1036                 /* Reprogram BRG for 32x clock for receive DPLL */
1037                 /* BRG off, keep Pclk source */
1038                 wrtscc(lp->cardbase, cmd, R14, BRSRC);
1039                 br = lp->speed; /* get desired speed */
1040                 /* calc 32X BRG divisor */
1041                 tc = ((lp->xtal / 32) / br) - 2;
1042                 wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);      /* lower byte */
1043                 wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);       /* upper byte */
1044                 /* SEARCH mode, BRG source */
1045                 wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);
1046                 /* Enable the BRG */
1047                 wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);
1048             }
1049         }
1050         /* Flush rx fifo */
1051         wrtscc(lp->cardbase, cmd, R3, Rx8);     /* Make sure rx is off */
1052         wrtscc(lp->cardbase, cmd, R0, ERR_RES); /* reset err latch */
1053         dummy = rdscc(lp->cardbase, cmd, R1);   /* get status byte from R1 */
1054         (void) rdscc(lp->cardbase, cmd, R8);
1055         (void) rdscc(lp->cardbase, cmd, R8);
1056 
1057         (void) rdscc(lp->cardbase, cmd, R8);
1058 
1059         /* Now, turn on the receiver and hunt for a flag */
1060         wrtscc(lp->cardbase, cmd, R3, RxENABLE | Rx8);
1061         lp->rstate = ACTIVE;    /* Normal state */
1062 
1063         if (cmd & 2) {          /* if channel a */
1064             setup_rx_dma(lp);
1065         } else {
1066             /* reset buffer pointers */
1067             lp->rcp = lp->rcvbuf->data;
1068             lp->rcvbuf->cnt = 0;
1069             wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1070         }
1071         wrtscc(lp->cardbase, cmd, R15, BRKIE);  /* allow ABORT int */
1072     }
1073 }
1074 
1075 /* Fill in the MAC-level header. */
1076 static int pi_header(struct sk_buff *skb, struct device *dev, unsigned short type,
     /* [previous][next][first][last][top][bottom][index][help] */
1077              void *daddr, void *saddr, unsigned len)
1078 {
1079     return ax25_encapsulate(skb, dev, type, daddr, saddr, len);
1080 }
1081 
1082 /* Rebuild the MAC-level header. */
1083 static int pi_rebuild_header(void *buff, struct device *dev, unsigned long raddr,
     /* [previous][next][first][last][top][bottom][index][help] */
1084                              struct sk_buff *skb)
1085 {
1086     return ax25_rebuild_header(buff, dev, raddr, skb);
1087 }
1088 
1089 static void scc_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1090 {
1091     unsigned long flags;
1092     struct pi_local *lp = (struct pi_local *) dev->priv;
1093 
1094     int tc;
1095     long br;
1096     register int cmd;
1097 
1098     /* Initialize 8530 channel for SDLC operation */
1099 
1100     cmd = CTL + lp->base;
1101     save_flags(flags);
1102     cli();
1103 
1104     switch (cmd & CHANA) {
1105     case CHANA:
1106         wrtscc(lp->cardbase, cmd, R9, CHRA);    /* Reset channel A */
1107         wrtscc(lp->cardbase, cmd, R2, 0xff);    /* Initialize interrupt vector */
1108         break;
1109     default:
1110         wrtscc(lp->cardbase, cmd, R9, CHRB);    /* Reset channel B */
1111         break;
1112     }
1113 
1114     /* Deselect all Rx and Tx interrupts */
1115     wrtscc(lp->cardbase, cmd, R1, 0);
1116 
1117     /* Turn off external interrupts (like CTS/CD) */
1118     wrtscc(lp->cardbase, cmd, R15, 0);
1119 
1120     /* X1 clock, SDLC mode */
1121     wrtscc(lp->cardbase, cmd, R4, SDLC | X1CLK);
1122 
1123     /* Tx/Rx parameters */
1124     if (lp->speed) {            /* Use internal clocking */
1125         wrtscc(lp->cardbase, cmd, R10, CRCPS | NRZI);
1126         if (!lp->clockmode)
1127             /* Tx Clk from BRG. Rcv Clk from DPLL, TRxC pin outputs DPLL */
1128             wrtscc(lp->cardbase, cmd, R11, TCBR | RCDPLL | TRxCDP | TRxCOI);
1129         else
1130             /* Tx Clk from DPLL, Rcv Clk from DPLL, TRxC Outputs BRG */
1131             wrtscc(lp->cardbase, cmd, R11, TCDPLL | RCDPLL | TRxCBR | TRxCOI);
1132     } else {                    /* Use external clocking */
1133         wrtscc(lp->cardbase, cmd, R10, CRCPS);
1134         /* Tx Clk from Trxcl. Rcv Clk from Rtxcl, TRxC pin is input */
1135         wrtscc(lp->cardbase, cmd, R11, TCTRxCP);
1136     }
1137 
1138     /* Null out SDLC start address */
1139     wrtscc(lp->cardbase, cmd, R6, 0);
1140 
1141     /* SDLC flag */
1142     wrtscc(lp->cardbase, cmd, R7, FLAG);
1143 
1144     /* Set up the Transmitter but don't enable it
1145      *  DTR, 8 bit TX chars only
1146      */
1147     wrtscc(lp->cardbase, cmd, R5, Tx8 | DTR);
1148 
1149     /* Receiver initial setup */
1150     wrtscc(lp->cardbase, cmd, R3, Rx8); /* 8 bits/char */
1151 
1152     /* Setting up BRG now - turn it off first */
1153     wrtscc(lp->cardbase, cmd, R14, BRSRC);      /* BRG off, keep Pclk source */
1154 
1155     /* set the 32x time constant for the BRG in Receive mode */
1156 
1157     if (lp->speed) {
1158         br = lp->speed;         /* get desired speed */
1159         tc = ((lp->xtal / 32) / br) - 2;        /* calc 32X BRG divisor */
1160     } else {
1161         tc = 14;
1162     }
1163 
1164     wrtscc(lp->cardbase, cmd, R12, tc & 0xFF);  /* lower byte */
1165     wrtscc(lp->cardbase, cmd, R13, (tc >> 8) & 0xFF);   /* upper byte */
1166 
1167     /* Following subroutine sets up and ENABLES the receiver */
1168     rts(lp, OFF);               /* TX OFF and RX ON */
1169 
1170     if (lp->speed) {
1171         /* DPLL frm BRG, BRG src PCLK */
1172         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSBR);
1173     } else {
1174         /* DPLL frm rtxc,BRG src PCLK */
1175         wrtscc(lp->cardbase, cmd, R14, BRSRC | SSRTxC);
1176     }
1177     wrtscc(lp->cardbase, cmd, R14, BRSRC | SEARCH);     /* SEARCH mode, keep BRG src */
1178     wrtscc(lp->cardbase, cmd, R14, BRSRC | BRENABL);    /* Enable the BRG */
1179 
1180     if (!(cmd & 2))             /* if channel b */
1181         wrtscc(lp->cardbase, cmd, R1, (INT_ALL_Rx | EXT_INT_ENAB));
1182 
1183     wrtscc(lp->cardbase, cmd, R15, BRKIE);      /* ABORT int */
1184 
1185     /* Now, turn on the receiver and hunt for a flag */
1186     wrtscc(lp->cardbase, cmd, R3, RxENABLE | RxCRC_ENAB | Rx8);
1187 
1188     restore_flags(flags);
1189 }
1190 
1191 static void chipset_init(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1192 {
1193     int cardbase;
1194     unsigned long flags;
1195 
1196     cardbase = dev->base_addr & 0x3f0;
1197 
1198     save_flags(flags);
1199     cli();
1200     wrtscc(cardbase, dev->base_addr + CTL, R9, FHWRES); /* Hardware reset */
1201     /* Disable interrupts with master interrupt ctrl reg */
1202     wrtscc(cardbase, dev->base_addr + CTL, R9, 0);
1203     restore_flags(flags);
1204 
1205 }
1206 
1207 
1208 int pi_init(void)
     /* [previous][next][first][last][top][bottom][index][help] */
1209 {
1210     int *port;
1211     int ioaddr = 0;
1212     int card_type = 0;
1213     int ports[] =
1214     {0x380, 0x300, 0x320, 0x340, 0x360, 0x3a0, 0};
1215 
1216     printk(version);
1217 
1218     /* Only one card supported for now */
1219     for (port = &ports[0]; *port && !card_type; port++) {
1220         ioaddr = *port;
1221 
1222         if (check_region(ioaddr, PI_TOTAL_SIZE) == 0) {
1223             printk("PI: Probing for card at address %#3x\n",ioaddr);
1224             card_type = hw_probe(ioaddr);
1225         }
1226     }
1227 
1228     switch (card_type) {
1229     case 1:
1230         printk("PI: Found a PI card at address %#3x\n", ioaddr);
1231         break;
1232     case 2:
1233         printk("PI: Found a PI2 card at address %#3x\n", ioaddr);
1234         break;
1235     default:
1236         printk("PI: ERROR: No card found\n");
1237         return -EIO;
1238     }
1239 
1240     /* Link a couple of device structures into the chain */
1241     /* For the A port */
1242     /* Allocate space for 4 buffers even though we only need 3,
1243        because one of them may cross a DMA page boundary and
1244        be rejected by get_dma_buffer().
1245     */
1246     register_netdev(&pi0a);
1247     
1248     pi0a.priv = kmalloc(sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
1249                         
1250     pi0a.dma = PI_DMA;
1251     pi0a.base_addr = ioaddr + 2;
1252     pi0a.irq = 0;
1253 
1254     /* And the B port */
1255     register_netdev(&pi0b);
1256     pi0b.base_addr = ioaddr;
1257     pi0b.irq = 0;
1258     pi0b.priv = kmalloc(sizeof(struct pi_local) + (DMA_BUFF_SIZE + sizeof(struct mbuf)) * 4, GFP_KERNEL | GFP_DMA);
1259 
1260     /* Now initialize them */
1261     pi_probe(&pi0a, card_type);
1262     pi_probe(&pi0b, card_type);
1263 
1264     pi0b.irq = pi0a.irq;        /* IRQ is shared */
1265     
1266     return 0;
1267 }
1268 
1269 static int valid_dma_page(unsigned long addr, unsigned long dev_buffsize)
     /* [previous][next][first][last][top][bottom][index][help] */
1270 {
1271     if (((addr & 0xffff) + dev_buffsize) <= 0x10000)
1272         return 1;
1273     else
1274         return 0;
1275 }
1276 
1277 static int pi_set_mac_address(struct device *dev, void *addr)
     /* [previous][next][first][last][top][bottom][index][help] */
1278 {
1279     memcpy(dev->dev_addr, addr, 7);     /* addr is an AX.25 shifted ASCII */
1280     return 0;                   /* mac address */
1281 }
1282 
1283 /* Allocate a buffer which does not cross a DMA page boundary */
1284 static char *
1285 get_dma_buffer(unsigned long *mem_ptr)
     /* [previous][next][first][last][top][bottom][index][help] */
1286 {
1287     char *ret;
1288 
1289     ret = (char *)*mem_ptr;
1290 
1291     if(!valid_dma_page(*mem_ptr, DMA_BUFF_SIZE + sizeof(struct mbuf))){
1292         *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1293         ret = (char *)*mem_ptr;
1294     }
1295     *mem_ptr += (DMA_BUFF_SIZE + sizeof(struct mbuf));
1296     return (ret);
1297 }
1298 
1299 static int pi_probe(struct device *dev, int card_type)
     /* [previous][next][first][last][top][bottom][index][help] */
1300 {
1301     short ioaddr;
1302     struct pi_local *lp;
1303     int i;
1304     unsigned long flags;
1305     unsigned long mem_ptr;
1306 
1307     ioaddr = dev->base_addr;
1308 
1309     /* Initialize the device structure. */
1310     /* Must be done before chipset_init */
1311     /* Make certain the data structures used by the PI2 are aligned. */
1312     dev->priv = (void *) (((int) dev->priv + 7) & ~7);
1313     lp = (struct pi_local *) dev->priv;
1314 
1315     memset(dev->priv, 0, sizeof(struct pi_local));
1316 
1317     /* Allocate some buffers which do not cross DMA page boundaries */
1318     mem_ptr = (unsigned long) dev->priv + sizeof(struct pi_local);
1319     lp->txdmabuf = get_dma_buffer(&mem_ptr);
1320     lp->rxdmabuf1 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1321     lp->rxdmabuf2 = (struct mbuf *) get_dma_buffer(&mem_ptr);
1322 
1323     /* Initialize rx buffer */
1324     lp->rcvbuf = lp->rxdmabuf1;
1325     lp->rcp = lp->rcvbuf->data;
1326     lp->rcvbuf->cnt = 0;
1327 
1328     /* Initialize the transmit queue head structure */
1329     skb_queue_head_init(&lp->sndq);
1330 
1331     /* These need to be initialized before scc_init is called. */
1332     if (card_type == 1)
1333         lp->xtal = (unsigned long) SINGLE / 2;
1334     else
1335         lp->xtal = (unsigned long) DOUBLE / 2;
1336     lp->base = dev->base_addr;
1337     lp->cardbase = dev->base_addr & 0x3f0;
1338     if (dev->base_addr & CHANA) {
1339         lp->speed = DEF_A_SPEED;
1340         /* default channel access Params */
1341         lp->txdelay = DEF_A_TXDELAY;
1342         lp->persist = DEF_A_PERSIST;
1343         lp->slotime = DEF_A_SLOTIME;
1344         lp->squeldelay = DEF_A_SQUELDELAY;
1345         lp->clockmode = DEF_A_CLOCKMODE;
1346 
1347     } else {
1348         lp->speed = DEF_B_SPEED;
1349         /* default channel access Params */
1350         lp->txdelay = DEF_B_TXDELAY;
1351         lp->persist = DEF_B_PERSIST;
1352         lp->slotime = DEF_B_SLOTIME;
1353         lp->squeldelay = DEF_B_SQUELDELAY;
1354         lp->clockmode = DEF_B_CLOCKMODE;
1355     }
1356     lp->bufsiz = DMA_BUFF_SIZE;
1357     lp->tstate = IDLE;
1358 
1359     chipset_init(dev);
1360 
1361     if (dev->base_addr & CHANA) {       /* Do these things only for the A port */
1362         /* Note that a single IRQ services 2 devices (A and B channels) */
1363 
1364         lp->dmachan = dev->dma;
1365         if (lp->dmachan < 1 || lp->dmachan > 3)
1366             printk("PI: DMA channel %d out of range\n", lp->dmachan);
1367 
1368         /* chipset_init() was already called */
1369 
1370         if (dev->irq < 2) {
1371             autoirq_setup(0);
1372             save_flags(flags);
1373             cli();
1374             wrtscc(lp->cardbase, CTL + lp->base, R1, EXT_INT_ENAB);
1375             /* enable PI card interrupts */
1376             wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1377             restore_flags(flags);
1378             /* request a timer interrupt for 1 mS hence */
1379             tdelay(lp, 1);
1380             /* 20 "jiffies" should be plenty of time... */
1381             dev->irq = autoirq_report(20);
1382             if (!dev->irq) {
1383                 printk(". Failed to detect IRQ line.\n");
1384             }
1385             save_flags(flags);
1386             cli();
1387             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, FHWRES);     /* Hardware reset */
1388             /* Disable interrupts with master interrupt ctrl reg */
1389             wrtscc(lp->cardbase, dev->base_addr + CTL, R9, 0);
1390             restore_flags(flags);
1391         }
1392 
1393         printk("PI: Autodetected IRQ %d, assuming DMA %d.\n",
1394                dev->irq, dev->dma);
1395 
1396         /* This board has jumpered interrupts. Snarf the interrupt vector
1397                    now.  There is no point in waiting since no other device can use
1398                    the interrupt, and this marks the 'irqaction' as busy. */
1399         {
1400             int irqval = request_irq(dev->irq, &pi_interrupt,0, "pi2");
1401             if (irqval) {
1402                 printk("PI: unable to get IRQ %d (irqval=%d).\n",
1403                        dev->irq, irqval);
1404                 return EAGAIN;
1405             }
1406         }
1407 
1408         /* Grab the region */
1409         snarf_region(ioaddr & 0x3f0, PI_TOTAL_SIZE);
1410 
1411 
1412     }                           /* Only for A port */
1413     dev->open = pi_open;
1414     dev->stop = pi_close;
1415     dev->do_ioctl = pi_ioctl;
1416     dev->hard_start_xmit = pi_send_packet;
1417     dev->get_stats = pi_get_stats;
1418 
1419     /* Fill in the fields of the device structure */
1420     for (i = 0; i < DEV_NUMBUFFS; i++)
1421         skb_queue_head_init(&dev->buffs[i]);
1422 
1423 
1424     dev->hard_header = pi_header;
1425     dev->rebuild_header = pi_rebuild_header;
1426     dev->set_mac_address = pi_set_mac_address;
1427 
1428     dev->type = ARPHRD_AX25;                    /* AF_AX25 device */
1429     dev->hard_header_len = 73;                  /* We do digipeaters now */
1430     dev->mtu = 1500;                            /* eth_mtu is the default */
1431     dev->addr_len = 7;                          /* sizeof an ax.25 address */
1432     memcpy(dev->broadcast, ax25_bcast, 7);
1433     memcpy(dev->dev_addr, ax25_test, 7);
1434 
1435     /* New-style flags. */
1436     dev->flags = 0;
1437     dev->family = AF_INET;
1438     dev->pa_addr = 0;
1439     dev->pa_brdaddr = 0;
1440     dev->pa_mask = 0;
1441     dev->pa_alen = 4;
1442 
1443     return 0;
1444 }
1445 
1446 /* Open/initialize the board.  This is called (in the current kernel)
1447    sometime after booting when the 'ifconfig' program is run.
1448 
1449    This routine should set everything up anew at each open, even
1450    registers that "should" only need to be set once at boot, so that
1451    there is non-reboot way to recover if something goes wrong.
1452    */
1453 static int pi_open(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1454 {
1455     unsigned long flags;
1456     static first_time = 1;
1457 
1458     struct pi_local *lp = (struct pi_local *) dev->priv;
1459 
1460     if (dev->base_addr & 2) {   /* if A channel */
1461         if (first_time) {
1462             if (request_dma(dev->dma,"pi2")) {
1463                 free_irq(dev->irq);
1464                 return -EAGAIN;
1465             }
1466             irq2dev_map[dev->irq] = dev;
1467         }
1468         /* Reset the hardware here. */
1469         chipset_init(dev);
1470     }
1471     lp->tstate = IDLE;
1472 
1473     if (dev->base_addr & 2) {   /* if A channel */
1474         scc_init(dev);          /* Called once for each channel */
1475         scc_init(dev->next);
1476     }
1477     /* master interrupt enable */
1478     save_flags(flags);
1479     cli();
1480     wrtscc(lp->cardbase, CTL + lp->base, R9, MIE | NV);
1481     restore_flags(flags);
1482 
1483     lp->open_time = jiffies;
1484 
1485     dev->tbusy = 0;
1486     dev->interrupt = 0;
1487     dev->start = 1;
1488     first_time = 0;
1489     return 0;
1490 }
1491 
1492 static int pi_send_packet(struct sk_buff *skb, struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1493 {
1494     struct pi_local *lp = (struct pi_local *) dev->priv;
1495 
1496     /* If some higher layer thinks we've missed an tx-done interrupt
1497            we are passed NULL. Caution: dev_tint() handles the cli()/sti()
1498            itself. */
1499     if (skb == NULL) {
1500         dev_tint(dev);
1501         return 0;
1502     }
1503     hardware_send_packet(lp, skb);
1504     dev->trans_start = jiffies;
1505 
1506     return 0;
1507 }
1508 
1509 /* The typical workload of the driver:
1510    Handle the network interface interrupts. */
1511 static void pi_interrupt(int reg_ptr, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
1512 {
1513 /*    int irq = -(((struct pt_regs *) reg_ptr)->orig_eax + 2);*/
1514     struct pi_local *lp;
1515     int st;
1516     unsigned long flags;
1517 
1518 /*    dev_b = dev_a->next;       Relies on the order defined in Space.c */
1519 
1520 #if 0
1521     if (dev_a == NULL) {
1522         printk("PI: pi_interrupt(): irq %d for unknown device.\n", irq);
1523         return;
1524     }
1525 #endif    
1526     /* Read interrupt status register (only valid from channel A)
1527      * Process all pending interrupts in while loop
1528      */
1529     lp = (struct pi_local *) pi0a.priv; /* Assume channel A */
1530     while ((st = rdscc(lp->cardbase, pi0a.base_addr | CHANA | CTL, R3)) != 0) {
1531         if (st & CHBTxIP) {
1532             /* Channel B Transmit Int Pending */
1533             lp = (struct pi_local *) pi0b.priv;
1534             b_txint(lp);
1535         } else if (st & CHARxIP) {
1536             /* Channel A Rcv Interrupt Pending */
1537             lp = (struct pi_local *) pi0a.priv;
1538             a_rxint(&pi0a, lp);
1539         } else if (st & CHATxIP) {
1540             /* Channel A Transmit Int Pending */
1541             lp = (struct pi_local *) pi0a.priv;
1542             a_txint(lp);
1543         } else if (st & CHAEXT) {
1544             /* Channel A External Status Int */
1545             lp = (struct pi_local *) pi0a.priv;
1546             a_exint(lp);
1547         } else if (st & CHBRxIP) {
1548             /* Channel B Rcv Interrupt Pending */
1549             lp = (struct pi_local *) pi0b.priv;
1550             b_rxint(&pi0b, lp);
1551         } else if (st & CHBEXT) {
1552             /* Channel B External Status Int */
1553             lp = (struct pi_local *) pi0b.priv;
1554             b_exint(lp);
1555         }
1556         /* Reset highest interrupt under service */
1557         save_flags(flags);
1558         cli();
1559         wrtscc(lp->cardbase, lp->base + CTL, R0, RES_H_IUS);
1560         restore_flags(flags);
1561     }                           /* End of while loop on int processing */
1562     return;
1563 }
1564 
1565 /* The inverse routine to pi_open(). */
1566 static int pi_close(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1567 {
1568     unsigned long flags;
1569     struct pi_local *lp;
1570     struct sk_buff *ptr;
1571 
1572     save_flags(flags);
1573     cli();
1574 
1575     lp = (struct pi_local *) dev->priv;
1576     ptr = NULL;
1577 
1578     chipset_init(dev);          /* reset the scc */
1579     disable_dma(lp->dmachan);
1580 
1581     lp->open_time = 0;
1582 
1583     dev->tbusy = 1;
1584     dev->start = 0;
1585 
1586     /* Free any buffers left in the hardware transmit queue */
1587     while ((ptr = skb_dequeue(&lp->sndq)) != NULL)
1588         free_p(ptr);
1589 
1590     restore_flags(flags);
1591     return 0;
1592 }
1593 
1594 static int pi_ioctl(struct device *dev, struct ifreq *ifr, int cmd)
     /* [previous][next][first][last][top][bottom][index][help] */
1595 {
1596     unsigned long flags;
1597     struct pi_req rq;
1598     struct pi_local *lp = (struct pi_local *) dev->priv;
1599 
1600     int ret = verify_area(VERIFY_WRITE, ifr->ifr_data, sizeof(struct pi_req));
1601     if (ret)
1602         return ret;
1603         
1604     if(cmd!=SIOCDEVPRIVATE)
1605         return -EINVAL;
1606 
1607     memcpy_fromfs(&rq, ifr->ifr_data, sizeof(struct pi_req));
1608 
1609     switch (rq.cmd) {
1610     case SIOCSPIPARAM:
1611 
1612         if (!suser())
1613             return -EPERM;
1614         save_flags(flags);
1615         cli();
1616         lp->txdelay = rq.txdelay;
1617         lp->persist = rq.persist;
1618         lp->slotime = rq.slotime;
1619         lp->squeldelay = rq.squeldelay;
1620         lp->clockmode = rq.clockmode;
1621         lp->speed = rq.speed;
1622         pi_open(&pi0a); /* both channels get reset %%% */
1623         restore_flags(flags);
1624         ret = 0;
1625         break;
1626 
1627     case SIOCSPIDMA:
1628 
1629         if (!suser())
1630             return -EPERM;
1631         ret = 0;
1632         if (dev->base_addr & 2) {   /* if A channel */
1633            if (rq.dmachan < 1 || rq.dmachan > 3)
1634                 return -EINVAL;
1635            save_flags(flags);
1636            cli();
1637            pi_close(dev);
1638            free_dma(lp->dmachan);
1639            dev->dma = lp->dmachan = rq.dmachan;
1640            if (request_dma(lp->dmachan,"pi2")) 
1641                 ret = -EAGAIN;
1642            pi_open(dev);
1643            restore_flags(flags);
1644         }
1645         break;
1646 
1647     case SIOCSPIIRQ:
1648         ret = -EINVAL;      /* add this later */
1649         break;
1650 
1651     case SIOCGPIPARAM:
1652     case SIOCGPIDMA:
1653     case SIOCGPIIRQ:
1654 
1655         rq.speed = lp->speed;
1656         rq.txdelay = lp->txdelay;
1657         rq.persist = lp->persist;
1658         rq.slotime = lp->slotime;
1659         rq.squeldelay = lp->squeldelay;
1660         rq.clockmode = lp->clockmode;
1661         rq.dmachan = lp->dmachan;
1662         rq.irq = dev->irq;
1663         memcpy_tofs(ifr->ifr_data, &rq, sizeof(struct pi_req));
1664         ret = 0;
1665         break;
1666 
1667     default:
1668         ret = -EINVAL;
1669     }
1670     return ret;
1671 }
1672 
1673 /* Get the current statistics.  This may be called with the card open or
1674    closed. */
1675 static struct netstats *
1676  pi_get_stats(struct device *dev)
     /* [previous][next][first][last][top][bottom][index][help] */
1677 {
1678     struct pi_local *lp = (struct pi_local *) dev->priv;
1679 
1680     return &lp->stats;
1681 }
1682 
1683 
1684 /*
1685  * Local variables:
1686  *  compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c skeleton.c"
1687  *  version-control: t
1688  *  kept-new-versions: 5
1689  *  tab-width: 4
1690  * End:
1691  */

/* [previous][next][first][last][top][bottom][index][help] */