This source file includes following definitions.
- de4x5_probe
- de4x5_hw_init
- de4x5_open
- de4x5_init
- de4x5_queue_pkt
- de4x5_interrupt
- de4x5_rx
- de4x5_tx
- de4x5_close
- de4x5_get_stats
- load_packet
- set_multicast_list
- SetMulticastFilter
- eisa_probe
- pci_probe
- alloc_device
- autoconf_media
- dc21040_autoconf
- dc21041_autoconf
- dc21140_autoconf
- test_media
- ping_media
- test_ans
- reset_init_sia
- load_ms_timer
- create_packet
- dce_us_delay
- dce_ms_delay
- EISA_signature
- DevicePresent
- aprom_crc
- srom_rd
- srom_latch
- srom_command
- srom_address
- srom_data
- sendto_srom
- getfrom_srom
- build_setup_frame
- de4x5_ioctl
- init_module
- cleanup_module
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133 static char *version = "de4x5.c:v0.241 4/18/95 davies@wanton.lkg.dec.com\n";
134
135 #include <linux/config.h>
136 #ifdef MODULE
137 #include <linux/module.h>
138 #include <linux/version.h>
139 #else
140 #define MOD_INC_USE_COUNT
141 #define MOD_DEC_USE_COUNT
142 #endif
143
144 #include <linux/kernel.h>
145 #include <linux/sched.h>
146 #include <linux/string.h>
147 #include <linux/interrupt.h>
148 #include <linux/ptrace.h>
149 #include <linux/errno.h>
150 #include <linux/ioport.h>
151 #include <linux/malloc.h>
152 #include <linux/pci.h>
153 #include <linux/delay.h>
154 #include <asm/bitops.h>
155 #include <asm/io.h>
156 #include <asm/dma.h>
157 #include <asm/segment.h>
158
159 #include <linux/netdevice.h>
160 #include <linux/etherdevice.h>
161 #include <linux/skbuff.h>
162
163 #include <linux/time.h>
164 #include <linux/types.h>
165 #include <linux/unistd.h>
166
167 #include "de4x5.h"
168
169 #ifdef DE4X5_DEBUG
170 static int de4x5_debug = DE4X5_DEBUG;
171 #else
172 static int de4x5_debug = 1;
173 #endif
174
175 #ifdef DE4X5_AUTOSENSE
176 static int de4x5_autosense = DE4X5_AUTOSENSE;
177 #else
178 static int de4x5_autosense = AUTO;
179 #endif
180
181
182
183
184 #define PROBE_LENGTH 32
185 #define ETH_PROM_SIG 0xAA5500FFUL
186
187
188
189
190 #define PKT_BUF_SZ 1544
191 #define MAX_PKT_SZ 1514
192 #define MAX_DAT_SZ 1500
193 #define MIN_DAT_SZ 1
194 #define PKT_HDR_LEN 14
195
196 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
197 #define CRC_POLYNOMIAL_LE 0xedb88320UL
198
199
200
201
202 #define DE4X5_EISA_IO_PORTS 0x0c00
203 #define DE4X5_EISA_TOTAL_SIZE 0xfff
204
205 #define MAX_EISA_SLOTS 16
206 #define EISA_SLOT_INC 0x1000
207
208 #define DE4X5_SIGNATURE {"DE425",""}
209 #define DE4X5_NAME_LENGTH 8
210
211
212
213
214 #define PCI_MAX_BUS_NUM 8
215 #define DE4X5_PCI_TOTAL_SIZE 0x80
216
217
218
219
220
221
222
223 #define ALIGN4 ((u_long)4 - 1)
224 #define ALIGN8 ((u_long)8 - 1)
225 #define ALIGN16 ((u_long)16 - 1)
226 #define ALIGN32 ((u_long)32 - 1)
227 #define ALIGN64 ((u_long)64 - 1)
228 #define ALIGN128 ((u_long)128 - 1)
229
230 #define ALIGN ALIGN32
231 #define CACHE_ALIGN CAL_16LONG
232 #define DESC_SKIP_LEN DSL_0
233
234 #define DESC_ALIGN
235
236 #ifndef IS_NOT_DEC
237 static int is_not_dec = 0;
238 #else
239 static int is_not_dec = 1;
240 #endif
241
242
243
244
245 static u_long irq_mask = IMR_SEM | IMR_RIM | IMR_RUM | IMR_TIM | IMR_TUM ;
246
247 static u_long irq_en = IMR_NIM | IMR_AIM;
248
249 #define ENABLE_IRQs { \
250 imr |= irq_en;\
251 outl(imr, DE4X5_IMR); \
252 }
253
254 #define DISABLE_IRQs {\
255 imr = inl(DE4X5_IMR);\
256 imr &= ~irq_en;\
257 outl(imr, DE4X5_IMR); \
258 }
259
260 #define UNMASK_IRQs {\
261 imr |= irq_mask;\
262 outl(imr, DE4X5_IMR); \
263 }
264
265 #define MASK_IRQs {\
266 imr = inl(DE4X5_IMR);\
267 imr &= ~irq_mask;\
268 outl(imr, DE4X5_IMR); \
269 }
270
271
272
273
274 #define START_DE4X5 {\
275 omr = inl(DE4X5_OMR);\
276 omr |= OMR_ST | OMR_SR;\
277 outl(omr, DE4X5_OMR); \
278 }
279
280 #define STOP_DE4X5 {\
281 omr = inl(DE4X5_OMR);\
282 omr &= ~(OMR_ST|OMR_SR);\
283 outl(omr, DE4X5_OMR); \
284 }
285
286
287
288
289 #define RESET_SIA outl(0, DE4X5_SICR);
290
291
292
293
294 struct de4x5_srom {
295 char reserved[18];
296 char version;
297 char num_adapters;
298 char ieee_addr[6];
299 char info[100];
300 short chksum;
301 };
302
303
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305
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307
308
309
310 #define NUM_RX_DESC 8
311 #define NUM_TX_DESC 8
312 #define BUFF_ALLOC_RETRIES 10
313 #define RX_BUFF_SZ 1536
314
315
316 struct de4x5_desc {
317 volatile long status;
318 u_long des1;
319 char *buf;
320 char *next;
321 DESC_ALIGN
322 };
323
324
325
326
327 #define DE4X5_PKT_STAT_SZ 16
328 #define DE4X5_PKT_BIN_SZ 128
329
330
331 struct de4x5_private {
332 char adapter_name[80];
333 struct de4x5_desc rx_ring[NUM_RX_DESC];
334 struct de4x5_desc tx_ring[NUM_TX_DESC];
335 struct sk_buff *skb[NUM_TX_DESC];
336 int rx_new, rx_old;
337 int tx_new, tx_old;
338 char setup_frame[SETUP_FRAME_LEN];
339 struct enet_statistics stats;
340 struct {
341 unsigned long bins[DE4X5_PKT_STAT_SZ];
342 unsigned long unicast;
343 unsigned long multicast;
344 unsigned long broadcast;
345 unsigned long excessive_collisions;
346 unsigned long tx_underruns;
347 unsigned long excessive_underruns;
348 } pktStats;
349 char rxRingSize;
350 char txRingSize;
351 char bus;
352 u_short chipset;
353 long media;
354 int autosense;
355 int tx_enable;
356 char lostMedia;
357 int setup_f;
358 };
359
360
361
362
363
364
365
366
367
368 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
369 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
370 lp->tx_old -lp->tx_new-1)
371
372
373
374
375
376 static int de4x5_open(struct device *dev);
377 static int de4x5_queue_pkt(struct sk_buff *skb, struct device *dev);
378 static void de4x5_interrupt(int irq, struct pt_regs *regs);
379 static int de4x5_close(struct device *dev);
380 static struct enet_statistics *de4x5_get_stats(struct device *dev);
381 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
382 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd);
383
384
385
386
387 static int de4x5_hw_init(struct device *dev, short iobase);
388 static int de4x5_init(struct device *dev);
389 static int de4x5_rx(struct device *dev);
390 static int de4x5_tx(struct device *dev);
391
392 static int autoconf_media(struct device *dev);
393 static void create_packet(struct device *dev, char *frame, int len);
394 static void dce_us_delay(u_long usec);
395 static void dce_ms_delay(u_long msec);
396 static void load_packet(struct device *dev, char *buf, u_long flags, struct sk_buff *skb);
397 static void dc21040_autoconf(struct device *dev);
398 static void dc21041_autoconf(struct device *dev);
399 static void dc21140_autoconf(struct device *dev);
400 static long test_media(struct device *dev, long irqs, long irq_mask, long csr13, long csr14, long csr15, long msec);
401 static long ping_media(struct device *dev);
402 static void reset_init_sia(struct device *dev, long sicr, long strr, long sigr);
403 static int test_ans(struct device *dev, long irqs, long irq_mask, long msec);
404 static void load_ms_timer(struct device *dev, u_long msec);
405 static int EISA_signature(char *name, long eisa_id);
406 static int DevicePresent(short iobase);
407 static short srom_rd(u_short address, u_char offset);
408 static void srom_latch(u_long command, u_short address);
409 static void srom_command(u_long command, u_short address);
410 static void srom_address(u_long command, u_short address, u_char offset);
411 static short srom_data(u_long command, u_short address);
412
413 static void sendto_srom(u_long command, u_short addr);
414 static long getfrom_srom(u_short addr);
415 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs);
416 static int aprom_crc (struct device *dev);
417
418 static void eisa_probe(struct device *dev, short iobase);
419 static void pci_probe(struct device *dev, short iobase);
420 static struct device *alloc_device(struct device *dev, int iobase);
421 static char *build_setup_frame(struct device *dev, int mode);
422
423 #ifdef MODULE
424 int init_module(void);
425 void cleanup_module(void);
426 static int autoprobed = 1, loading_module = 1;
427 # else
428 static unsigned char de4x5_irq[] = {5,9,10,11};
429 static int autoprobed = 0, loading_module = 0;
430 #endif
431
432 static char name[DE4X5_NAME_LENGTH + 1];
433 static int num_de4x5s = 0, num_eth = 0;
434
435
436
437
438
439
440 static struct bus_type {
441 int bus;
442 int device;
443 int chipset;
444 struct de4x5_srom srom;
445 int autosense;
446 } bus;
447
448
449
450
451 #define RESET_DE4X5 {\
452 long i;\
453 i=inl(DE4X5_BMR);\
454 outl(i | BMR_SWR, DE4X5_BMR);\
455 outl(i, DE4X5_BMR);\
456 for (i=0;i<5;i++) inl(DE4X5_BMR);\
457 }
458
459
460
461 int de4x5_probe(struct device *dev)
462 {
463 int tmp = num_de4x5s, iobase = dev->base_addr;
464 int status = -ENODEV;
465
466 if ((iobase == 0) && loading_module){
467 printk("Autoprobing is not supported when loading a module based driver.\n");
468 status = -EIO;
469 } else {
470
471 eisa_probe(dev, iobase);
472 pci_probe(dev, iobase);
473
474 if ((tmp == num_de4x5s) && (iobase != 0)) {
475 printk("%s: de4x5_probe() cannot find device at 0x%04x.\n", dev->name,
476 iobase);
477 }
478
479
480
481
482
483 for (; (dev->priv == NULL) && (dev->next != NULL); dev = dev->next);
484
485 if (dev->priv) status = 0;
486 if (iobase == 0) autoprobed = 1;
487 }
488
489 return status;
490 }
491
492 static int
493 de4x5_hw_init(struct device *dev, short iobase)
494 {
495 struct bus_type *lp = &bus;
496 int tmpbus, tmpchs, i, j, status=0;
497 char *tmp;
498 u_long nicsr;
499
500
501 if (lp->chipset == DC21041) {
502 outl(0, PCI_CFDA);
503 dce_ms_delay(10);
504 }
505
506 RESET_DE4X5;
507
508 if (((nicsr=inl(DE4X5_STS)) & (STS_TS | STS_RS)) == 0) {
509
510
511
512 if (lp->bus == PCI) {
513 if (!is_not_dec) {
514 if ((lp->chipset == DC21040) || (lp->chipset == DC21041)) {
515 strcpy(name, "DE435");
516 } else if (lp->chipset == DC21140) {
517 strcpy(name, "DE500");
518 }
519 } else {
520 strcpy(name, "UNKNOWN");
521 }
522 } else {
523 EISA_signature(name, EISA_ID0);
524 }
525
526 if (*name != '\0') {
527 dev->base_addr = iobase;
528
529 if (lp->bus == EISA) {
530 printk("%s: %s at %#3x (EISA slot %d)",
531 dev->name, name, (u_short)iobase, (((u_short)iobase>>12)&0x0f));
532 } else {
533 printk("%s: %s at %#3x (PCI device %d)", dev->name, name, (u_short)iobase,lp->device);
534 }
535
536 printk(", h/w address ");
537 status = aprom_crc(dev);
538 for (i = 0; i < ETH_ALEN - 1; i++) {
539 printk("%2.2x:", dev->dev_addr[i]);
540 }
541 printk("%2.2x,\n", dev->dev_addr[i]);
542
543 tmpbus = lp->bus;
544 tmpchs = lp->chipset;
545
546 if (status == 0) {
547 struct de4x5_private *lp;
548
549
550
551
552
553 dev->priv = (void *) kmalloc(sizeof(struct de4x5_private) + ALIGN,
554 GFP_KERNEL);
555
556
557
558 dev->priv = (void *)(((u_long)dev->priv + ALIGN) & ~ALIGN);
559 lp = (struct de4x5_private *)dev->priv;
560 memset(dev->priv, 0, sizeof(struct de4x5_private));
561 lp->bus = tmpbus;
562 lp->chipset = tmpchs;
563
564
565
566
567 if (de4x5_autosense & AUTO) {
568 lp->autosense = AUTO;
569 } else {
570 if (lp->chipset != DC21140) {
571 if ((lp->chipset == DC21040) && (de4x5_autosense & TP_NW)) {
572 de4x5_autosense = TP;
573 }
574 if ((lp->chipset == DC21041) && (de4x5_autosense & BNC_AUI)) {
575 de4x5_autosense = BNC;
576 }
577 lp->autosense = de4x5_autosense & 0x001f;
578 } else {
579 lp->autosense = de4x5_autosense & 0x00c0;
580 }
581 }
582
583 sprintf(lp->adapter_name,"%s (%s)", name, dev->name);
584 request_region(iobase, (lp->bus == PCI ? DE4X5_PCI_TOTAL_SIZE :
585 DE4X5_EISA_TOTAL_SIZE),
586 lp->adapter_name);
587
588
589
590
591
592
593 for (tmp=NULL, j=0; (j<BUFF_ALLOC_RETRIES) && (tmp==NULL); j++) {
594 if ((tmp = (void *)kmalloc(RX_BUFF_SZ * NUM_RX_DESC + ALIGN,
595 GFP_KERNEL)) != NULL) {
596 tmp = (char *)(((u_long) tmp + ALIGN) & ~ALIGN);
597 for (i=0; i<NUM_RX_DESC; i++) {
598 lp->rx_ring[i].status = 0;
599 lp->rx_ring[i].des1 = RX_BUFF_SZ;
600 lp->rx_ring[i].buf = tmp + i * RX_BUFF_SZ;
601 lp->rx_ring[i].next = NULL;
602 }
603 }
604 }
605
606 if (tmp != NULL) {
607 lp->rxRingSize = NUM_RX_DESC;
608 lp->txRingSize = NUM_TX_DESC;
609
610
611 lp->rx_ring[lp->rxRingSize - 1].des1 |= RD_RER;
612 lp->tx_ring[lp->txRingSize - 1].des1 |= TD_TER;
613
614
615 outl((long)lp->rx_ring, DE4X5_RRBA);
616 outl((long)lp->tx_ring, DE4X5_TRBA);
617
618 lp->tx_enable = TRUE;
619
620 if (dev->irq < 2) {
621 #ifndef MODULE
622 unsigned char irqnum;
623 u_long omr;
624 autoirq_setup(0);
625
626 omr = inl(DE4X5_OMR);
627 outl(IMR_AIM|IMR_RUM, DE4X5_IMR);
628 outl(OMR_SR | omr, DE4X5_OMR);
629
630 irqnum = autoirq_report(1);
631 if (!irqnum) {
632 printk(" and failed to detect IRQ line.\n");
633 status = -ENXIO;
634 } else {
635 for (dev->irq=0,i=0; (i<sizeof(de4x5_irq)) && (!dev->irq); i++) {
636 if (irqnum == de4x5_irq[i]) {
637 dev->irq = irqnum;
638 printk(" and uses IRQ%d.\n", dev->irq);
639 }
640 }
641
642 if (!dev->irq) {
643 printk(" but incorrect IRQ line detected.\n");
644 status = -ENXIO;
645 }
646 }
647
648 outl(0, DE4X5_IMR);
649
650 #endif
651 } else {
652 printk(" and requires IRQ%d (not probed).\n", dev->irq);
653 }
654 } else {
655 printk("%s: Kernel could not allocate RX buffer memory.\n",
656 dev->name);
657 status = -ENXIO;
658 }
659 if (status) release_region(iobase, (lp->bus == PCI ?
660 DE4X5_PCI_TOTAL_SIZE :
661 DE4X5_EISA_TOTAL_SIZE));
662 } else {
663 printk(" which has an Ethernet PROM CRC error.\n");
664 status = -ENXIO;
665 }
666 } else {
667 status = -ENXIO;
668 }
669 } else {
670 status = -ENXIO;
671 }
672
673 if (!status) {
674 if (de4x5_debug > 0) {
675 printk(version);
676 }
677
678
679 dev->open = &de4x5_open;
680 dev->hard_start_xmit = &de4x5_queue_pkt;
681 dev->stop = &de4x5_close;
682 dev->get_stats = &de4x5_get_stats;
683 #ifdef HAVE_MULTICAST
684 dev->set_multicast_list = &set_multicast_list;
685 #endif
686 dev->do_ioctl = &de4x5_ioctl;
687
688 dev->mem_start = 0;
689
690
691 ether_setup(dev);
692
693
694 if (lp->chipset == DC21041) {
695 outl(0, DE4X5_SICR);
696 outl(CFDA_PSM, PCI_CFDA);
697 }
698 } else {
699 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
700 if (lp) {
701 kfree_s(lp->rx_ring[0].buf, RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
702 }
703 if (dev->priv) {
704 kfree_s(dev->priv, sizeof(struct de4x5_private) + ALIGN);
705 dev->priv = NULL;
706 }
707 }
708
709 return status;
710 }
711
712
713 static int
714 de4x5_open(struct device *dev)
715 {
716 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
717 short iobase = dev->base_addr;
718 int i, status = 0;
719 long imr, omr, sts;
720
721
722
723
724 if (lp->chipset == DC21041) {
725 outl(0, PCI_CFDA);
726 dce_ms_delay(10);
727 }
728
729 if (request_irq(dev->irq, (void *)de4x5_interrupt, 0, lp->adapter_name)) {
730 printk("de4x5_open(): Requested IRQ%d is busy\n",dev->irq);
731 status = -EAGAIN;
732 } else {
733
734 irq2dev_map[dev->irq] = dev;
735
736
737
738 status = de4x5_init(dev);
739
740 if (de4x5_debug > 1){
741 printk("%s: de4x5 open with irq %d\n",dev->name,dev->irq);
742 printk("\tphysical address: ");
743 for (i=0;i<6;i++){
744 printk("%2.2x:",(short)dev->dev_addr[i]);
745 }
746 printk("\n");
747 printk("Descriptor head addresses:\n");
748 printk("\t0x%8.8lx 0x%8.8lx\n",(long)lp->rx_ring,(long)lp->tx_ring);
749 printk("Descriptor addresses:\nRX: ");
750 for (i=0;i<lp->rxRingSize-1;i++){
751 if (i < 3) {
752 printk("0x%8.8lx ",(long)&lp->rx_ring[i].status);
753 }
754 }
755 printk("...0x%8.8lx\n",(long)&lp->rx_ring[i].status);
756 printk("TX: ");
757 for (i=0;i<lp->txRingSize-1;i++){
758 if (i < 3) {
759 printk("0x%8.8lx ", (long)&lp->tx_ring[i].status);
760 }
761 }
762 printk("...0x%8.8lx\n", (long)&lp->tx_ring[i].status);
763 printk("Descriptor buffers:\nRX: ");
764 for (i=0;i<lp->rxRingSize-1;i++){
765 if (i < 3) {
766 printk("0x%8.8lx ",(long)lp->rx_ring[i].buf);
767 }
768 }
769 printk("...0x%8.8lx\n",(long)lp->rx_ring[i].buf);
770 printk("TX: ");
771 for (i=0;i<lp->txRingSize-1;i++){
772 if (i < 3) {
773 printk("0x%8.8lx ", (long)lp->tx_ring[i].buf);
774 }
775 }
776 printk("...0x%8.8lx\n", (long)lp->tx_ring[i].buf);
777 printk("Ring size: \nRX: %d\nTX: %d\n",
778 (short)lp->rxRingSize,
779 (short)lp->txRingSize);
780 printk("\tstatus: %d\n", status);
781 }
782
783 if (!status) {
784 dev->tbusy = 0;
785 dev->start = 1;
786 dev->interrupt = UNMASK_INTERRUPTS;
787 dev->trans_start = jiffies;
788
789 START_DE4X5;
790
791
792 imr = 0;
793 UNMASK_IRQs;
794
795
796 sts = inl(DE4X5_STS);
797 outl(sts, DE4X5_STS);
798
799 ENABLE_IRQs;
800 }
801 if (de4x5_debug > 1) {
802 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
803 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
804 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
805 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
806 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
807 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
808 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
809 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
810 }
811 }
812
813 MOD_INC_USE_COUNT;
814
815 return status;
816 }
817
818
819
820
821
822
823
824
825
826 static int
827 de4x5_init(struct device *dev)
828 {
829 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
830 short iobase = dev->base_addr;
831 int status = 0;
832 long i, j, bmr, omr;
833
834
835 set_bit(0, (void *)&dev->tbusy);
836
837 RESET_DE4X5;
838
839 bmr = inl(DE4X5_BMR);
840 bmr |= PBL_8 | DESC_SKIP_LEN | CACHE_ALIGN;
841 outl(bmr, DE4X5_BMR);
842
843 if (lp->chipset != DC21140) {
844 omr = TR_96;
845 lp->setup_f = HASH_PERF;
846 } else {
847 omr = OMR_SDP | OMR_SF;
848 lp->setup_f = PERFECT;
849 }
850 outl((long)lp->rx_ring, DE4X5_RRBA);
851 outl((long)lp->tx_ring, DE4X5_TRBA);
852
853 lp->rx_new = lp->rx_old = 0;
854 lp->tx_new = lp->tx_old = 0;
855
856 for (i = 0; i < lp->rxRingSize; i++) {
857 lp->rx_ring[i].status = R_OWN;
858 }
859
860 for (i = 0; i < lp->txRingSize; i++) {
861 lp->tx_ring[i].status = 0;
862 }
863
864
865 SetMulticastFilter(dev, 0, NULL);
866
867 if (lp->chipset != DC21140) {
868 load_packet(dev, lp->setup_frame, HASH_F|TD_SET|SETUP_FRAME_LEN, NULL);
869 } else {
870 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, NULL);
871 }
872 outl(omr|OMR_ST, DE4X5_OMR);
873
874
875 for (j=0, i=0;(i<100) && (j==0);i++) {
876 if (lp->tx_ring[lp->tx_new].status >= 0) j=1;
877 }
878 outl(omr, DE4X5_OMR);
879
880 if (i == 100) {
881 printk("%s: Setup frame timed out, status %08x\n", dev->name,
882 inl(DE4X5_STS));
883 status = -EIO;
884 }
885
886 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
887 lp->tx_old = lp->tx_new;
888
889
890 if (autoconf_media(dev) == 0) {
891 status = -EIO;
892 }
893
894 return 0;
895 }
896
897
898
899
900 static int
901 de4x5_queue_pkt(struct sk_buff *skb, struct device *dev)
902 {
903 volatile struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
904 int iobase = dev->base_addr;
905 int status = 0;
906 u_long imr, omr, sts;
907
908 sts = inl(DE4X5_STS);
909
910
911
912
913
914
915 if (dev->tbusy || (lp->lostMedia > LOST_MEDIA_THRESHOLD)) {
916 int tickssofar = jiffies - dev->trans_start;
917 if (tickssofar < 10 && (lp->lostMedia <= LOST_MEDIA_THRESHOLD)) {
918 status = -1;
919 } else {
920 printk("%s: transmit timed out, status %08x, tbusy:%d, lostMedia:%d tickssofar:%d, resetting.\n",dev->name, inl(DE4X5_STS), dev->tbusy, lp->lostMedia, tickssofar);
921
922
923 STOP_DE4X5;
924 status = de4x5_init(dev);
925
926
927 if (!status) {
928
929 dev->interrupt = UNMASK_INTERRUPTS;
930 dev->start = 1;
931 dev->tbusy = 0;
932 dev->trans_start = jiffies;
933
934 START_DE4X5;
935
936
937 imr = 0;
938 UNMASK_IRQs;
939
940
941 sts = inl(DE4X5_STS);
942 outl(sts, DE4X5_STS);
943
944 ENABLE_IRQs;
945 } else {
946 printk("%s: hardware initialisation failure, status %08x.\n",
947 dev->name, inl(DE4X5_STS));
948 }
949 }
950 } else if (skb == NULL) {
951 dev_tint(dev);
952 } else if (skb->len > 0) {
953
954
955
956
957
958 if (set_bit(0, (void*)&dev->tbusy) != 0)
959 printk("%s: Transmitter access conflict.\n", dev->name);
960
961 if (TX_BUFFS_AVAIL) {
962 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
963 if (lp->tx_enable) {
964 outl(POLL_DEMAND, DE4X5_TPD);
965 }
966
967 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
968
969 dev->trans_start = jiffies;
970 }
971
972 if (TX_BUFFS_AVAIL) {
973 dev->tbusy = 0;
974 }
975 }
976
977 return status;
978 }
979
980
981
982
983 static void
984 de4x5_interrupt(int irq, struct pt_regs *regs)
985 {
986 struct device *dev = (struct device *)(irq2dev_map[irq]);
987 struct de4x5_private *lp;
988 int iobase;
989 u_long imr, omr, sts;
990
991 if (dev == NULL) {
992 printk ("de4x5_interrupt(): irq %d for unknown device.\n", irq);
993 } else {
994 lp = (struct de4x5_private *)dev->priv;
995 iobase = dev->base_addr;
996
997 if (dev->interrupt)
998 printk("%s: Re-entering the interrupt handler.\n", dev->name);
999
1000 dev->interrupt = MASK_INTERRUPTS;
1001
1002
1003
1004
1005
1006
1007
1008 sts = inl(DE4X5_STS);
1009 MASK_IRQs;
1010
1011 outl(sts, DE4X5_STS);
1012
1013 if (sts & (STS_RI | STS_RU))
1014 de4x5_rx(dev);
1015
1016 if (sts & (STS_TI | STS_TU))
1017 de4x5_tx(dev);
1018
1019 if (sts & STS_SE) {
1020 STOP_DE4X5;
1021 printk("%s: Fatal bus error occurred, sts=0x%08lx, device stopped.\n",
1022 dev->name, sts);
1023 }
1024
1025 if (TX_BUFFS_AVAIL && dev->tbusy) {
1026 dev->tbusy = 0;
1027 mark_bh(NET_BH);
1028 }
1029
1030 dev->interrupt = UNMASK_INTERRUPTS;
1031
1032 UNMASK_IRQs;
1033 }
1034
1035 return;
1036 }
1037
1038 static int
1039 de4x5_rx(struct device *dev)
1040 {
1041 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1042 int i, entry;
1043 volatile long status;
1044 char *buf;
1045
1046 for (entry = lp->rx_new; lp->rx_ring[entry].status >= 0;entry = lp->rx_new) {
1047 status = lp->rx_ring[entry].status;
1048
1049 if (status & RD_FS) {
1050 lp->rx_old = entry;
1051 }
1052
1053 if (status & RD_LS) {
1054 if (status & RD_ES) {
1055 lp->stats.rx_errors++;
1056 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1057 if (status & RD_CE) lp->stats.rx_crc_errors++;
1058 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1059 } else {
1060 struct sk_buff *skb;
1061 short pkt_len = (short)(lp->rx_ring[entry].status >> 16) - 4;
1062
1063 if ((skb = alloc_skb(pkt_len, GFP_ATOMIC)) != NULL) {
1064 skb->len = pkt_len;
1065 skb->dev = dev;
1066
1067 if (entry < lp->rx_old) {
1068 short len = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
1069 memcpy(skb->data, lp->rx_ring[lp->rx_old].buf, len);
1070 memcpy(skb->data + len, lp->rx_ring[0].buf, pkt_len - len);
1071 } else {
1072 memcpy(skb->data, lp->rx_ring[lp->rx_old].buf, pkt_len);
1073 }
1074
1075
1076
1077
1078
1079 skb->protocol=eth_type_trans(skb,dev);
1080 netif_rx(skb);
1081
1082
1083
1084
1085 lp->stats.rx_packets++;
1086 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1087 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1088 lp->pktStats.bins[i]++;
1089 i = DE4X5_PKT_STAT_SZ;
1090 }
1091 }
1092 buf = skb->data;
1093 if (buf[0] & 0x01) {
1094 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1095 lp->pktStats.broadcast++;
1096 } else {
1097 lp->pktStats.multicast++;
1098 }
1099 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1100 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1101 lp->pktStats.unicast++;
1102 }
1103
1104 lp->pktStats.bins[0]++;
1105 if (lp->pktStats.bins[0] == 0) {
1106 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1107 }
1108 } else {
1109 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1110 lp->stats.rx_dropped++;
1111 break;
1112 }
1113 }
1114
1115
1116 for (; lp->rx_old!=entry; lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1117 lp->rx_ring[lp->rx_old].status = R_OWN;
1118 }
1119 lp->rx_ring[entry].status = R_OWN;
1120 }
1121
1122
1123
1124
1125 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1126 }
1127
1128 return 0;
1129 }
1130
1131
1132
1133
1134 static int
1135 de4x5_tx(struct device *dev)
1136 {
1137 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1138 int entry, iobase = dev->base_addr;
1139 long status;
1140
1141 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1142 status = lp->tx_ring[entry].status;
1143 if (status < 0) {
1144 break;
1145 } else if (status & TD_ES) {
1146 lp->stats.tx_errors++;
1147 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1148 if (status & TD_LC) lp->stats.tx_window_errors++;
1149 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1150 if (status & TD_LC) lp->stats.collisions++;
1151 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1152 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1153
1154 if (status & (TD_LO | TD_NC | TD_EC | TD_LF)) {
1155 lp->lostMedia++;
1156 } else {
1157 outl(POLL_DEMAND, DE4X5_TPD);
1158 }
1159 } else {
1160 lp->stats.tx_packets++;
1161 lp->lostMedia = 0;
1162 }
1163
1164 if (lp->skb[entry] != NULL) {
1165 dev_kfree_skb(lp->skb[entry], FREE_WRITE);
1166 }
1167
1168
1169 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1170 }
1171
1172 return 0;
1173 }
1174
1175 static int
1176 de4x5_close(struct device *dev)
1177 {
1178 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1179 int iobase = dev->base_addr;
1180 u_long imr, omr;
1181
1182 dev->start = 0;
1183 dev->tbusy = 1;
1184
1185 if (de4x5_debug > 1) {
1186 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1187 dev->name, inl(DE4X5_STS));
1188 }
1189
1190
1191
1192
1193 DISABLE_IRQs;
1194
1195 STOP_DE4X5;
1196
1197
1198
1199
1200 free_irq(dev->irq);
1201 irq2dev_map[dev->irq] = 0;
1202
1203 MOD_DEC_USE_COUNT;
1204
1205
1206 if (lp->chipset == DC21041) {
1207 outl(0, DE4X5_SICR);
1208 outl(CFDA_PSM, PCI_CFDA);
1209 }
1210
1211 return 0;
1212 }
1213
1214 static struct enet_statistics *
1215 de4x5_get_stats(struct device *dev)
1216 {
1217 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1218 int iobase = dev->base_addr;
1219
1220 lp->stats.rx_missed_errors = (int) (inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1221
1222 return &lp->stats;
1223 }
1224
1225 static void load_packet(struct device *dev, char *buf, u_long flags, struct sk_buff *skb)
1226 {
1227 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1228
1229 lp->tx_ring[lp->tx_new].buf = buf;
1230 lp->tx_ring[lp->tx_new].des1 &= TD_TER;
1231 lp->tx_ring[lp->tx_new].des1 |= flags;
1232 lp->skb[lp->tx_new] = skb;
1233 lp->tx_ring[lp->tx_new].status = T_OWN;
1234
1235 return;
1236 }
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247 static void
1248 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1249 {
1250 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1251 int iobase = dev->base_addr;
1252
1253
1254 if (irq2dev_map[dev->irq] != NULL) {
1255 if (num_addrs >= 0) {
1256 SetMulticastFilter(dev, num_addrs, (char *)addrs);
1257 if (lp->setup_f == HASH_PERF) {
1258 load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
1259 SETUP_FRAME_LEN, NULL);
1260 } else {
1261 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1262 SETUP_FRAME_LEN, NULL);
1263 }
1264
1265 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1266 outl(POLL_DEMAND, DE4X5_TPD);
1267 dev->trans_start = jiffies;
1268 }
1269 }
1270
1271 return;
1272 }
1273
1274
1275
1276
1277
1278
1279 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs)
1280 {
1281 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1282 int i, j, bit, byte, iobase = dev->base_addr;
1283 u_short hashcode;
1284 u_long crc, omr, poly = CRC_POLYNOMIAL_LE;
1285 char *pa;
1286
1287 omr = inl(DE4X5_OMR);
1288 pa = build_setup_frame(dev, ALL);
1289
1290 if (lp->setup_f == HASH_PERF) {
1291 if (num_addrs == HASH_TABLE_LEN) {
1292 omr |= OMR_PM;
1293 } else {
1294 omr &= ~OMR_PM;
1295
1296 for (i=0;i<num_addrs;i++) {
1297 if ((*addrs & 0x01) == 1) {
1298 crc = 0xffffffff;
1299 for (byte=0;byte<ETH_ALEN;byte++) {
1300
1301 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1302 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1303 }
1304 }
1305 hashcode = crc & HASH_BITS;
1306
1307 byte = hashcode >> 3;
1308 bit = 1 << (hashcode & 0x07);
1309
1310 byte <<= 1;
1311 if (byte & 0x02) {
1312 byte -= 1;
1313 }
1314 lp->setup_frame[byte] |= bit;
1315
1316 } else {
1317 addrs += ETH_ALEN;
1318 }
1319 }
1320 }
1321 } else {
1322 omr &= ~OMR_PM;
1323 for (j=0; j<num_addrs; j++) {
1324 for (i=0; i<ETH_ALEN; i++) {
1325 *(pa + (i&1)) = *addrs++;
1326 if (i & 0x01) pa += 4;
1327 }
1328 }
1329 }
1330 outl(omr, DE4X5_OMR);
1331
1332 return;
1333 }
1334
1335
1336
1337
1338
1339 static void eisa_probe(struct device *dev, short ioaddr)
1340 {
1341 int i, maxSlots;
1342 int status;
1343 u_short vendor, device, iobase;
1344 struct bus_type *lp = &bus;
1345 char name[DE4X5_STRLEN];
1346 long cfid;
1347
1348 if (!ioaddr && autoprobed) return ;
1349 if ((ioaddr < 0x1000) && (ioaddr > 0)) return;
1350
1351 lp->bus = EISA;
1352
1353 if (ioaddr == 0) {
1354 iobase = EISA_SLOT_INC;
1355 i = 1;
1356 maxSlots = MAX_EISA_SLOTS;
1357 } else {
1358 iobase = ioaddr;
1359 i = (ioaddr >> 12);
1360 maxSlots = i + 1;
1361 }
1362
1363 for (status = -ENODEV; (i<maxSlots) && (dev!=NULL); i++, iobase+=EISA_SLOT_INC) {
1364 if (EISA_signature(name, EISA_ID)) {
1365 cfid = inl(PCI_CFID);
1366 device = (u_short)(cfid >> 16);
1367 vendor = (u_short) cfid;
1368
1369 lp->bus = EISA;
1370 lp->chipset = device;
1371 if (DevicePresent(EISA_APROM) == 0) {
1372
1373 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
1374 outl(0x00004000, PCI_CFLT);
1375 outl((u_long)iobase, PCI_CBIO);
1376
1377 if (check_region(iobase, DE4X5_EISA_TOTAL_SIZE) == 0) {
1378 if ((dev = alloc_device(dev, iobase)) != NULL) {
1379 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1380 num_de4x5s++;
1381 }
1382 num_eth++;
1383 }
1384 } else if (autoprobed) {
1385 printk("%s: region already allocated at 0x%04x.\n", dev->name, iobase);
1386 }
1387 }
1388 }
1389 }
1390
1391 return;
1392 }
1393
1394
1395
1396
1397 #define PCI_DEVICE (dev_num << 3)
1398 #define PCI_LAST_DEV 32
1399
1400 static void pci_probe(struct device *dev, short ioaddr)
1401
1402 {
1403 u_char irq;
1404 u_short pb, dev_num, dev_last;
1405 u_short vendor, device, status;
1406 u_long class, iobase;
1407 struct bus_type *lp = &bus;
1408
1409 if (!ioaddr && autoprobed) return ;
1410
1411 if (pcibios_present()) {
1412 lp->bus = PCI;
1413
1414 if (ioaddr < 0x1000) {
1415 pb = (u_short)(ioaddr >> 8);
1416 dev_num = (u_short)(ioaddr & 0xff);
1417 } else {
1418 pb = 0;
1419 dev_num = 0;
1420 }
1421 if (ioaddr > 0) {
1422 dev_last = (dev_num < PCI_LAST_DEV) ? dev_num + 1 : PCI_LAST_DEV;
1423 } else {
1424 dev_last = PCI_LAST_DEV;
1425 }
1426
1427 for (; (dev_num < dev_last) && (dev != NULL); dev_num++) {
1428 pcibios_read_config_dword(pb, PCI_DEVICE, PCI_CLASS_REVISION, &class);
1429 if (class != 0xffffffff) {
1430 pcibios_read_config_word(pb, PCI_DEVICE, PCI_VENDOR_ID, &vendor);
1431 pcibios_read_config_word(pb, PCI_DEVICE, PCI_DEVICE_ID, &device);
1432 if (is_DC21040 || is_DC21041 || is_DC21140) {
1433
1434 lp->device = dev_num;
1435
1436
1437 lp->chipset = device;
1438
1439
1440 pcibios_read_config_dword(pb, PCI_DEVICE, PCI_BASE_ADDRESS_0, &iobase);
1441 iobase &= CBIO_MASK;
1442
1443
1444 pcibios_read_config_byte(pb, PCI_DEVICE, PCI_INTERRUPT_LINE, &irq);
1445
1446
1447 pcibios_read_config_word(pb, PCI_DEVICE, PCI_COMMAND, &status);
1448 status |= PCI_COMMAND_IO | PCI_COMMAND_MASTER;
1449 pcibios_write_config_word(pb, PCI_DEVICE, PCI_COMMAND, status);
1450
1451
1452 if ((DevicePresent(DE4X5_APROM) == 0) || is_not_dec) {
1453 if (check_region(iobase, DE4X5_PCI_TOTAL_SIZE) == 0) {
1454 if ((dev = alloc_device(dev, iobase)) != NULL) {
1455 dev->irq = irq;
1456 if ((status = de4x5_hw_init(dev, iobase)) == 0) {
1457 num_de4x5s++;
1458 }
1459 num_eth++;
1460 }
1461 } else if (autoprobed) {
1462 printk("%s: region already allocated at 0x%04x.\n", dev->name, (u_short)iobase);
1463 }
1464 }
1465 }
1466 }
1467 }
1468 }
1469
1470 return;
1471 }
1472
1473
1474
1475
1476
1477 static struct device *alloc_device(struct device *dev, int iobase)
1478 {
1479 int addAutoProbe = 0;
1480 struct device *tmp = NULL, *ret;
1481 int (*init)(struct device *) = NULL;
1482
1483
1484
1485
1486 if (!loading_module) {
1487 while (dev->next != NULL) {
1488 if ((dev->base_addr == 0xffe0) || (dev->base_addr == 0)) break;
1489 dev = dev->next;
1490 num_eth++;
1491 }
1492
1493
1494
1495
1496
1497 if ((dev->base_addr == 0) && (num_de4x5s > 0)) {
1498 addAutoProbe++;
1499 tmp = dev->next;
1500 init = dev->init;
1501 }
1502
1503
1504
1505
1506
1507 if ((dev->next == NULL) &&
1508 !((dev->base_addr == 0xffe0) || (dev->base_addr == 0))){
1509 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1510 GFP_KERNEL);
1511
1512 dev = dev->next;
1513 if (dev == NULL) {
1514 printk("eth%d: Device not initialised, insufficient memory\n",
1515 num_eth);
1516 } else {
1517
1518
1519
1520
1521
1522 dev->name = (char *)(dev + sizeof(struct device));
1523 if (num_eth > 9999) {
1524 sprintf(dev->name,"eth????");
1525 } else {
1526 sprintf(dev->name,"eth%d", num_eth);
1527 }
1528 dev->base_addr = iobase;
1529 dev->next = NULL;
1530 dev->init = &de4x5_probe;
1531 num_de4x5s++;
1532 }
1533 }
1534 ret = dev;
1535
1536
1537
1538
1539
1540 if (ret != NULL) {
1541 if (addAutoProbe) {
1542 for (; (tmp->next!=NULL) && (tmp->base_addr!=0xffe0); tmp=tmp->next);
1543
1544
1545
1546
1547
1548 if ((tmp->next == NULL) && !(tmp->base_addr == 0xffe0)) {
1549 tmp->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1550 GFP_KERNEL);
1551 tmp = tmp->next;
1552 if (tmp == NULL) {
1553 printk("%s: Insufficient memory to extend the device list.\n",
1554 dev->name);
1555 } else {
1556
1557
1558
1559
1560
1561 tmp->name = (char *)(tmp + sizeof(struct device));
1562 if (num_eth > 9999) {
1563 sprintf(tmp->name,"eth????");
1564 } else {
1565 sprintf(tmp->name,"eth%d", num_eth);
1566 }
1567 tmp->base_addr = 0;
1568 tmp->next = NULL;
1569 tmp->init = init;
1570 }
1571 } else {
1572 tmp->base_addr = 0;
1573 }
1574 }
1575 }
1576 } else {
1577 ret = dev;
1578 }
1579
1580 return ret;
1581 }
1582
1583
1584
1585
1586
1587
1588
1589 static int autoconf_media(struct device *dev)
1590 {
1591 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1592 int iobase = dev->base_addr;
1593
1594 if (lp->chipset == DC21040) {
1595 lp->media = (lp->autosense == AUTO ? TP : lp->autosense);
1596 dc21040_autoconf(dev);
1597 } else if (lp->chipset == DC21041) {
1598 lp->media = (lp->autosense == AUTO ? TP_NW : lp->autosense);
1599 dc21041_autoconf(dev);
1600 } else if (lp->chipset == DC21140) {
1601
1602 lp->media = (lp->autosense == AUTO ? _10Mb : lp->autosense);
1603 dc21140_autoconf(dev);
1604 }
1605
1606 if (de4x5_debug >= 1 ) {
1607 if (lp->chipset != DC21140) {
1608 printk("%s: Media is %s\n",dev->name,
1609 (lp->media == NC ? "unconnected!" :
1610 (lp->media == TP ? "TP." :
1611 (lp->media == ANS ? "TP/Nway." :
1612 (lp->media == BNC ? "BNC." :
1613 (lp->media == AUI ? "AUI." :
1614 "BNC/AUI."
1615 ))))));
1616 } else {
1617 printk("%s: Mode is forced to %s\n",dev->name,
1618 (lp->media == NC ? "link down.":
1619 (lp->media == _100Mb ? "100Mb/s." :
1620 (lp->media == _10Mb ? "10Mb/s." :
1621 "\?\?\?"
1622 ))));
1623 }
1624 }
1625
1626 if (lp->media) {
1627 lp->lostMedia = 0;
1628 inl(DE4X5_MFC);
1629 }
1630 dce_ms_delay(10);
1631
1632 return (lp->media);
1633 }
1634
1635 static void dc21040_autoconf(struct device *dev)
1636 {
1637 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1638 int iobase = dev->base_addr;
1639 u_long i, sisr = 0, linkBad;
1640 u_long t_3s = 3000;
1641
1642 switch (lp->media) {
1643 case TP:
1644 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1645 for (linkBad=1,i=0;(i<t_3s) && linkBad && !(sisr & SISR_NCR);i++) {
1646 if (((sisr = inl(DE4X5_SISR)) & SISR_LKF) == 0) linkBad = 0;
1647 dce_ms_delay(1);
1648 }
1649 if (linkBad && (lp->autosense == AUTO)) {
1650 lp->media = BNC_AUI;
1651 dc21040_autoconf(dev);
1652 }
1653 break;
1654
1655 case BNC:
1656 case AUI:
1657 case BNC_AUI:
1658 reset_init_sia(dev, 0x8f09, 0x0705, 0x0006);
1659 dce_ms_delay(330);
1660 linkBad = ping_media(dev);
1661 if (linkBad && (lp->autosense == AUTO)) {
1662 lp->media = NC;
1663 dc21040_autoconf(dev);
1664 }
1665 break;
1666
1667 case NC:
1668 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
1669 break;
1670 }
1671
1672 return;
1673 }
1674
1675
1676
1677
1678
1679
1680
1681 static void dc21041_autoconf(struct device *dev)
1682 {
1683 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1684 int iobase = dev->base_addr;
1685 u_long sts, irqs, irq_mask, omr;
1686
1687 switch (lp->media) {
1688 case TP_NW:
1689 omr = inl(DE4X5_OMR);
1690 outl(omr | OMR_FD, DE4X5_OMR);
1691 irqs = STS_LNF | STS_LNP;
1692 irq_mask = IMR_LFM | IMR_LPM;
1693 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
1694 if (sts & STS_LNP) {
1695 lp->media = ANS;
1696 } else {
1697 lp->media = AUI;
1698 }
1699 dc21041_autoconf(dev);
1700 break;
1701
1702 case ANS:
1703 irqs = STS_LNP;
1704 irq_mask = IMR_LPM;
1705 sts = test_ans(dev, irqs, irq_mask, 3000);
1706 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1707 lp->media = TP;
1708 dc21041_autoconf(dev);
1709 }
1710 break;
1711
1712 case TP:
1713 omr = inl(DE4X5_OMR);
1714 outl(omr & ~OMR_FD, DE4X5_OMR);
1715 irqs = STS_LNF | STS_LNP;
1716 irq_mask = IMR_LFM | IMR_LPM;
1717 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
1718 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
1719 if (inl(DE4X5_SISR) & SISR_NRA) {
1720 lp->media = AUI;
1721 } else {
1722 lp->media = BNC;
1723 }
1724 dc21041_autoconf(dev);
1725 }
1726 break;
1727
1728 case AUI:
1729 omr = inl(DE4X5_OMR);
1730 outl(omr & ~OMR_FD, DE4X5_OMR);
1731 irqs = 0;
1732 irq_mask = 0;
1733 sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x000e, 1000);
1734 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1735 lp->media = BNC;
1736 dc21041_autoconf(dev);
1737 }
1738 break;
1739
1740 case BNC:
1741 omr = inl(DE4X5_OMR);
1742 outl(omr & ~OMR_FD, DE4X5_OMR);
1743 irqs = 0;
1744 irq_mask = 0;
1745 sts = test_media(dev, irqs, irq_mask, 0xef09, 0xf7fd, 0x0006, 1000);
1746 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
1747 lp->media = NC;
1748 } else {
1749 if (ping_media(dev)) lp->media = NC;
1750 }
1751 break;
1752
1753 case NC:
1754 omr = inl(DE4X5_OMR);
1755 outl(omr | OMR_FD, DE4X5_OMR);
1756 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);
1757 break;
1758 }
1759
1760 return;
1761 }
1762
1763
1764
1765
1766 static void dc21140_autoconf(struct device *dev)
1767 {
1768 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1769 int iobase = dev->base_addr;
1770 u_long omr;
1771
1772 switch(lp->media) {
1773 case _100Mb:
1774 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1775 outl(omr | OMR_PS | OMR_HBD | OMR_PCS | OMR_SCR, DE4X5_OMR);
1776 outl(GEP_FDXD | GEP_MODE, DE4X5_GEP);
1777 break;
1778
1779 case _10Mb:
1780 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR));
1781 outl(omr | OMR_TTM, DE4X5_OMR);
1782 outl(GEP_FDXD, DE4X5_GEP);
1783 break;
1784 }
1785
1786 return;
1787 }
1788
1789 static long test_media(struct device *dev, long irqs, long irq_mask, long csr13, long csr14, long csr15, long msec)
1790 {
1791 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1792 int iobase = dev->base_addr;
1793 long sts, time, csr12;
1794
1795 reset_init_sia(dev, csr13, csr14, csr15);
1796
1797
1798 load_ms_timer(dev, msec);
1799
1800
1801 sts = inl(DE4X5_STS);
1802 outl(sts, DE4X5_STS);
1803
1804
1805 csr12 = inl(DE4X5_SISR);
1806 outl(csr12, DE4X5_SISR);
1807
1808
1809 do {
1810 time = inl(DE4X5_GPT) & GPT_VAL;
1811 sts = inl(DE4X5_STS);
1812 } while ((time != 0) && !(sts & irqs));
1813
1814 sts = inl(DE4X5_STS);
1815
1816 return sts;
1817 }
1818
1819
1820
1821
1822
1823 static long ping_media(struct device *dev)
1824 {
1825 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1826 int entry, iobase = dev->base_addr;
1827 char frame[64];
1828 long i, linkBad, omr;
1829 u_long t_3s = 3000;
1830
1831 create_packet(dev, frame, sizeof(frame));
1832
1833 entry = lp->tx_new;
1834 load_packet(dev, frame, TD_LS | TD_FS | sizeof(frame),NULL);
1835
1836 omr = inl(DE4X5_OMR);
1837 outl(omr|OMR_ST, DE4X5_OMR);
1838
1839 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1840 lp->tx_old = lp->tx_new;
1841
1842
1843 for (linkBad=1,i=0;(i<t_3s) && linkBad;i++) {
1844 if ((inl(DE4X5_SISR) & SISR_NCR) == 1) break;
1845 if (lp->tx_ring[entry].status >= 0) linkBad=0;
1846 dce_ms_delay(1);
1847 }
1848 outl(omr, DE4X5_OMR);
1849
1850 return ((linkBad || (lp->tx_ring[entry].status & TD_ES)) ? 1 : 0);
1851 }
1852
1853
1854
1855
1856
1857 static int test_ans(struct device *dev, long irqs, long irq_mask, long msec)
1858 {
1859 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1860 int iobase = dev->base_addr;
1861 long sts, ans;
1862
1863 outl(irq_mask, DE4X5_IMR);
1864
1865
1866 load_ms_timer(dev, msec);
1867
1868
1869 sts = inl(DE4X5_STS);
1870 outl(sts, DE4X5_STS);
1871
1872
1873 do {
1874 ans = inl(DE4X5_SISR) & SISR_ANS;
1875 sts = inl(DE4X5_STS);
1876 } while (!(sts & irqs) && (ans ^ ANS_NWOK) != 0);
1877
1878 return ((sts & STS_LNP) && ((ans ^ ANS_NWOK) == 0) ? STS_LNP : 0);
1879 }
1880
1881
1882
1883
1884 static void reset_init_sia(struct device *dev, long sicr, long strr, long sigr)
1885 {
1886 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1887 int iobase = dev->base_addr;
1888
1889 RESET_SIA;
1890 outl(sigr, DE4X5_SIGR);
1891 outl(strr, DE4X5_STRR);
1892 outl(sicr, DE4X5_SICR);
1893
1894 return;
1895 }
1896
1897
1898
1899
1900 static void load_ms_timer(struct device *dev, u_long msec)
1901 {
1902 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
1903 int iobase = dev->base_addr;
1904
1905 outl((long)(msec * 10000)/2048, DE4X5_GPT);
1906
1907 return;
1908 }
1909
1910
1911
1912
1913 static void create_packet(struct device *dev, char *frame, int len)
1914 {
1915 int i;
1916 char *buf = frame;
1917
1918 for (i=0; i<ETH_ALEN; i++) {
1919 *buf++ = dev->dev_addr[i];
1920 }
1921 for (i=0; i<ETH_ALEN; i++) {
1922 *buf++ = dev->dev_addr[i];
1923 }
1924
1925 *buf++ = 0;
1926 *buf++ = 1;
1927
1928 return;
1929 }
1930
1931
1932
1933
1934 static void dce_us_delay(u_long usec)
1935 {
1936 udelay(usec);
1937
1938 return;
1939 }
1940
1941
1942
1943
1944 static void dce_ms_delay(u_long msec)
1945 {
1946 u_long i;
1947
1948 for (i=0; i<msec; i++) {
1949 dce_us_delay(1000);
1950 }
1951
1952 return;
1953 }
1954
1955
1956
1957
1958
1959 int EISA_signature(char *name, long eisa_id)
1960 {
1961 unsigned long i;
1962 char *signatures[] = DE4X5_SIGNATURE;
1963 char ManCode[DE4X5_STRLEN];
1964 union {
1965 long ID;
1966 char Id[4];
1967 } Eisa;
1968 int status = 0;
1969
1970 *name = '\0';
1971 Eisa.ID = inl(eisa_id);
1972
1973 ManCode[0]=(((Eisa.Id[0]>>2)&0x1f)+0x40);
1974 ManCode[1]=(((Eisa.Id[1]&0xe0)>>5)+((Eisa.Id[0]&0x03)<<3)+0x40);
1975 ManCode[2]=(((Eisa.Id[2]>>4)&0x0f)+0x30);
1976 ManCode[3]=((Eisa.Id[2]&0x0f)+0x30);
1977 ManCode[4]=(((Eisa.Id[3]>>4)&0x0f)+0x30);
1978 ManCode[5]='\0';
1979
1980 for (i=0;(*signatures[i] != '\0') && (*name == '\0');i++) {
1981 if (strstr(ManCode, signatures[i]) != NULL) {
1982 strcpy(name,ManCode);
1983 status = 1;
1984 }
1985 }
1986
1987 return status;
1988 }
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
2001
2002 static int DevicePresent(short aprom_addr)
2003 {
2004 union {
2005 struct {
2006 u_long a;
2007 u_long b;
2008 } llsig;
2009 char Sig[sizeof(long) << 1];
2010 } dev;
2011 char data;
2012 long i, j, tmp;
2013 short sigLength;
2014 int status = 0;
2015 struct bus_type *lp = &bus;
2016
2017 dev.llsig.a = ETH_PROM_SIG;
2018 dev.llsig.b = ETH_PROM_SIG;
2019 sigLength = sizeof(long) << 1;
2020
2021 if (lp->chipset == DC21040) {
2022 for (i=0,j=0;(j<sigLength) && (i<PROBE_LENGTH+sigLength-1);i++) {
2023 if (lp->bus == PCI) {
2024 while ((tmp = inl(aprom_addr)) < 0);
2025 data = (char)tmp;
2026 } else {
2027 data = inb(aprom_addr);
2028 }
2029 if (dev.Sig[j] == data) {
2030 j++;
2031 } else {
2032 if (data == dev.Sig[0]) {
2033 j=1;
2034 } else {
2035 j=0;
2036 }
2037 }
2038 }
2039
2040 if (j!=sigLength) {
2041 status = -ENODEV;
2042 }
2043
2044 } else {
2045 short *p = (short *)&lp->srom;
2046 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
2047 *p++ = srom_rd(aprom_addr, i);
2048 }
2049 }
2050
2051 return status;
2052 }
2053
2054 static int aprom_crc(struct device *dev)
2055 {
2056 int iobase = dev->base_addr;
2057 long i, k, tmp;
2058 unsigned short j,chksum;
2059 unsigned char status = 0;
2060 struct bus_type *lp = &bus;
2061
2062 for (i=0,k=0,j=0;j<3;j++) {
2063 k <<= 1 ;
2064 if (k > 0xffff) k-=0xffff;
2065
2066 if (lp->bus == PCI) {
2067 if (lp->chipset == DC21040) {
2068 while ((tmp = inl(DE4X5_APROM)) < 0);
2069 k += (u_char) tmp;
2070 dev->dev_addr[i++] = (u_char) tmp;
2071 while ((tmp = inl(DE4X5_APROM)) < 0);
2072 k += (u_short) (tmp << 8);
2073 dev->dev_addr[i++] = (u_char) tmp;
2074 } else {
2075 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2076 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
2077 }
2078 } else {
2079 k += (u_char) (tmp = inb(EISA_APROM));
2080 dev->dev_addr[i++] = (u_char) tmp;
2081 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
2082 dev->dev_addr[i++] = (u_char) tmp;
2083 }
2084
2085 if (k > 0xffff) k-=0xffff;
2086 }
2087 if (k == 0xffff) k=0;
2088
2089 if (lp->bus == PCI) {
2090 if (lp->chipset == DC21040) {
2091 while ((tmp = inl(DE4X5_APROM)) < 0);
2092 chksum = (u_char) tmp;
2093 while ((tmp = inl(DE4X5_APROM)) < 0);
2094 chksum |= (u_short) (tmp << 8);
2095 if (k != chksum) status = -1;
2096 }
2097 } else {
2098 chksum = (u_char) inb(EISA_APROM);
2099 chksum |= (u_short) (inb(EISA_APROM) << 8);
2100 if (k != chksum) status = -1;
2101 }
2102
2103
2104 return status;
2105 }
2106
2107
2108
2109
2110 static short srom_rd(u_short addr, u_char offset)
2111 {
2112 sendto_srom(SROM_RD | SROM_SR, addr);
2113
2114 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
2115 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
2116 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
2117
2118 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
2119 }
2120
2121 static void srom_latch(u_long command, u_short addr)
2122 {
2123 sendto_srom(command, addr);
2124 sendto_srom(command | DT_CLK, addr);
2125 sendto_srom(command, addr);
2126
2127 return;
2128 }
2129
2130 static void srom_command(u_long command, u_short addr)
2131 {
2132 srom_latch(command, addr);
2133 srom_latch(command, addr);
2134 srom_latch((command & 0x0000ff00) | DT_CS, addr);
2135
2136 return;
2137 }
2138
2139 static void srom_address(u_long command, u_short addr, u_char offset)
2140 {
2141 long i;
2142 char a;
2143
2144 a = (char)(offset << 2);
2145 for (i=0; i<6; i++, a <<= 1) {
2146 srom_latch(command | ((a < 0) ? DT_IN : 0), addr);
2147 }
2148 dce_us_delay(1);
2149
2150 i = (getfrom_srom(addr) >> 3) & 0x01;
2151 if (i != 0) {
2152 printk("Bad SROM address phase.....\n");
2153 }
2154
2155 return;
2156 }
2157
2158 static short srom_data(u_long command, u_short addr)
2159 {
2160 int i;
2161 short word = 0;
2162 long tmp;
2163
2164 for (i=0; i<16; i++) {
2165 sendto_srom(command | DT_CLK, addr);
2166 tmp = getfrom_srom(addr);
2167 sendto_srom(command, addr);
2168
2169 word = (word << 1) | ((tmp >> 3) & 0x01);
2170 }
2171
2172 sendto_srom(command & 0x0000ff00, addr);
2173
2174 return word;
2175 }
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192 static void sendto_srom(u_long command, u_short addr)
2193 {
2194 outl(command, addr);
2195 dce_us_delay(1);
2196
2197 return;
2198 }
2199
2200 static long getfrom_srom(u_short addr)
2201 {
2202 long tmp;
2203
2204 tmp = inl(addr);
2205 dce_us_delay(1);
2206
2207 return tmp;
2208 }
2209
2210 static char *build_setup_frame(struct device *dev, int mode)
2211 {
2212 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2213 int i;
2214 char *pa = lp->setup_frame;
2215
2216
2217 if (mode == ALL) {
2218 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
2219 }
2220
2221 if (lp->setup_f == HASH_PERF) {
2222 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
2223 *(pa + i) = dev->dev_addr[i];
2224 if (i & 0x01) pa += 2;
2225 }
2226 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
2227 } else {
2228 for (i=0; i<ETH_ALEN; i++) {
2229 *(pa + (i&1)) = dev->dev_addr[i];
2230 if (i & 0x01) pa += 4;
2231 }
2232 for (i=0; i<ETH_ALEN; i++) {
2233 *(pa + (i&1)) = (char) 0xff;
2234 if (i & 0x01) pa += 4;
2235 }
2236 }
2237
2238 return pa;
2239 }
2240
2241
2242
2243
2244
2245 static int de4x5_ioctl(struct device *dev, struct ifreq *rq, int cmd)
2246 {
2247 struct de4x5_private *lp = (struct de4x5_private *)dev->priv;
2248 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_data;
2249 int i, j, iobase = dev->base_addr, status = 0;
2250 u_long omr;
2251 union {
2252 unsigned char addr[(HASH_TABLE_LEN * ETH_ALEN)];
2253 unsigned short sval[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
2254 unsigned long lval[(HASH_TABLE_LEN * ETH_ALEN) >> 2];
2255 } tmp;
2256
2257 switch(ioc->cmd) {
2258 case DE4X5_GET_HWADDR:
2259 for (i=0; i<ETH_ALEN; i++) {
2260 tmp.addr[i] = dev->dev_addr[i];
2261 }
2262 ioc->len = ETH_ALEN;
2263 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2264
2265 break;
2266 case DE4X5_SET_HWADDR:
2267 if (suser()) {
2268 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
2269 for (i=0; i<ETH_ALEN; i++) {
2270 dev->dev_addr[i] = tmp.addr[i];
2271 }
2272 build_setup_frame(dev, PHYS_ADDR_ONLY);
2273
2274 while (set_bit(0, (void *)&dev->tbusy) != 0);
2275 if (lp->setup_f == HASH_PERF) {
2276 load_packet(dev, lp->setup_frame, TD_IC | HASH_F | TD_SET |
2277 SETUP_FRAME_LEN, NULL);
2278 } else {
2279 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
2280 SETUP_FRAME_LEN, NULL);
2281 }
2282 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
2283 outl(POLL_DEMAND, DE4X5_TPD);
2284 dev->tbusy = 0;
2285
2286 } else {
2287 status = -EPERM;
2288 }
2289
2290 break;
2291 case DE4X5_SET_PROM:
2292 if (suser()) {
2293 omr = inl(DE4X5_OMR);
2294 omr |= OMR_PR;
2295 outl(omr, DE4X5_OMR);
2296 } else {
2297 status = -EPERM;
2298 }
2299
2300 break;
2301 case DE4X5_CLR_PROM:
2302 if (suser()) {
2303 omr = inl(DE4X5_OMR);
2304 omr &= ~OMR_PR;
2305 outb(omr, DE4X5_OMR);
2306 } else {
2307 status = -EPERM;
2308 }
2309
2310 break;
2311 case DE4X5_SAY_BOO:
2312 printk("%s: Boo!\n", dev->name);
2313
2314 break;
2315 case DE4X5_GET_MCA:
2316 ioc->len = (HASH_TABLE_LEN >> 3);
2317 memcpy_tofs(ioc->data, lp->setup_frame, 192);
2318
2319 break;
2320 case DE4X5_SET_MCA:
2321 if (suser()) {
2322 if (ioc->len != HASH_TABLE_LEN) {
2323 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
2324 }
2325 set_multicast_list(dev, ioc->len, tmp.addr);
2326 } else {
2327 status = -EPERM;
2328 }
2329
2330 break;
2331 case DE4X5_CLR_MCA:
2332 if (suser()) {
2333 set_multicast_list(dev, 0, NULL);
2334 } else {
2335 status = -EPERM;
2336 }
2337
2338 break;
2339 case DE4X5_MCA_EN:
2340 if (suser()) {
2341 omr = inl(DE4X5_OMR);
2342 omr |= OMR_PM;
2343 outl(omr, DE4X5_OMR);
2344 } else {
2345 status = -EPERM;
2346 }
2347
2348 break;
2349 case DE4X5_GET_STATS:
2350 cli();
2351 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
2352 ioc->len = DE4X5_PKT_STAT_SZ;
2353 sti();
2354
2355 break;
2356 case DE4X5_CLR_STATS:
2357 if (suser()) {
2358 cli();
2359 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
2360 sti();
2361 } else {
2362 status = -EPERM;
2363 }
2364
2365 break;
2366 case DE4X5_GET_OMR:
2367 tmp.addr[0] = inl(DE4X5_OMR);
2368 memcpy_tofs(ioc->data, tmp.addr, 1);
2369
2370 break;
2371 case DE4X5_SET_OMR:
2372 if (suser()) {
2373 memcpy_fromfs(tmp.addr, ioc->data, 1);
2374 outl(tmp.addr[0], DE4X5_OMR);
2375 } else {
2376 status = -EPERM;
2377 }
2378
2379 break;
2380 case DE4X5_GET_REG:
2381 tmp.lval[0] = inl(DE4X5_STS);
2382 tmp.lval[1] = inl(DE4X5_BMR);
2383 tmp.lval[2] = inl(DE4X5_IMR);
2384 tmp.lval[3] = inl(DE4X5_OMR);
2385 tmp.lval[4] = inl(DE4X5_SISR);
2386 tmp.lval[5] = inl(DE4X5_SICR);
2387 tmp.lval[6] = inl(DE4X5_STRR);
2388 tmp.lval[7] = inl(DE4X5_SIGR);
2389 memcpy_tofs(ioc->data, tmp.addr, 32);
2390
2391 break;
2392
2393 #define DE4X5_DUMP 0x0f
2394
2395 case DE4X5_DUMP:
2396 j = 0;
2397 tmp.addr[j++] = dev->irq;
2398 for (i=0; i<ETH_ALEN; i++) {
2399 tmp.addr[j++] = dev->dev_addr[i];
2400 }
2401 tmp.addr[j++] = lp->rxRingSize;
2402 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
2403 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
2404
2405 for (i=0;i<lp->rxRingSize-1;i++){
2406 if (i < 3) {
2407 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2408 }
2409 }
2410 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
2411 for (i=0;i<lp->txRingSize-1;i++){
2412 if (i < 3) {
2413 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2414 }
2415 }
2416 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
2417
2418 for (i=0;i<lp->rxRingSize-1;i++){
2419 if (i < 3) {
2420 tmp.lval[j>>2] = (long)lp->rx_ring[i].buf; j+=4;
2421 }
2422 }
2423 tmp.lval[j>>2] = (long)lp->rx_ring[i].buf; j+=4;
2424 for (i=0;i<lp->txRingSize-1;i++){
2425 if (i < 3) {
2426 tmp.lval[j>>2] = (long)lp->tx_ring[i].buf; j+=4;
2427 }
2428 }
2429 tmp.lval[j>>2] = (long)lp->tx_ring[i].buf; j+=4;
2430
2431 for (i=0;i<lp->rxRingSize;i++){
2432 tmp.lval[j>>2] = lp->rx_ring[i].status; j+=4;
2433 }
2434 for (i=0;i<lp->txRingSize;i++){
2435 tmp.lval[j>>2] = lp->tx_ring[i].status; j+=4;
2436 }
2437
2438 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
2439 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
2440 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
2441 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
2442 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
2443 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
2444 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
2445 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
2446
2447 tmp.addr[j++] = lp->txRingSize;
2448 tmp.addr[j++] = dev->tbusy;
2449
2450 ioc->len = j;
2451 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
2452
2453 break;
2454 default:
2455 status = -EOPNOTSUPP;
2456 }
2457
2458 return status;
2459 }
2460
2461 #ifdef MODULE
2462 char kernel_version[] = UTS_RELEASE;
2463 static struct device thisDE4X5 = {
2464 " ",
2465 0, 0, 0, 0,
2466 0x2000, 10,
2467 0, 0, 0, NULL, de4x5_probe };
2468
2469 int io=0x000b;
2470 int irq=10;
2471
2472 int
2473 init_module(void)
2474 {
2475 thisDE4X5.base_addr=io;
2476 thisDE4X5.irq=irq;
2477 if (register_netdev(&thisDE4X5) != 0)
2478 return -EIO;
2479 return 0;
2480 }
2481
2482 void
2483 cleanup_module(void)
2484 {
2485 struct de4x5_private *lp = (struct de4x5_private *) thisDE4X5.priv;
2486
2487 if (MOD_IN_USE) {
2488 printk("%s: device busy, remove delayed\n",thisDE4X5.name);
2489 } else {
2490 release_region(thisDE4X5.base_addr, (lp->bus == PCI ?
2491 DE4X5_PCI_TOTAL_SIZE :
2492 DE4X5_EISA_TOTAL_SIZE));
2493 if (lp) {
2494 kfree_s(lp->rx_ring[0].buf, RX_BUFF_SZ * NUM_RX_DESC + ALIGN);
2495 }
2496 kfree_s(thisDE4X5.priv, sizeof(struct de4x5_private) + ALIGN);
2497 thisDE4X5.priv = NULL;
2498
2499 unregister_netdev(&thisDE4X5);
2500 }
2501 }
2502 #endif
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