This source file includes following definitions.
- ewrk3_probe
- ewrk3_hw_init
- ewrk3_open
- ewrk3_init
- ewrk3_queue_pkt
- ewrk3_interrupt
- ewrk3_rx
- ewrk3_tx
- ewrk3_close
- ewrk3_get_stats
- set_multicast_list
- SetMulticastFilter
- isa_probe
- eisa_probe
- alloc_device
- Read_EEPROM
- Write_EEPROM
- EthwrkSignature
- DevicePresent
- aprom_crc
- ewrk3_ioctl
- asc2hex
- init_module
- cleanup_module
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129 static const char *version = "ewrk3.c:v0.32 1/16/95 davies@wanton.lkg.dec.com\n";
130
131 #include <linux/module.h>
132
133 #include <stdarg.h>
134
135 #include <linux/kernel.h>
136 #include <linux/sched.h>
137 #include <linux/string.h>
138 #include <linux/ptrace.h>
139 #include <linux/errno.h>
140 #include <linux/ioport.h>
141 #include <linux/malloc.h>
142 #include <linux/interrupt.h>
143 #include <linux/netdevice.h>
144 #include <linux/etherdevice.h>
145 #include <linux/skbuff.h>
146 #include <linux/time.h>
147 #include <linux/types.h>
148 #include <linux/unistd.h>
149
150 #include <asm/bitops.h>
151 #include <asm/io.h>
152 #include <asm/dma.h>
153 #include <asm/segment.h>
154
155 #include "ewrk3.h"
156
157 #ifdef EWRK3_DEBUG
158 static int ewrk3_debug = EWRK3_DEBUG;
159 #else
160 static int ewrk3_debug = 1;
161 #endif
162
163 #ifndef PROBE_LENGTH
164 #define PROBE_LENGTH 32
165 #endif
166
167 #ifndef PROBE_SEQUENCE
168 #define PROBE_SEQUENCE "FF0055AAFF0055AA"
169 #endif
170
171 #ifndef EWRK3_SIGNATURE
172 #define EWRK3_SIGNATURE {"DE203","DE204","DE205",""}
173 #define EWRK3_NAME_LENGTH 8
174 #endif
175
176 #ifndef EWRK3_RAM_BASE_ADDRESSES
177 #define EWRK3_RAM_BASE_ADDRESSES {0xc0000,0xd0000,0x00000}
178 #endif
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194 #define EWRK3_IO_BASE 0x100
195 #define EWRK3_IOP_INC 0x20
196 #define EWRK3_TOTAL_SIZE 0x20
197 #define EWRK3_IO_SEARCH 0x007dff7f
198 static long mem_chkd = EWRK3_IO_SEARCH;
199
200
201 #ifndef MAX_NUM_EWRK3S
202 #define MAX_NUM_EWRK3S 21
203 #endif
204
205 #ifndef EWRK3_EISA_IO_PORTS
206 #define EWRK3_EISA_IO_PORTS 0x0c00
207 #endif
208
209 #ifndef MAX_EISA_SLOTS
210 #define MAX_EISA_SLOTS 8
211 #define EISA_SLOT_INC 0x1000
212 #endif
213
214 #define CRC_POLYNOMIAL_BE 0x04c11db7UL
215 #define CRC_POLYNOMIAL_LE 0xedb88320UL
216
217
218
219
220 #define IO_ONLY 0x00
221 #define SHMEM_2K 0x800
222 #define SHMEM_32K 0x8000
223 #define SHMEM_64K 0x10000
224
225
226
227
228 static unsigned char irq_mask = TNEM|TXDM|RNEM|RXDM;
229
230 #define ENABLE_IRQs \
231 icr |= irq_mask;\
232 outb(icr, EWRK3_ICR)
233
234 #define DISABLE_IRQs \
235 icr = inb(EWRK3_ICR);\
236 icr &= ~irq_mask;\
237 outb(icr, EWRK3_ICR)
238
239
240
241
242 #define START_EWRK3 \
243 csr = inb(EWRK3_CSR);\
244 csr &= ~(TXD|RXD);\
245 outb(csr, EWRK3_CSR)
246
247 #define STOP_EWRK3 \
248 csr = (TXD|RXD);\
249 outb(csr, EWRK3_CSR)
250
251
252
253
254 #define EWRK3_PKT_STAT_SZ 16
255 #define EWRK3_PKT_BIN_SZ 128
256
257
258 struct ewrk3_private {
259 long shmem_base;
260 long shmem_length;
261 struct enet_statistics stats;
262 struct {
263 unsigned long bins[EWRK3_PKT_STAT_SZ];
264 unsigned long unicast;
265 unsigned long multicast;
266 unsigned long broadcast;
267 unsigned long excessive_collisions;
268 unsigned long tx_underruns;
269 unsigned long excessive_underruns;
270 } pktStats;
271 short mPage;
272 unsigned char lemac;
273 unsigned char hard_strapped;
274 unsigned char lock;
275 unsigned char txc;
276 };
277
278
279
280
281 #define FORCE_2K_MODE \
282 shmem_length = SHMEM_2K;\
283 outb(((mem_start - 0x80000) >> 11), EWRK3_MBR)
284
285
286
287
288 static int ewrk3_open(struct device *dev);
289 static int ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev);
290 static void ewrk3_interrupt(int irq, struct pt_regs *regs);
291 static int ewrk3_close(struct device *dev);
292 static struct enet_statistics *ewrk3_get_stats(struct device *dev);
293 static void set_multicast_list(struct device *dev, int num_addrs, void *addrs);
294 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd);
295
296
297
298
299 static int ewrk3_hw_init(struct device *dev, short iobase);
300 static void ewrk3_init(struct device *dev);
301 static int ewrk3_rx(struct device *dev);
302 static int ewrk3_tx(struct device *dev);
303
304 static void EthwrkSignature(char * name, char *eeprom_image);
305 static int DevicePresent(short iobase);
306 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table);
307
308 static int Read_EEPROM(short iobase, unsigned char eaddr);
309 static int Write_EEPROM(short data, short iobase, unsigned char eaddr);
310 static unsigned char aprom_crc (struct device *dev, unsigned char *eeprom_image, char chipType);
311
312 #ifndef MODULE
313 static struct device *isa_probe(struct device *dev);
314 static struct device *eisa_probe(struct device *dev);
315 static struct device *alloc_device(struct device *dev, int iobase);
316
317 static int num_ewrk3s = 0, num_eth = 0;
318 static unsigned char irq[] = {5,0,10,3,11,9,15,12};
319
320 #else
321 int init_module(void);
322 void cleanup_module(void);
323
324 #endif
325
326 static int autoprobed = 0;
327
328
329
330
331 #define INIT_EWRK3 {\
332 int i;\
333 outb(EEPROM_INIT, EWRK3_IOPR);\
334 for (i=0;i<5000;i++) inb(EWRK3_CSR);\
335 }
336
337
338
339
340 int ewrk3_probe(struct device *dev)
341 {
342 int base_addr = dev->base_addr;
343 int status = -ENODEV;
344 #ifndef MODULE
345 struct device *eth0;
346 #endif
347
348 if (base_addr > 0x0ff) {
349 if (!autoprobed) {
350 if (!check_region(base_addr, EWRK3_TOTAL_SIZE)) {
351 if (((mem_chkd >> ((base_addr - EWRK3_IO_BASE)/ EWRK3_IOP_INC))&0x01)==1) {
352 if (DevicePresent(base_addr) == 0) {
353
354 request_region(base_addr, EWRK3_IOP_INC, "ewrk3");
355 status = ewrk3_hw_init(dev, base_addr);
356 } else {
357 printk("ewrk3_probe(): No device found\n");
358 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
359 }
360 }
361 } else {
362 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, base_addr);
363 mem_chkd &= ~(0x01 << ((base_addr - EWRK3_IO_BASE)/EWRK3_IOP_INC));
364 }
365 } else {
366 status = ewrk3_hw_init(dev, base_addr);
367 }
368 } else if (base_addr > 0) {
369 status = -ENXIO;
370
371 #ifdef MODULE
372 } else {
373 printk("Autoprobing is not supported when loading a module based driver.\n");
374 status = -EIO;
375 #else
376 } else if (!autoprobed) {
377
378 eth0=isa_probe(dev);
379 eth0=eisa_probe(eth0);
380 if (dev->priv) status=0;
381 autoprobed = 1;
382 } else {
383 status = -ENXIO;
384 #endif
385
386 }
387
388 if (status) dev->base_addr = base_addr;
389
390 return status;
391 }
392
393 static int
394 ewrk3_hw_init(struct device *dev, short iobase)
395 {
396 struct ewrk3_private *lp;
397 int i, status=0;
398 unsigned long mem_start, shmem_length;
399 char name[EWRK3_NAME_LENGTH + 1];
400 unsigned char cr, cmr, icr, nicsr, lemac, hard_strapped = 0;
401 unsigned char eeprom_image[EEPROM_MAX], chksum, eisa_cr = 0;
402
403
404
405
406
407 if (iobase > 0x400) eisa_cr = inb(EISA_CR);
408 INIT_EWRK3;
409
410 nicsr = inb(EWRK3_CSR);
411
412
413
414
415 DISABLE_IRQs;
416
417 if (nicsr == (TXD|RXD)) {
418
419
420
421
422 for (chksum=0, i=0; i<EEPROM_MAX; i+=2) {
423 union {
424 short val;
425 char c[2];
426 } tmp;
427
428 tmp.val = (short)Read_EEPROM(iobase, (i>>1));
429 eeprom_image[i] = tmp.c[0];
430 eeprom_image[i+1] = tmp.c[1];
431
432 chksum += eeprom_image[i] + eeprom_image[i+1];
433 }
434
435 if (chksum != 0) {
436 printk("%s: Device has a bad on-board EEPROM.\n", dev->name);
437 status = -ENXIO;
438 } else {
439
440
441
442 EthwrkSignature(name, eeprom_image);
443
444 if (*name != '\0') {
445 dev->base_addr = iobase;
446
447 if (iobase > 0x400) {
448 outb(eisa_cr, EISA_CR);
449 }
450
451 lemac = eeprom_image[EEPROM_CHIPVER];
452 cmr = inb(EWRK3_CMR);
453
454 if (((lemac == LeMAC) && ((cmr & NO_EEPROM) != NO_EEPROM)) ||
455 ((lemac == LeMAC2) && !(cmr & HS))) {
456 printk("%s: %s at %#3x", dev->name, name, iobase);
457 hard_strapped = 1;
458 } else if ((iobase&0x0fff)==EWRK3_EISA_IO_PORTS) {
459
460 printk("%s: %s at %#3x (EISA slot %d)",
461 dev->name, name, iobase, ((iobase>>12)&0x0f));
462 } else {
463 printk("%s: %s at %#3x", dev->name, name, iobase);
464 }
465
466 if (!status) {
467 printk(", h/w address ");
468 if (lemac == LeMAC2) {
469 for (i = 0;i < ETH_ALEN - 1;i++) {
470 printk("%2.2x:", dev->dev_addr[i] =
471 eeprom_image[EEPROM_PADDR0 + i]);
472 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
473 }
474 printk("%2.2x,\n",dev->dev_addr[i] = eeprom_image[EEPROM_PADDR0 + i]);
475 outb(eeprom_image[EEPROM_PADDR0 + i], EWRK3_PAR0 + i);
476 } else {
477 DevicePresent(iobase);
478 for (i = 0; i < ETH_ALEN - 1; i++) {
479 printk("%2.2x:", dev->dev_addr[i] = inb(EWRK3_APROM));
480 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
481 }
482 printk("%2.2x,\n", dev->dev_addr[i] = inb(EWRK3_APROM));
483 outb(dev->dev_addr[i], EWRK3_PAR0 + i);
484 }
485
486 if (aprom_crc(dev, eeprom_image, lemac)) {
487 printk(" which has an EEPROM CRC error.\n");
488 status = -ENXIO;
489 } else {
490 if (lemac == LeMAC2) {
491 cmr &= ~(RA | WB | LINK | POLARITY | _0WS);
492 if (eeprom_image[EEPROM_MISC0] & READ_AHEAD) cmr |= RA;
493 if (eeprom_image[EEPROM_MISC0] & WRITE_BEHIND) cmr |= WB;
494 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_POL) cmr |= POLARITY;
495 if (eeprom_image[EEPROM_NETMAN0] & NETMAN_LINK) cmr |= LINK;
496 if (eeprom_image[EEPROM_MISC0] & _0WS_ENA) cmr |= _0WS;
497 }
498 if (eeprom_image[EEPROM_SETUP] & SETUP_DRAM) cmr |= DRAM;
499 outb(cmr, EWRK3_CMR);
500
501 cr = inb(EWRK3_CR);
502 cr |= eeprom_image[EEPROM_SETUP] & SETUP_APD;
503 if (cr & SETUP_APD) cr |= eeprom_image[EEPROM_SETUP] & SETUP_PS;
504 cr |= eeprom_image[EEPROM_MISC0] & FAST_BUS;
505 cr |= eeprom_image[EEPROM_MISC0] & ENA_16;
506 outb(cr, EWRK3_CR);
507
508
509
510
511
512 mem_start = inb(EWRK3_MBR);
513 shmem_length = 0;
514 if (mem_start != 0) {
515 if ((mem_start >= 0x0a) && (mem_start <= 0x0f)) {
516 mem_start *= SHMEM_64K;
517 shmem_length = SHMEM_64K;
518 } else if ((mem_start >= 0x14) && (mem_start <= 0x1f)) {
519 mem_start *= SHMEM_32K;
520 shmem_length = SHMEM_32K;
521 } else if ((mem_start >= 0x40) && (mem_start <= 0xff)) {
522 mem_start = mem_start * SHMEM_2K + 0x80000;
523 shmem_length = SHMEM_2K;
524 } else {
525 status = -ENXIO;
526 }
527 }
528
529
530
531
532
533
534
535 if (!status) {
536 if (hard_strapped) {
537 printk(" is hard strapped.\n");
538 } else if (mem_start) {
539 printk(" has a %dk RAM window", (int)(shmem_length >> 10));
540 printk(" at 0x%.5lx", mem_start);
541 } else {
542 printk(" is in I/O only mode");
543 }
544
545
546 dev->priv = (void *) kmalloc(sizeof(struct ewrk3_private),
547 GFP_KERNEL);
548 if (dev->priv == NULL)
549 return -ENOMEM;
550 lp = (struct ewrk3_private *)dev->priv;
551 memset(dev->priv, 0, sizeof(struct ewrk3_private));
552 lp->shmem_base = mem_start;
553 lp->shmem_length = shmem_length;
554 lp->lemac = lemac;
555 lp->hard_strapped = hard_strapped;
556
557 lp->mPage = 64;
558 if (cmr & DRAM) lp->mPage <<= 1 ;
559
560 if (!hard_strapped) {
561
562
563
564 icr |= IE;
565 outb(icr, EWRK3_ICR);
566
567
568 dev->dma = 0;
569
570
571
572 if (dev->irq < 2) {
573 #ifndef MODULE
574 unsigned char irqnum;
575
576 autoirq_setup(0);
577
578
579
580
581 icr |=TNEM;
582 outb(1,EWRK3_TDQ);
583 outb(icr, EWRK3_ICR);
584
585 irqnum = irq[((icr & IRQ_SEL) >> 4)];
586
587 dev->irq = autoirq_report(1);
588 if ((dev->irq) && (irqnum == dev->irq)) {
589 printk(" and uses IRQ%d.\n", dev->irq);
590 } else {
591 if (!dev->irq) {
592 printk(" and failed to detect IRQ line.\n");
593 } else if ((irqnum == 1) && (lemac == LeMAC2)) {
594 printk(" and an illegal IRQ line detected.\n");
595 } else {
596 printk(", but incorrect IRQ line detected.\n");
597 }
598 status = -ENXIO;
599 }
600
601 DISABLE_IRQs;
602
603 #endif
604 } else {
605 printk(" and requires IRQ%d.\n", dev->irq);
606 }
607 }
608 } else {
609 status = -ENXIO;
610 }
611 }
612 }
613 } else {
614 status = -ENXIO;
615 }
616 }
617
618 if (!status) {
619 if (ewrk3_debug > 0) {
620 printk(version);
621 }
622
623
624 dev->open = &ewrk3_open;
625 dev->hard_start_xmit = &ewrk3_queue_pkt;
626 dev->stop = &ewrk3_close;
627 dev->get_stats = &ewrk3_get_stats;
628 #ifdef HAVE_MULTICAST
629 dev->set_multicast_list = &set_multicast_list;
630 #endif
631 dev->do_ioctl = &ewrk3_ioctl;
632
633 dev->mem_start = 0;
634
635
636 ether_setup(dev);
637 }
638 } else {
639 status = -ENXIO;
640 }
641
642 return status;
643 }
644
645
646 static int
647 ewrk3_open(struct device *dev)
648 {
649 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
650 int i, iobase = dev->base_addr;
651 int status = 0;
652 unsigned char icr, csr;
653
654
655
656
657 STOP_EWRK3;
658
659 if (!lp->hard_strapped) {
660 if (request_irq(dev->irq, &ewrk3_interrupt, 0, "ewrk3")) {
661 printk("ewrk3_open(): Requested IRQ%d is busy\n",dev->irq);
662 status = -EAGAIN;
663 } else {
664
665 irq2dev_map[dev->irq] = dev;
666
667
668
669
670 ewrk3_init(dev);
671
672 if (ewrk3_debug > 1){
673 printk("%s: ewrk3 open with irq %d\n",dev->name,dev->irq);
674 printk("\tphysical address: ");
675 for (i=0;i<6;i++){
676 printk("%2.2x:",(short)dev->dev_addr[i]);
677 }
678 printk("\n");
679 printk("\tchecked memory: 0x%08lx\n",mem_chkd);
680 if (lp->shmem_length == 0) {
681 printk("\tno shared memory, I/O only mode\n");
682 } else {
683 printk("\tstart of shared memory: 0x%08lx\n",lp->shmem_base);
684 printk("\twindow length: 0x%04lx\n",lp->shmem_length);
685 }
686 printk("\t# of DRAMS: %d\n",((inb(EWRK3_CMR) & 0x02) ? 2 : 1));
687 printk("\tcsr: 0x%02x\n", inb(EWRK3_CSR));
688 printk("\tcr: 0x%02x\n", inb(EWRK3_CR));
689 printk("\ticr: 0x%02x\n", inb(EWRK3_ICR));
690 printk("\tcmr: 0x%02x\n", inb(EWRK3_CMR));
691 printk("\tfmqc: 0x%02x\n", inb(EWRK3_FMQC));
692 }
693
694 dev->tbusy = 0;
695 dev->start = 1;
696 dev->interrupt = UNMASK_INTERRUPTS;
697
698
699
700
701 icr = inb(EWRK3_ICR);
702 ENABLE_IRQs;
703
704 }
705 } else {
706 dev->start = 0;
707 dev->tbusy = 1;
708 printk("%s: ewrk3 available for hard strapped set up only.\n", dev->name);
709 printk(" Run the 'ewrk3setup' utility or remove the hard straps.\n");
710 }
711
712 MOD_INC_USE_COUNT;
713
714 return status;
715 }
716
717
718
719
720 static void
721 ewrk3_init(struct device *dev)
722 {
723 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
724 char csr, page;
725 short iobase = dev->base_addr;
726
727
728
729
730 set_multicast_list(dev, HASH_TABLE_LEN, NULL);
731
732
733
734
735 while (inb(EWRK3_TQ));
736 while (inb(EWRK3_TDQ));
737 while (inb(EWRK3_RQ));
738 while (inb(EWRK3_FMQ));
739
740
741
742
743 for (page=1;page<lp->mPage;page++) {
744 outb(page, EWRK3_FMQ);
745 }
746
747 lp->lock = 0;
748
749 START_EWRK3;
750 }
751
752
753
754
755 static int
756 ewrk3_queue_pkt(struct sk_buff *skb, struct device *dev)
757 {
758 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
759 int iobase = dev->base_addr;
760 int status = 0;
761 unsigned char icr, csr;
762
763
764 if (dev->tbusy || lp->lock) {
765 int tickssofar = jiffies - dev->trans_start;
766 if (tickssofar < 10) {
767 status = -1;
768 } else if (!lp->hard_strapped) {
769 printk("%s: transmit timed/locked out, status %04x, resetting.\n",
770 dev->name, inb(EWRK3_CSR));
771
772
773
774
775 DISABLE_IRQs;
776
777
778
779
780 STOP_EWRK3;
781
782 ewrk3_init(dev);
783
784
785
786
787 ENABLE_IRQs;
788
789 dev->tbusy=0;
790 dev->trans_start = jiffies;
791 }
792 } else if (skb == NULL) {
793 dev_tint(dev);
794 } else if (skb->len > 0) {
795
796
797
798
799
800 if (set_bit(0, (void*)&dev->tbusy) != 0)
801 printk("%s: Transmitter access conflict.\n", dev->name);
802
803 DISABLE_IRQs;
804
805
806
807
808 if (inb(EWRK3_FMQC) > 0) {
809 unsigned char *buf;
810 unsigned char page;
811
812 if ((page = inb(EWRK3_FMQ)) < lp->mPage) {
813 buf = NULL;
814
815
816
817
818 while (set_bit(0, (void *)&lp->lock) != 0);
819 if (lp->shmem_length == IO_ONLY) {
820 outb(page, EWRK3_IOPR);
821 } else if (lp->shmem_length == SHMEM_2K) {
822 buf = (char *) lp->shmem_base;
823 outb(page, EWRK3_MPR);
824 } else if (lp->shmem_length == SHMEM_32K) {
825 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
826 outb((page >> 4), EWRK3_MPR);
827 } else if (lp->shmem_length == SHMEM_64K) {
828 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
829 outb((page >> 5), EWRK3_MPR);
830 } else {
831 status = -1;
832 printk("%s: Oops - your private data area is hosed!\n",dev->name);
833 }
834
835 if (!status) {
836
837
838
839
840
841
842 if (lp->shmem_length == IO_ONLY) {
843 int i;
844 unsigned char *p = skb->data;
845
846 outb((char)(QMODE | PAD | IFC), EWRK3_DATA);
847 outb((char)(skb->len & 0xff), EWRK3_DATA);
848 outb((char)((skb->len >> 8) & 0xff), EWRK3_DATA);
849 outb((char)0x04, EWRK3_DATA);
850 for (i=0; i<skb->len; i++) {
851 outb(*p++, EWRK3_DATA);
852 }
853 outb(page, EWRK3_TQ);
854 } else {
855 *buf++ = (char)(QMODE | PAD | IFC);
856 *buf++ = (char)(skb->len & 0xff);
857 if (lp->txc) {
858 *buf++ = (char)(((skb->len >> 8) & 0xff) | XCT);
859 *buf++ = 0x04;
860 *(buf + skb->len) = 0x00;
861 memcpy(buf, skb->data, PRELOAD);
862 outb(page, EWRK3_TQ);
863 memcpy(buf + PRELOAD, skb->data + PRELOAD, skb->len - PRELOAD);
864 *(buf + skb->len) = 0xff;
865 } else {
866 *buf++ = (char)((skb->len >> 8) & 0xff);
867 *buf++ = 0x04;
868 memcpy(buf, skb->data, skb->len);
869 outb(page, EWRK3_TQ);
870 }
871 }
872
873 dev->trans_start = jiffies;
874
875 dev_kfree_skb (skb, FREE_WRITE);
876
877 } else {
878 outb(page, EWRK3_FMQ);
879 }
880 lp->lock = 0;
881 } else {
882 printk("ewrk3_queue_pkt(): Invalid free memory page (%d).\n",
883 (unsigned char) page);
884 }
885 } else {
886 printk("ewrk3_queue_pkt(): No free resources...\n");
887 printk("ewrk3_queue_pkt(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
888 }
889
890
891 if (inb(EWRK3_FMQC) > 0) {
892 dev->tbusy = 0;
893 }
894
895 ENABLE_IRQs;
896 }
897
898 return status;
899 }
900
901
902
903
904 static void
905 ewrk3_interrupt(int irq, struct pt_regs * regs)
906 {
907 struct device *dev = (struct device *)(irq2dev_map[irq]);
908 struct ewrk3_private *lp;
909 int iobase;
910 unsigned char icr, cr, csr;
911
912 if (dev == NULL) {
913 printk ("ewrk3_interrupt(): irq %d for unknown device.\n", irq);
914 } else {
915 lp = (struct ewrk3_private *)dev->priv;
916 iobase = dev->base_addr;
917
918 if (dev->interrupt)
919 printk("%s: Re-entering the interrupt handler.\n", dev->name);
920
921 dev->interrupt = MASK_INTERRUPTS;
922
923
924 csr = inb(EWRK3_CSR);
925
926
927
928
929 DISABLE_IRQs;
930
931 cr = inb(EWRK3_CR);
932 cr |= LED;
933 outb(cr, EWRK3_CR);
934
935 if (csr & RNE)
936 ewrk3_rx(dev);
937
938 if (csr & TNE)
939 ewrk3_tx(dev);
940
941
942
943
944
945
946
947 if (inb(EWRK3_FMQC)) {
948 irq_mask |= TXDM|RXDM;
949 csr &= ~(TXD|RXD);
950 outb(csr, EWRK3_CSR);
951 dev->tbusy = 0;
952 mark_bh(NET_BH);
953 } else {
954 irq_mask &= ~(TXDM|RXDM);
955 }
956
957
958 cr &= ~LED;
959 outb(cr, EWRK3_CR);
960
961 dev->interrupt = UNMASK_INTERRUPTS;
962
963 ENABLE_IRQs;
964 }
965
966 return;
967 }
968
969 static int
970 ewrk3_rx(struct device *dev)
971 {
972 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
973 int i, iobase = dev->base_addr;
974 unsigned char page, tmpPage = 0, tmpLock = 0, *buf;
975 int status = 0;
976
977 while (inb(EWRK3_RQC) && !status) {
978 if ((page = inb(EWRK3_RQ)) < lp->mPage) {
979 buf = NULL;
980
981
982
983
984
985 if ((tmpLock = set_bit(0, (void *)&lp->lock)) == 1) {
986 if (lp->shmem_length == IO_ONLY) {
987 tmpPage = inb(EWRK3_IOPR);
988 } else {
989 tmpPage = inb(EWRK3_MPR);
990 }
991 }
992
993
994
995
996 if (lp->shmem_length == IO_ONLY) {
997 outb(page, EWRK3_IOPR);
998 } else if (lp->shmem_length == SHMEM_2K) {
999 buf = (char *) lp->shmem_base;
1000 outb(page, EWRK3_MPR);
1001 } else if (lp->shmem_length == SHMEM_32K) {
1002 buf = (char *)((((short)page << 11) & 0x7800) + lp->shmem_base);
1003 outb((page >> 4), EWRK3_MPR);
1004 } else if (lp->shmem_length == SHMEM_64K) {
1005 buf = (char *)((((short)page << 11) & 0xf800) + lp->shmem_base);
1006 outb((page >> 5), EWRK3_MPR);
1007 } else {
1008 status = -1;
1009 printk("%s: Oops - your private data area is hosed!\n",dev->name);
1010 }
1011
1012 if (!status) {
1013 char rx_status;
1014 int pkt_len;
1015
1016 if (lp->shmem_length == IO_ONLY) {
1017 rx_status = inb(EWRK3_DATA);
1018 pkt_len = inb(EWRK3_DATA);
1019 pkt_len |= ((unsigned short)inb(EWRK3_DATA) << 8);
1020 } else {
1021 rx_status = (char)(*buf++);
1022 pkt_len = (short)(*buf+((*(buf+1))<<8));
1023 buf+=3;
1024 }
1025
1026 if (!(rx_status & ROK)) {
1027 lp->stats.rx_errors++;
1028 if (rx_status & DBE) lp->stats.rx_frame_errors++;
1029 if (rx_status & CRC) lp->stats.rx_crc_errors++;
1030 if (rx_status & PLL) lp->stats.rx_fifo_errors++;
1031 } else {
1032 struct sk_buff *skb;
1033
1034 if ((skb = dev_alloc_skb(pkt_len+2)) != NULL) {
1035 unsigned char *p;
1036 skb->dev = dev;
1037 skb_reserve(skb,2);
1038 p = skb_put(skb,pkt_len);
1039
1040 if (lp->shmem_length == IO_ONLY) {
1041 *p = inb(EWRK3_DATA);
1042 for (i=0; i<pkt_len; i++) {
1043 *p++ = inb(EWRK3_DATA);
1044 }
1045 } else {
1046 memcpy(p, buf, pkt_len);
1047 }
1048
1049
1050
1051
1052
1053
1054 skb->protocol=eth_type_trans(skb,dev);
1055 netif_rx(skb);
1056
1057
1058
1059
1060 lp->stats.rx_packets++;
1061 for (i=1; i<EWRK3_PKT_STAT_SZ-1; i++) {
1062 if (pkt_len < i*EWRK3_PKT_BIN_SZ) {
1063 lp->pktStats.bins[i]++;
1064 i = EWRK3_PKT_STAT_SZ;
1065 }
1066 }
1067 buf = skb->data;
1068 if (buf[0] & 0x01) {
1069 if ((*(long *)&buf[0] == -1) && (*(short *)&buf[4] == -1)) {
1070 lp->pktStats.broadcast++;
1071 } else {
1072 lp->pktStats.multicast++;
1073 }
1074 } else if ((*(long *)&buf[0] == *(long *)&dev->dev_addr[0]) &&
1075 (*(short *)&buf[4] == *(short *)&dev->dev_addr[4])) {
1076 lp->pktStats.unicast++;
1077 }
1078
1079 lp->pktStats.bins[0]++;
1080 if (lp->pktStats.bins[0] == 0) {
1081 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1082 }
1083 } else {
1084 printk("%s: Insufficient memory; nuking packet.\n", dev->name);
1085 lp->stats.rx_dropped++;
1086 break;
1087 }
1088 }
1089 }
1090
1091
1092
1093 outb(page, EWRK3_FMQ);
1094
1095 if (tmpLock) {
1096 if (lp->shmem_length == IO_ONLY) {
1097 outb(tmpPage, EWRK3_IOPR);
1098 } else {
1099 outb(tmpPage, EWRK3_MPR);
1100 }
1101 }
1102 lp->lock = 0;
1103 } else {
1104 printk("ewrk3_rx(): Illegal page number, page %d\n",page);
1105 printk("ewrk3_rx(): CSR: %02x ICR: %02x FMQC: %02x\n",inb(EWRK3_CSR),inb(EWRK3_ICR),inb(EWRK3_FMQC));
1106 }
1107 }
1108 return status;
1109 }
1110
1111
1112
1113
1114 static int
1115 ewrk3_tx(struct device *dev)
1116 {
1117 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1118 int iobase = dev->base_addr;
1119 unsigned char tx_status;
1120
1121 while ((tx_status = inb(EWRK3_TDQ)) > 0) {
1122 if (tx_status & VSTS) {
1123 if (tx_status & MAC_TXE) {
1124 lp->stats.tx_errors++;
1125 if (tx_status & MAC_NCL) lp->stats.tx_carrier_errors++;
1126 if (tx_status & MAC_LCL) lp->stats.tx_window_errors++;
1127 if (tx_status & MAC_CTU) {
1128 if ((tx_status & MAC_COLL) ^ MAC_XUR) {
1129 lp->pktStats.tx_underruns++;
1130 } else {
1131 lp->pktStats.excessive_underruns++;
1132 }
1133 } else if (tx_status & MAC_COLL) {
1134 if ((tx_status & MAC_COLL) ^ MAC_XCOLL) {
1135 lp->stats.collisions++;
1136 } else {
1137 lp->pktStats.excessive_collisions++;
1138 }
1139 }
1140 } else {
1141 lp->stats.tx_packets++;
1142 }
1143 }
1144 }
1145
1146 return 0;
1147 }
1148
1149 static int
1150 ewrk3_close(struct device *dev)
1151 {
1152 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1153 int iobase = dev->base_addr;
1154 unsigned char icr, csr;
1155
1156 dev->start = 0;
1157 dev->tbusy = 1;
1158
1159 if (ewrk3_debug > 1) {
1160 printk("%s: Shutting down ethercard, status was %2.2x.\n",
1161 dev->name, inb(EWRK3_CSR));
1162 }
1163
1164
1165
1166
1167 DISABLE_IRQs;
1168
1169 STOP_EWRK3;
1170
1171
1172
1173
1174
1175
1176
1177 while (inb(EWRK3_TQ));
1178 while (inb(EWRK3_TDQ));
1179 while (inb(EWRK3_RQ));
1180
1181 if (!lp->hard_strapped) {
1182 free_irq(dev->irq);
1183
1184 irq2dev_map[dev->irq] = 0;
1185 }
1186
1187 MOD_DEC_USE_COUNT;
1188
1189 return 0;
1190 }
1191
1192 static struct enet_statistics *
1193 ewrk3_get_stats(struct device *dev)
1194 {
1195 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1196
1197
1198
1199 return &lp->stats;
1200 }
1201
1202
1203
1204
1205
1206
1207
1208
1209 static void
1210 set_multicast_list(struct device *dev, int num_addrs, void *addrs)
1211 {
1212 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1213 int iobase = dev->base_addr;
1214 char *multicast_table;
1215 unsigned char csr;
1216
1217 csr = inb(EWRK3_CSR);
1218
1219 if (lp->shmem_length == IO_ONLY) {
1220 multicast_table = (char *) PAGE0_HTE;
1221 } else {
1222 multicast_table = (char *)(lp->shmem_base + PAGE0_HTE);
1223 }
1224
1225 if (num_addrs >= 0) {
1226 SetMulticastFilter(dev, num_addrs, (char *)addrs, multicast_table);
1227 csr &= ~PME;
1228 csr |= MCE;
1229 outb(csr, EWRK3_CSR);
1230 } else {
1231 csr |= PME;
1232 csr &= ~MCE;
1233 outb(csr, EWRK3_CSR);
1234 }
1235 }
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245 static void SetMulticastFilter(struct device *dev, int num_addrs, char *addrs, char *multicast_table)
1246 {
1247 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1248 int i, iobase = dev->base_addr;
1249 char j, bit, byte;
1250 short *p = (short *) multicast_table;
1251 u_short hashcode;
1252 u_long crc, poly = CRC_POLYNOMIAL_LE;
1253
1254 while (set_bit(0, (void *)&lp->lock) != 0);
1255
1256 if (lp->shmem_length == IO_ONLY) {
1257 outb(0, EWRK3_IOPR);
1258 outw((short)((long)multicast_table), EWRK3_PIR1);
1259 } else {
1260 outb(0, EWRK3_MPR);
1261 }
1262
1263 if (num_addrs == HASH_TABLE_LEN) {
1264 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1265 if (lp->shmem_length == IO_ONLY) {
1266 outb(0xff, EWRK3_DATA);
1267 } else {
1268 *p++ = 0xffff;
1269 i++;
1270 }
1271 }
1272 } else {
1273
1274 if (lp->shmem_length == IO_ONLY) {
1275 for (i=0; i<(HASH_TABLE_LEN >> 4) - 1; i++) {
1276 outb(0x00, EWRK3_DATA);
1277 }
1278 outb(0x80, EWRK3_DATA); i++;
1279 for (; i<(HASH_TABLE_LEN >> 3); i++) {
1280 outb(0x00, EWRK3_DATA);
1281 }
1282 } else {
1283 memset(multicast_table, 0, (HASH_TABLE_LEN >> 3));
1284 *(multicast_table + (HASH_TABLE_LEN >> 4) - 1) = 0x80;
1285 }
1286
1287
1288 for (i=0;i<num_addrs;i++) {
1289 if ((*addrs & 0x01) == 1) {
1290 crc = 0xffffffff;
1291 for (byte=0;byte<ETH_ALEN;byte++) {
1292
1293 for (bit = *addrs++,j=0;j<8;j++, bit>>=1) {
1294 crc = (crc >> 1) ^ (((crc ^ bit) & 0x01) ? poly : 0);
1295 }
1296 }
1297 hashcode = crc & ((1 << 9) - 1);
1298
1299 byte = hashcode >> 3;
1300 bit = 1 << (hashcode & 0x07);
1301
1302 if (lp->shmem_length == IO_ONLY) {
1303 unsigned char tmp;
1304
1305 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1306 tmp = inb(EWRK3_DATA);
1307 tmp |= bit;
1308 outw((short)((long)multicast_table) + byte, EWRK3_PIR1);
1309 outb(tmp, EWRK3_DATA);
1310 } else {
1311 multicast_table[byte] |= bit;
1312 }
1313 } else {
1314 addrs += ETH_ALEN;
1315 }
1316 }
1317 }
1318
1319 lp->lock = 0;
1320
1321 return;
1322 }
1323
1324 #ifndef MODULE
1325
1326
1327
1328 static struct device *isa_probe(struct device *dev)
1329 {
1330 int i, iobase, status;
1331 unsigned long int tmp = mem_chkd;
1332
1333 for (status = -ENODEV, iobase = EWRK3_IO_BASE,i = 0;
1334 i < 24;
1335 iobase += EWRK3_IOP_INC, i++) {
1336 if (tmp & 0x01) {
1337
1338 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1339 if (DevicePresent(iobase) == 0) {
1340
1341
1342
1343
1344 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1345 if (num_ewrk3s > 0) {
1346 dev = alloc_device(dev, iobase);
1347 } else {
1348 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1349 num_ewrk3s++;
1350 }
1351 }
1352 num_eth++;
1353 } else {
1354 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1355 }
1356 } else {
1357 printk("%s: ewrk3_probe(): Detected a device already registered at 0x%02x\n", dev->name, iobase);
1358 mem_chkd &= ~(0x01 << ((iobase - EWRK3_IO_BASE)/EWRK3_IOP_INC));
1359 }
1360 }
1361 tmp >>= 1;
1362 }
1363
1364 return dev;
1365 }
1366
1367
1368
1369
1370
1371 static struct device *eisa_probe(struct device *dev)
1372 {
1373 int i, iobase = EWRK3_EISA_IO_PORTS;
1374 int status;
1375
1376 iobase+=EISA_SLOT_INC;
1377 for (status = -ENODEV, i=1; i<MAX_EISA_SLOTS; i++, iobase+=EISA_SLOT_INC) {
1378
1379
1380 if (!check_region(iobase, EWRK3_TOTAL_SIZE)) {
1381 if (DevicePresent(iobase) == 0) {
1382
1383
1384
1385
1386 mem_chkd |= (0x01 << (i + 24));
1387 request_region(iobase, EWRK3_IOP_INC, "ewrk3");
1388 if (num_ewrk3s > 0) {
1389 dev = alloc_device(dev, iobase);
1390 } else {
1391 if ((status = ewrk3_hw_init(dev, iobase)) == 0) {
1392 num_ewrk3s++;
1393 }
1394 }
1395 num_eth++;
1396 }
1397 }
1398 }
1399 return dev;
1400 }
1401
1402
1403
1404
1405
1406 static struct device *alloc_device(struct device *dev, int iobase)
1407 {
1408
1409
1410
1411 while (dev->next != NULL) {
1412 if (dev->next->base_addr == 0xffe0) break;
1413 dev = dev->next;
1414 num_eth++;
1415 }
1416
1417
1418
1419
1420
1421 if (dev->next == NULL) {
1422 dev->next = (struct device *)kmalloc(sizeof(struct device) + 8,
1423 GFP_KERNEL);
1424 if (dev->next == NULL) {
1425 printk("eth%d: Device not initialised, insufficient memory\n",
1426 num_eth);
1427 }
1428 }
1429
1430
1431
1432
1433
1434
1435 if ((dev->next != NULL) &&
1436 (num_eth > 0) && (num_eth < 9999)) {
1437 dev = dev->next;
1438 dev->name = (char *)(dev + sizeof(struct device));
1439 sprintf(dev->name,"eth%d", num_eth);
1440 dev->base_addr = iobase;
1441 dev->next = NULL;
1442 dev->init = &ewrk3_probe;
1443 num_ewrk3s++;
1444 }
1445
1446 return dev;
1447 }
1448 #endif
1449
1450
1451
1452
1453 static int Read_EEPROM(short iobase, unsigned char eaddr)
1454 {
1455 int i;
1456
1457 outb((eaddr & 0x3f), EWRK3_PIR1);
1458 outb(EEPROM_RD, EWRK3_IOPR);
1459 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1460
1461 return inw(EWRK3_EPROM1);
1462 }
1463
1464
1465
1466
1467 static int Write_EEPROM(short data, short iobase, unsigned char eaddr)
1468 {
1469 int i;
1470
1471 outb(EEPROM_WR_EN, EWRK3_IOPR);
1472 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1473 outw(data, EWRK3_EPROM1);
1474 outb((eaddr & 0x3f), EWRK3_PIR1);
1475 outb(EEPROM_WR, EWRK3_IOPR);
1476 for (i=0;i<75000;i++) inb(EWRK3_CSR);
1477 outb(EEPROM_WR_DIS, EWRK3_IOPR);
1478 for (i=0;i<5000;i++) inb(EWRK3_CSR);
1479
1480 return 0;
1481 }
1482
1483
1484
1485
1486 static void EthwrkSignature(char *name, char *eeprom_image)
1487 {
1488 unsigned long i,j,k;
1489 char signatures[][EWRK3_NAME_LENGTH] = EWRK3_SIGNATURE;
1490
1491 strcpy(name, "");
1492 for (i=0;*signatures[i] != '\0' && *name == '\0';i++) {
1493 for (j=EEPROM_PNAME7,k=0;j<=EEPROM_PNAME0 && k<strlen(signatures[i]);j++) {
1494 if (signatures[i][k] == eeprom_image[j]) {
1495 k++;
1496 } else {
1497 k=0;
1498 }
1499 }
1500 if (k == strlen(signatures[i])) {
1501 for (k=0; k<EWRK3_NAME_LENGTH; k++) {
1502 name[k] = eeprom_image[EEPROM_PNAME7 + k];
1503 name[EWRK3_NAME_LENGTH] = '\0';
1504 }
1505 }
1506 }
1507
1508 return;
1509 }
1510
1511
1512
1513
1514
1515
1516 static int DevicePresent(short iobase)
1517 {
1518 static short fp=1,sigLength=0;
1519 static char devSig[] = PROBE_SEQUENCE;
1520 char data;
1521 int i, j, status = 0;
1522 static char asc2hex(char value);
1523
1524
1525
1526
1527 if (fp) {
1528 for (i=0,j=0;devSig[i] != '\0' && !status;i+=2,j++) {
1529 if ((devSig[i]=asc2hex(devSig[i]))>=0) {
1530 devSig[i]<<=4;
1531 if((devSig[i+1]=asc2hex(devSig[i+1]))>=0){
1532 devSig[j]=devSig[i]+devSig[i+1];
1533 } else {
1534 status= -1;
1535 }
1536 } else {
1537 status= -1;
1538 }
1539 }
1540 sigLength=j;
1541 fp = 0;
1542 }
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552 if (!status) {
1553 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
1554 data = inb(EWRK3_APROM);
1555 if (devSig[j] == data) {
1556 j++;
1557 } else {
1558 j=0;
1559 }
1560 }
1561
1562 if (j!=sigLength) {
1563 status = -ENODEV;
1564 }
1565 }
1566
1567 return status;
1568 }
1569
1570 static unsigned char aprom_crc(struct device *dev, unsigned char *eeprom_image, char chipType)
1571 {
1572 long k;
1573 unsigned short j,chksum;
1574 unsigned char crc, lfsr, sd, status = 0;
1575 int iobase = dev->base_addr;
1576
1577 if (chipType == LeMAC2) {
1578 for (crc=0x6a, j=0; j<ETH_ALEN; j++) {
1579 for (sd=inb(EWRK3_PAR0+j), k=0; k<8; k++, sd >>= 1) {
1580 lfsr = ((((crc & 0x02) >> 1) ^ (crc & 0x01)) ^ (sd & 0x01)) << 7;
1581 crc = (crc >> 1) + lfsr;
1582 }
1583 }
1584 if (crc != eeprom_image[EEPROM_PA_CRC]) status = -1;
1585 } else {
1586 for (k=0,j=0;j<3;j++) {
1587 k <<= 1 ;
1588 if (k > 0xffff) k-=0xffff;
1589 k += inw(EWRK3_PAR0 + (j<<1));
1590 if (k > 0xffff) k-=0xffff;
1591 }
1592 if (k == 0xffff) k=0;
1593 chksum = inb(EWRK3_APROM);
1594 chksum |= (inb(EWRK3_APROM)<<8);
1595 if (k != chksum) status = -1;
1596 }
1597
1598 return status;
1599 }
1600
1601
1602
1603
1604
1605 static int ewrk3_ioctl(struct device *dev, struct ifreq *rq, int cmd)
1606 {
1607 struct ewrk3_private *lp = (struct ewrk3_private *)dev->priv;
1608 struct ewrk3_ioctl *ioc = (struct ewrk3_ioctl *) &rq->ifr_data;
1609 int i, j, iobase = dev->base_addr, status = 0;
1610 unsigned char csr;
1611 union {
1612 unsigned char addr[HASH_TABLE_LEN * ETH_ALEN];
1613 unsigned short val[(HASH_TABLE_LEN * ETH_ALEN) >> 1];
1614 } tmp;
1615 int err;
1616
1617 switch(ioc->cmd) {
1618 case EWRK3_GET_HWADDR:
1619 for (i=0; i<ETH_ALEN; i++) {
1620 tmp.addr[i] = dev->dev_addr[i];
1621 }
1622 ioc->len = ETH_ALEN;
1623
1624 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ETH_ALEN);
1625 if (err) return err;
1626 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1627
1628 break;
1629 case EWRK3_SET_HWADDR:
1630 if (suser()) {
1631 csr = inb(EWRK3_CSR);
1632 csr |= (TXD|RXD);
1633 outb(csr, EWRK3_CSR);
1634
1635 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN);
1636 if (err) return err;
1637 memcpy_fromfs(tmp.addr,ioc->data,ETH_ALEN);
1638 for (i=0; i<ETH_ALEN; i++) {
1639 dev->dev_addr[i] = tmp.addr[i];
1640 outb(tmp.addr[i], EWRK3_PAR0 + i);
1641 }
1642
1643 csr &= ~(TXD|RXD);
1644 outb(csr, EWRK3_CSR);
1645 } else {
1646 status = -EPERM;
1647 }
1648
1649 break;
1650 case EWRK3_SET_PROM:
1651 if (suser()) {
1652 csr = inb(EWRK3_CSR);
1653 csr |= PME;
1654 csr &= ~MCE;
1655 outb(csr, EWRK3_CSR);
1656 } else {
1657 status = -EPERM;
1658 }
1659
1660 break;
1661 case EWRK3_CLR_PROM:
1662 if (suser()) {
1663 csr = inb(EWRK3_CSR);
1664 csr &= ~PME;
1665 outb(csr, EWRK3_CSR);
1666 } else {
1667 status = -EPERM;
1668 }
1669
1670 break;
1671 case EWRK3_SAY_BOO:
1672 printk("%s: Boo!\n", dev->name);
1673
1674 break;
1675 case EWRK3_GET_MCA:
1676 err = verify_area(VERIFY_WRITE, (void *)ioc->data, HASH_TABLE_LEN >> 3);
1677 if (err) return err;
1678
1679 while (set_bit(0, (void *)&lp->lock) != 0);
1680 if (lp->shmem_length == IO_ONLY) {
1681 outb(0, EWRK3_IOPR);
1682 outw(PAGE0_HTE, EWRK3_PIR1);
1683 for (i=0; i<(HASH_TABLE_LEN >> 3); i++) {
1684 tmp.addr[i] = inb(EWRK3_DATA);
1685 }
1686 } else {
1687 outb(0, EWRK3_MPR);
1688 memcpy(tmp.addr, (char *)(lp->shmem_base + PAGE0_HTE), (HASH_TABLE_LEN >> 3));
1689 }
1690 ioc->len = (HASH_TABLE_LEN >> 3);
1691 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1692 lp->lock = 0;
1693
1694 break;
1695 case EWRK3_SET_MCA:
1696 if (suser()) {
1697 err = verify_area(VERIFY_READ, (void *)ioc->data, ETH_ALEN * ioc->len);
1698 if (err) return err;
1699
1700 if (ioc->len != HASH_TABLE_LEN) {
1701 memcpy_fromfs(tmp.addr, ioc->data, ETH_ALEN * ioc->len);
1702 }
1703 set_multicast_list(dev, ioc->len, tmp.addr);
1704 } else {
1705 status = -EPERM;
1706 }
1707
1708 break;
1709 case EWRK3_CLR_MCA:
1710 if (suser()) {
1711 set_multicast_list(dev, 0, NULL);
1712 } else {
1713 status = -EPERM;
1714 }
1715
1716 break;
1717 case EWRK3_MCA_EN:
1718 if (suser()) {
1719 csr = inb(EWRK3_CSR);
1720 csr |= MCE;
1721 csr &= ~PME;
1722 outb(csr, EWRK3_CSR);
1723 } else {
1724 status = -EPERM;
1725 }
1726
1727 break;
1728 case EWRK3_GET_STATS:
1729 err = verify_area(VERIFY_WRITE, (void *)ioc->data, sizeof(lp->pktStats));
1730 if (err) return err;
1731
1732 cli();
1733 memcpy_tofs(ioc->data, &lp->pktStats, sizeof(lp->pktStats));
1734 ioc->len = EWRK3_PKT_STAT_SZ;
1735 sti();
1736
1737 break;
1738 case EWRK3_CLR_STATS:
1739 if (suser()) {
1740 cli();
1741 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
1742 sti();
1743 } else {
1744 status = -EPERM;
1745 }
1746
1747 break;
1748 case EWRK3_GET_CSR:
1749 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1750 if (err) return err;
1751
1752 tmp.addr[0] = inb(EWRK3_CSR);
1753 memcpy_tofs(ioc->data, tmp.addr, 1);
1754
1755 break;
1756 case EWRK3_SET_CSR:
1757 err = verify_area(VERIFY_READ, (void *)ioc->data, 1);
1758 if (err) return err;
1759
1760 if (suser()) {
1761 memcpy_fromfs(tmp.addr, ioc->data, 1);
1762 outb(tmp.addr[0], EWRK3_CSR);
1763 } else {
1764 status = -EPERM;
1765 }
1766
1767 break;
1768 case EWRK3_GET_EEPROM:
1769 if (suser()) {
1770 err = verify_area(VERIFY_WRITE, (void *)ioc->data, ioc->len);
1771 if (err) return err;
1772
1773 for (i=0; i<(EEPROM_MAX>>1); i++) {
1774 tmp.val[i] = (short)Read_EEPROM(iobase, i);
1775 }
1776 i = EEPROM_MAX;
1777 tmp.addr[i++] = inb(EWRK3_CMR);
1778 for (j=0;j<ETH_ALEN;j++) {
1779 tmp.addr[i++] = inb(EWRK3_PAR0 + j);
1780 }
1781 ioc->len = EEPROM_MAX + 1 + ETH_ALEN;
1782 memcpy_tofs(ioc->data, tmp.addr, ioc->len);
1783 } else {
1784 status = -EPERM;
1785 }
1786
1787 break;
1788 case EWRK3_SET_EEPROM:
1789 if (suser()) {
1790 err = verify_area(VERIFY_READ, (void *)ioc->data, EEPROM_MAX);
1791 if (err) return err;
1792
1793 memcpy_fromfs(tmp.addr, ioc->data, EEPROM_MAX);
1794 for (i=0; i<(EEPROM_MAX>>1); i++) {
1795 Write_EEPROM(tmp.val[i], iobase, i);
1796 }
1797 } else {
1798 status = -EPERM;
1799 }
1800
1801 break;
1802 case EWRK3_GET_CMR:
1803 err = verify_area(VERIFY_WRITE, (void *)ioc->data, 1);
1804 if (err) return err;
1805
1806 tmp.addr[0] = inb(EWRK3_CMR);
1807 memcpy_tofs(ioc->data, tmp.addr, 1);
1808
1809 break;
1810 case EWRK3_SET_TX_CUT_THRU:
1811 if (suser()) {
1812 lp->txc = 1;
1813 } else {
1814 status = -EPERM;
1815 }
1816
1817 break;
1818 case EWRK3_CLR_TX_CUT_THRU:
1819 if (suser()) {
1820 lp->txc = 0;
1821 } else {
1822 status = -EPERM;
1823 }
1824
1825 break;
1826 default:
1827 status = -EOPNOTSUPP;
1828 }
1829
1830 return status;
1831 }
1832
1833 static char asc2hex(char value)
1834 {
1835 value -= 0x30;
1836 if (value >= 0) {
1837 if (value > 9) {
1838 value &= 0x1f;
1839 value -= 0x07;
1840 if ((value < 0x0a) || (value > 0x0f)) {
1841 value = -1;
1842 }
1843 }
1844 } else {
1845 value = -1;
1846 }
1847 return value;
1848 }
1849
1850 #ifdef MODULE
1851 static char devicename[9] = { 0, };
1852 static struct device thisEthwrk = {
1853 devicename,
1854 0, 0, 0, 0,
1855 0x300, 5,
1856 0, 0, 0, NULL, ewrk3_probe };
1857
1858 static int io=0x300;
1859 static int irq=5;
1860
1861 int
1862 init_module(void)
1863 {
1864 thisEthwrk.base_addr=io;
1865 thisEthwrk.irq=irq;
1866 if (register_netdev(&thisEthwrk) != 0)
1867 return -EIO;
1868 return 0;
1869 }
1870
1871 void
1872 cleanup_module(void)
1873 {
1874 release_region(thisEthwrk.base_addr, EWRK3_TOTAL_SIZE);
1875 unregister_netdev(&thisEthwrk);
1876 kfree(thisEthwrk.priv);
1877 thisEthwrk.priv = NULL;
1878 }
1879 #endif
1880
1881
1882
1883
1884
1885
1886
1887
1888
1889
1890
1891