drivers/scsi/aha152x.h

/* */
   1 #ifndef _AHA152X_H
   2 #define _AHA152X_H
   3 
   4 /*
   5  * $Id: aha152x.h,v 1.9 1995/03/18 09:21:04 root Exp root $
   6  */
   7 
   8 #if defined(__KERNEL__)
   9 
  10 #include <linux/blk.h>
  11 #include "scsi.h"
  12 #include <asm/io.h>
  13 
  14 int        aha152x_detect(Scsi_Host_Template *);
  15 int        aha152x_command(Scsi_Cmnd *);
  16 int        aha152x_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
  17 int        aha152x_abort(Scsi_Cmnd *);
  18 int        aha152x_reset(Scsi_Cmnd *);
  19 int        aha152x_biosparam(Disk *, kdev_t, int*);
  20 
  21 /* number of queueable commands
  22    (unless we support more than 1 cmd_per_lun this should do) */
  23 #define AHA152X_MAXQUEUE        7               
  24 
  25 #define AHA152X_REVID "Adaptec 152x SCSI driver; $Revision: 1.9 $"
  26 
  27 extern struct proc_dir_entry proc_scsi_aha152x;
  28 
  29 /* Initial value of Scsi_Host entry */
  30 #define AHA152X       { /* next */              NULL,                       \
  31                         /* usage_count */       NULL,                       \
  32                                                 &proc_scsi_aha152x,         \
  33                                                 NULL,                       \
  34                         /* name */              AHA152X_REVID,              \
  35                         /* detect */            aha152x_detect,             \
  36                         /* release */           NULL,                       \
  37                         /* info */              NULL,                       \
  38                         /* command */           aha152x_command,            \
  39                         /* queuecommand */      aha152x_queue,              \
  40                         /* abort */             aha152x_abort,              \
  41                         /* reset */             aha152x_reset,              \
  42                         /* slave_attach */      /* NULL */  0,              \
  43                         /* bios_param */        aha152x_biosparam,          \
  44                         /* can_queue */         1,                          \
  45                         /* this_id */           7,                          \
  46                         /* sg_tablesize */      SG_ALL,                     \
  47                         /* cmd_per_lun */       1,                          \
  48                         /* present */           0,                          \
  49                         /* unchecked_isa_dma */ 0,                          \
  50                         /* use_clustering */    DISABLE_CLUSTERING }
  51 #endif
  52 
  53 
  54 /* port addresses */
  55 #define SCSISEQ         (port_base+0x00)        /* SCSI sequence control */
  56 #define SXFRCTL0        (port_base+0x01)        /* SCSI transfer control 0 */
  57 #define SXFRCTL1        (port_base+0x02)        /* SCSI transfer control 1 */
  58 #define SCSISIG         (port_base+0x03)        /* SCSI signal in/out */
  59 #define SCSIRATE        (port_base+0x04)        /* SCSI rate control */
  60 #define SELID           (port_base+0x05)        /* selection/reselection ID */
  61 #define SCSIID          SELID                   /* SCSI ID */
  62 #define SCSIDAT         (port_base+0x06)        /* SCSI latched data */
  63 #define SCSIBUS         (port_base+0x07)        /* SCSI data bus */
  64 #define STCNT0          (port_base+0x08)        /* SCSI transfer count 0 */
  65 #define STCNT1          (port_base+0x09)        /* SCSI transfer count 1 */
  66 #define STCNT2          (port_base+0x0a)        /* SCSI transfer count 2 */
  67 #define SSTAT0          (port_base+0x0b)        /* SCSI interrupt status 0 */
  68 #define SSTAT1          (port_base+0x0c)        /* SCSI interrupt status 1 */
  69 #define SSTAT2          (port_base+0x0d)        /* SCSI interrupt status 2 */
  70 #define SCSITEST        (port_base+0x0e)        /* SCSI test control */
  71 #define SSTAT4          (port_base+0x0f)        /* SCSI status 4 */
  72 #define SIMODE0         (port_base+0x10)        /* SCSI interrupt mode 0 */
  73 #define SIMODE1         (port_base+0x11)        /* SCSI interrupt mode 1 */
  74 #define DMACNTRL0       (port_base+0x12)        /* DMA control 0 */
  75 #define DMACNTRL1       (port_base+0x13)        /* DMA control 1 */
  76 #define DMASTAT         (port_base+0x14)        /* DMA status */
  77 #define FIFOSTAT        (port_base+0x15)        /* FIFO status */
  78 #define DATAPORT        (port_base+0x16)        /* DATA port */
  79 #define BRSTCNTRL       (port_base+0x18)        /* burst control */
  80 #define PORTA           (port_base+0x1a)        /* PORT A */
  81 #define PORTB           (port_base+0x1b)        /* PORT B */
  82 #define REV             (port_base+0x1c)        /* revision */
  83 #define STACK           (port_base+0x1d)        /* stack */
  84 #define TEST            (port_base+0x1e)        /* test register */
  85 
  86 
  87 /* bits and bitmasks to ports */
  88 
  89 /* SCSI sequence control */
  90 #define TEMODEO         0x80
  91 #define ENSELO          0x40
  92 #define ENSELI          0x20
  93 #define ENRESELI        0x10
  94 #define ENAUTOATNO      0x08
  95 #define ENAUTOATNI      0x04
  96 #define ENAUTOATNP      0x02
  97 #define SCSIRSTO        0x01
  98 
  99 /* SCSI transfer control 0 */
 100 #define SCSIEN          0x80
 101 #define DMAEN           0x40
 102 #define CH1             0x20
 103 #define CLRSTCNT        0x10
 104 #define SPIOEN          0x08
 105 #define CLRCH1          0x02
 106 
 107 /* SCSI transfer control 1 */
 108 #define BITBUCKET       0x80
 109 #define SWRAPEN         0x40
 110 #define ENSPCHK         0x20
 111 #define STIMESEL        0x18    /* mask */
 112 #define STIMESEL_       3
 113 #define ENSTIMER        0x04
 114 #define BYTEALIGN       0x02
 115 
 116 /* SCSI signal IN */
 117 #define CDI             0x80
 118 #define IOI             0x40
 119 #define MSGI            0x20
 120 #define ATNI            0x10
 121 #define SELI            0x08
 122 #define BSYI            0x04
 123 #define REQI            0x02
 124 #define ACKI            0x01
 125 
 126 /* SCSI Phases */
 127 #define P_MASK          (MSGI|CDI|IOI)
 128 #define P_DATAO         (0)
 129 #define P_DATAI         (IOI)
 130 #define P_CMD           (CDI)
 131 #define P_STATUS        (CDI|IOI)
 132 #define P_MSGO          (MSGI|CDI)
 133 #define P_MSGI          (MSGI|CDI|IOI)
 134 
 135 /* SCSI signal OUT */
 136 #define CDO             0x80
 137 #define IOO             0x40
 138 #define MSGO            0x20
 139 #define ATNO            0x10
 140 #define SELO            0x08
 141 #define BSYO            0x04
 142 #define REQO            0x02
 143 #define ACKO            0x01
 144 
 145 /* SCSI rate control */
 146 #define SXFR            0x70    /* mask */
 147 #define SXFR_           4
 148 #define SOFS            0x0f    /* mask */
 149 
 150 /* SCSI ID */
 151 #define OID             0x70
 152 #define OID_            4
 153 #define TID             0x07
 154 
 155 /* SCSI transfer count */
 156 #define GETSTCNT()   ( (GETPORT(STCNT2)<<16) \
 157                      + (GETPORT(STCNT1)<< 8) \
 158                      + GETPORT(STCNT0) )
 159 
 160 #define SETSTCNT(X)  { SETPORT(STCNT2, ((X) & 0xFF0000) >> 16); \
 161                        SETPORT(STCNT1, ((X) & 0x00FF00) >>  8); \
 162                        SETPORT(STCNT0, ((X) & 0x0000FF) ); }
 163 
 164 /* SCSI interrupt status */
 165 #define TARGET          0x80
 166 #define SELDO           0x40
 167 #define SELDI           0x20
 168 #define SELINGO         0x10
 169 #define SWRAP           0x08
 170 #define SDONE           0x04
 171 #define SPIORDY         0x02
 172 #define DMADONE         0x01
 173 
 174 #define SETSDONE        0x80
 175 #define CLRSELDO        0x40
 176 #define CLRSELDI        0x20
 177 #define CLRSELINGO      0x10
 178 #define CLRSWRAP        0x08
 179 #define CLRSDONE        0x04
 180 #define CLRSPIORDY      0x02
 181 #define CLRDMADONE      0x01
 182 
 183 /* SCSI status 1 */
 184 #define SELTO           0x80
 185 #define ATNTARG         0x40
 186 #define SCSIRSTI        0x20
 187 #define PHASEMIS        0x10
 188 #define BUSFREE         0x08
 189 #define SCSIPERR        0x04
 190 #define PHASECHG        0x02
 191 #define REQINIT         0x01
 192 
 193 #define CLRSELTIMO      0x80
 194 #define CLRATNO         0x40
 195 #define CLRSCSIRSTI     0x20
 196 #define CLRBUSFREE      0x08
 197 #define CLRSCSIPERR     0x04
 198 #define CLRPHASECHG     0x02
 199 #define CLRREQINIT      0x01
 200 
 201 /* SCSI status 2 */
 202 #define SOFFSET         0x20
 203 #define SEMPTY          0x10
 204 #define SFULL           0x08
 205 #define SFCNT           0x07    /* mask */
 206 
 207 /* SCSI status 3 */
 208 #define SCSICNT         0xf0    /* mask */
 209 #define SCSICNT_        4
 210 #define OFFCNT          0x0f    /* mask */
 211 
 212 /* SCSI TEST control */
 213 #define SCTESTU         0x08
 214 #define SCTESTD         0x04
 215 #define STCTEST         0x01
 216 
 217 /* SCSI status 4 */
 218 #define SYNCERR         0x04
 219 #define FWERR           0x02
 220 #define FRERR           0x01
 221 
 222 #define CLRSYNCERR      0x04
 223 #define CLRFWERR        0x02
 224 #define CLRFRERR        0x01
 225 
 226 /* SCSI interrupt mode 0 */
 227 #define ENSELDO         0x40
 228 #define ENSELDI         0x20
 229 #define ENSELINGO       0x10
 230 #define ENSWRAP         0x08
 231 #define ENSDONE         0x04
 232 #define ENSPIORDY       0x02
 233 #define ENDMADONE       0x01
 234 
 235 /* SCSI interrupt mode 1 */
 236 #define ENSELTIMO       0x80
 237 #define ENATNTARG       0x40
 238 #define ENSCSIRST       0x20
 239 #define ENPHASEMIS      0x10
 240 #define ENBUSFREE       0x08
 241 #define ENSCSIPERR      0x04
 242 #define ENPHASECHG      0x02
 243 #define ENREQINIT       0x01
 244 
 245 /* DMA control 0 */
 246 #define ENDMA           0x80
 247 #define _8BIT           0x40
 248 #define DMA             0x20
 249 #define WRITE_READ      0x08
 250 #define INTEN           0x04
 251 #define RSTFIFO         0x02
 252 #define SWINT           0x01
 253 
 254 /* DMA control 1 */
 255 #define PWRDWN          0x80
 256 #define STK             0x07    /* mask */
 257 
 258 /* DMA status */
 259 #define ATDONE          0x80
 260 #define WORDRDY         0x40
 261 #define INTSTAT         0x20
 262 #define DFIFOFULL       0x10
 263 #define DFIFOEMP        0x08
 264 
 265 /* BURST control */
 266 #define BON             0xf0
 267 #define BOFF            0x0f
 268 
 269 /* TEST REGISTER */
 270 #define BOFFTMR         0x40
 271 #define BONTMR          0x20
 272 #define STCNTH          0x10
 273 #define STCNTM          0x08
 274 #define STCNTL          0x04
 275 #define SCSIBLK         0x02
 276 #define DMABLK          0x01
 277 
 278 /* On the AHA-152x board PORTA and PORTB contain
 279    some information about the board's configuration. */
 280 typedef union {
 281   struct {
 282     unsigned reserved:2;        /* reserved */
 283     unsigned tardisc:1;         /* Target disconnect: 0=disabled, 1=enabled */
 284     unsigned syncneg:1;         /* Initial sync neg: 0=disabled, 1=enabled */
 285     unsigned msgclasses:2;      /* Message classes
 286                                    0=#4
 287                                    1=#0, #1, #2, #3, #4
 288                                    2=#0, #3, #4
 289                                    3=#0, #4
 290                                 */
 291     unsigned boot:1;            /* boot: 0=disabled, 1=enabled */
 292     unsigned dma:1;             /* Transfer mode: 0=PIO; 1=DMA */
 293     unsigned id:3;              /* SCSI-id */
 294     unsigned irq:2;             /* IRQ-Channel: 0,3=12, 1=10, 2=11 */
 295     unsigned dmachan:2;         /* DMA-Channel: 0=0, 1=5, 2=6, 3=7 */
 296     unsigned parity:1;          /* SCSI-parity: 1=enabled 0=disabled */
 297   } fields;
 298   unsigned short port;
 299 } aha152x_config ;
 300 
 301 #define cf_parity       fields.parity
 302 #define cf_dmachan      fields.dmachan
 303 #define cf_irq          fields.irq
 304 #define cf_id           fields.id
 305 #define cf_dma          fields.dma
 306 #define cf_boot         fields.boot
 307 #define cf_msgclasses   fields.msgclasses
 308 #define cf_syncneg      fields.syncneg
 309 #define cf_tardisc      fields.tardisc
 310 #define cf_port         port
 311 
 312 /* Some macros to manipulate ports and their bits */
 313 
 314 #define SETPORT(PORT, VAL)      \
 315         outb( (VAL), (PORT) )
 316 
 317 #define SETPORTP(PORT, VAL)     \
 318         outb_p( (VAL), (PORT) )
 319 
 320 #define SETPORTW(PORT, VAL)     \
 321         outw( (VAL), (PORT) )
 322 
 323 #define GETPORT(PORT)   \
 324         inb( PORT )
 325 
 326 #define GETPORTW(PORT)  \
 327         inw( PORT )
 328 
 329 #define SETBITS(PORT, BITS)     \
 330         outb( (inb(PORT) | (BITS)), (PORT) )
 331 
 332 #define CLRBITS(PORT, BITS)     \
 333         outb( (inb(PORT) & ~(BITS)), (PORT) )
 334 
 335 #define CLRSETBITS(PORT, CLR, SET)      \
 336         outb( (inb(PORT) & ~(CLR)) | (SET) , (PORT) )
 337 
 338 #define TESTHI(PORT, BITS)      \
 339         ((inb(PORT) & (BITS)) == BITS)
 340 
 341 #define TESTLO(PORT, BITS)      \
 342         ((inb(PORT) & (BITS)) == 0)
 343 
 344 #ifdef DEBUG_AHA152X
 345 enum {
 346         debug_skipports =0x0001,
 347         debug_queue     =0x0002,
 348         debug_intr      =0x0004,
 349         debug_selection =0x0008,
 350         debug_msgo      =0x0010,
 351         debug_msgi      =0x0020,
 352         debug_status    =0x0040,
 353         debug_cmd       =0x0080,
 354         debug_datai     =0x0100,
 355         debug_datao     =0x0200,
 356         debug_abort     =0x0400,
 357         debug_done      =0x0800,
 358         debug_biosparam =0x1000,
 359         debug_phases    =0x2000,
 360         debug_queues    =0x4000,
 361         debug_reset     =0x8000,
 362 };
 363 #endif
 364 
 365 #endif /* _AHA152X_H */
/* */
root/drivers/scsi/aha152x.h

INCLUDED FROM
