1 /*+M************************************************************************* 2 * Adaptec 274x/284x/294x device driver for Linux. 3 * 4 * Copyright (c) 1994 John Aycock 5 * The University of Calgary Department of Computer Science. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2, or (at your option) 10 * any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; see the file COPYING. If not, write to 19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20 * 21 * Sources include the Adaptec 1740 driver (aha1740.c), the Ultrastor 24F 22 * driver (ultrastor.c), various Linux kernel source, the Adaptec EISA 23 * config file (!adp7771.cfg), the Adaptec AHA-2740A Series User's Guide, 24 * the Linux Kernel Hacker's Guide, Writing a SCSI Device Driver for Linux, 25 * the Adaptec 1542 driver (aha1542.c), the Adaptec EISA overlay file 26 * (adp7770.ovl), the Adaptec AHA-2740 Series Technical Reference Manual, 27 * the Adaptec AIC-7770 Data Book, the ANSI SCSI specification, the 28 * ANSI SCSI-2 specification (draft 10c), ... 29 * 30 * ---------------------------------------------------------------- 31 * Modified to include support for wide and twin bus adapters, 32 * DMAing of SCBs, tagged queueing, IRQ sharing, bug fixes, 33 * and other rework of the code. 34 * 35 * Parts of this driver are based on the FreeBSD driver by Justin 36 * T. Gibbs. 37 * 38 * A Boot time option was also added for not resetting the scsi bus. 39 * 40 * Form: aic7xxx=extended,no_reset 41 * 42 * -- Daniel M. Eischen, deischen@iworks.InterWorks.org, 04/03/95 43 * 44 * $Id: aic7xxx.c,v 2.5 1995/09/20 05:18:18 deang Exp $ 45 *-M*************************************************************************/ 46
47 #ifdefMODULE 48 #include <linux/module.h>
49 #endif 50
51 #include <stdarg.h>
52 #include <asm/io.h>
53 #include <linux/string.h>
54 #include <linux/errno.h>
55 #include <linux/kernel.h>
56 #include <linux/ioport.h>
57 #include <linux/bios32.h>
58 #include <linux/delay.h>
59 #include <linux/sched.h>
60 #include <linux/pci.h>
61 #include <linux/proc_fs.h>
62 #include <linux/blk.h>
63 #include "sd.h"
64 #include "scsi.h"
65 #include "hosts.h"
66 #include "aic7xxx.h"
67 #include <linux/stat.h>
68
69 #include <linux/config.h> /* for CONFIG_PCI */ 70
71 structproc_dir_entryproc_scsi_aic7xxx = { 72 PROC_SCSI_AIC7XXX, 7, "aic7xxx",
73 S_IFDIR | S_IRUGO | S_IXUGO, 2
74 };
75
76 #defineAIC7XXX_C_VERSION "$Revision: 2.5 $"
77
78 #defineNUMBER(arr) (sizeof(arr) / sizeof(arr[0]))
79 #defineMIN(a,b) ((a < b) ? a : b)
80 #defineALL_TARGETS -1
81 #ifndefTRUE 82 # defineTRUE 1
83 #endif 84 #ifndefFALSE 85 # defineFALSE 0
86 #endif 87
88 /* 89 * Defines for PCI bus support, testing twin bus support, DMAing of 90 * SCBs, tagged queueing, commands (SCBs) per lun, and SCSI bus reset 91 * delay time. 92 * 93 * o PCI bus support - this has been implemented and working since 94 * the December 1, 1994 release of this driver. If you don't have 95 * a PCI bus and do not wish to configure your kernel with PCI 96 * support, then make sure this define is set to the cprrect 97 * define for PCI support (CONFIG_PCI) and configure your kernel 98 * without PCI support (make config). 99 * 100 * o Twin bus support - this has been tested and does work. 101 * 102 * o DMAing of SCBs - thanks to Kai Makisara, this now works. 103 * This define is now taken out and DMAing of SCBs is always 104 * performed (8/12/95 - DE). 105 * 106 * o Tagged queueing - this driver is capable of tagged queueing 107 * but I am unsure as to how well the higher level driver implements 108 * tagged queueing. Therefore, the maximum commands per lun is 109 * set to 2. If you want to implement tagged queueing, ensure 110 * this define is not commented out. 111 * 112 * o Sharing IRQs - allowed for sharing of IRQs. This will allow 113 * for multiple aic7xxx host adapters sharing the same IRQ, but 114 * not for sharing IRQs with other devices. The higher level 115 * PCI code and interrupt handling needs to be modified to 116 * support this. 117 * 118 * o Commands per lun - If tagged queueing is enabled, then you 119 * may want to try increasing AIC7XXX_CMDS_PER_LUN to more 120 * than 2. By default, we limit the SCBs per lun to 2 with 121 * or without tagged queueing enabled. If tagged queueing is 122 * disabled, the sequencer will keep the 2nd SCB in the input 123 * queue until the first one completes - so it is OK to to have 124 * more than 1 SCB queued. If tagged queueing is enabled, then 125 * the sequencer will attempt to send the 2nd SCB to the device 126 * while the first SCB is executing and the device is disconnected. 127 * For adapters limited to 4 SCBs, you may want to actually 128 * decrease the commands per lun to 1, if you often have more 129 * than 2 devices active at the same time. This will allocate 130 * 1 SCB for each device and ensure that there will always be 131 * a free SCB for up to 4 devices active at the same time. 132 * 133 * Daniel M. Eischen, deischen@iworks.InterWorks.org, 03/11/95 134 */ 135
136 /* Uncomment this for testing twin bus support. */ 137 #defineAIC7XXX_TWIN_SUPPORT 138
139 /* Uncomment this for tagged queueing. */ 140 /* #define AIC7XXX_TAGGED_QUEUEING */ 141
142 /* Uncomment this for allowing sharing of IRQs. */ 143 #defineAIC7XXX_SHARE_IRQS 144
145 /* 146 * You can try raising me if tagged queueing is enabled, or lowering 147 * me if you only have 4 SCBs. 148 */ 149 #defineAIC7XXX_CMDS_PER_LUN 2
150
151 /* Set this to the delay in seconds after SCSI bus reset. */ 152 #defineAIC7XXX_RESET_DELAY 15
153
154 /* 155 * Uncomment the following define for collection of SCSI transfer statistics 156 * for the /proc filesystem. 157 * 158 * NOTE: This does affect performance since it has to maintain statistics. 159 */ 160 /* #define AIC7XXX_PROC_STATS */ 161
162 /* 163 * Define this to use polling rather than using kernel support for waking 164 * up a waiting process. 165 */ 166 #undefAIC7XXX_POLL 167
168 /* 169 * Controller type and options 170 */ 171 typedefenum{ 172 AIC_NONE,
173 AIC_274x, /* EISA aic7770 */ 174 AIC_284x, /* VLB aic7770 */ 175 AIC_7870, /* PCI aic7870 */ 176 AIC_7850, /* PCI aic7850 */ 177 AIC_7872/* PCI aic7870 on 394x */ 178 }aha_type;
179
180 typedefenum{ 181 AIC_SINGLE, /* Single Channel */ 182 AIC_TWIN, /* Twin Channel */ 183 AIC_WIDE/* Wide Channel */ 184 }aha_bus_type;
185
186 typedefenum{ 187 AIC_UNKNOWN,
188 AIC_ENABLED,
189 AIC_DISABLED 190 }aha_status_type;
191
192 typedefenum{ 193 LIST_HEAD,
194 LIST_SECOND,
195 LIST_TAIL
196 }insert_type;
197
198 /* 199 * There should be a specific return value for this in scsi.h, but 200 * it seems that most drivers ignore it. 201 */ 202 #define DID_UNDERFLOW DID_ERROR 203
204 /* 205 * What we want to do is have the higher level scsi driver requeue 206 * the command to us. There is no specific driver status for this 207 * condition, but the higher level scsi driver will requeue the 208 * command on a DID_BUS_BUSY error. 209 */ 210 #defineDID_RETRY_COMMANDDID_BUS_BUSY 211
212 /* 213 * EISA/VL-bus stuff 214 */ 215 #defineMINSLOT 1
216 #defineMAXSLOT 15
217 #defineSLOTBASE(x) ((x) << 12)
218 #defineMAXIRQ 15
219
220 /* 221 * Standard EISA Host ID regs (Offset from slot base) 222 */ 223 #defineHID0(x) ((x) + 0xC80) /* 0,1: msb of ID2, 2-7: ID1 */ 224 #defineHID1(x) ((x) + 0xC81) /* 0-4: ID3, 5-7: LSB ID2 */ 225 #defineHID2(x) ((x) + 0xC82) /* product */ 226 #define HID3(x) ((x) + 0xC83) /* firmware revision */ 227
228 /* 229 * AIC-7770 I/O range to reserve for a card 230 */ 231 #defineMINREG(x) ((x) + 0xC00ul)
232 #defineMAXREG(x) ((x) + 0xCBFul)
233
234 /* -------------------- AIC-7770 offset definitions ----------------------- */ 235
236 /* 237 * SCSI Sequence Control (p. 3-11). 238 * Each bit, when set starts a specific SCSI sequence on the bus 239 */ 240 #defineSCSISEQ(x) ((x) + 0xC00ul)
241 #defineTEMODEO 0x80
242 #defineENSELO 0x40
243 #defineENSELI 0x20
244 #defineENRSELI 0x10
245 #defineENAUTOATNO 0x08
246 #defineENAUTOATNI 0x04
247 #defineENAUTOATNP 0x02
248 #defineSCSIRSTO 0x01
249
250 /* 251 * SCSI Transfer Control 1 Register (pp. 3-14,15). 252 * Controls the SCSI module data path. 253 */ 254 #defineSXFRCTL1(x) ((x) + 0xC02ul)
255 #define BITBUCKET 0x80
256 #define SWRAPEN 0x40
257 #defineENSPCHK 0x20
258 #defineSTIMESEL 0x18
259 #defineENSTIMER 0x04
260 #defineACTNEGEN 0x02
261 #defineSTPWEN 0x01 /* Powered Termination */ 262
263 /* 264 * SCSI Control Signal Read Register (p. 3-15). 265 * Reads the actual state of the SCSI bus pins 266 */ 267 #defineSCSISIGI(x) ((x) + 0xC03ul)
268 #defineCDI 0x80
269 #defineIOI 0x40
270 #defineMSGI 0x20
271 #defineATNI 0x10
272 #defineSELI 0x08
273 #defineBSYI 0x04
274 #defineREQI 0x02
275 #defineACKI 0x01
276
277 /* 278 * SCSI Contol Signal Write Register (p. 3-16). 279 * Writing to this register modifies the control signals on the bus. Only 280 * those signals that are allowed in the current mode (Initiator/Target) are 281 * asserted. 282 */ 283 #define SCSISIGO(x) ((x) + 0xC03ul)
284 #defineCDO 0x80
285 #define IOO 0x40
286 #defineMSGO 0x20
287 #defineATNO 0x10
288 #define SELO 0x08
289 #define BSYO 0x04
290 #define REQO 0x02
291 #define ACKO 0x01
292
293 /* 294 * SCSI Rate 295 */ 296 #defineSCSIRATE(x) ((x) + 0xC04ul)
297 #defineWIDEXFER 0x80 /* Wide transfer control */ 298 #defineSXFR 0x70 /* Sync transfer rate */ 299 #define SOFS 0x0F /* Sync offset */ 300
301 /* 302 * SCSI ID (p. 3-18). 303 * Contains the ID of the board and the current target on the 304 * selected channel 305 */ 306 #defineSCSIID(x) ((x) + 0xC05ul)
307 #define TID 0xF0 /* Target ID mask */ 308 #define OID 0x0F /* Our ID mask */ 309
310 /* 311 * SCSI Transfer Count (pp. 3-19,20) 312 * These registers count down the number of bytes transfered 313 * across the SCSI bus. The counter is decremented only once 314 * the data has been safely transfered. SDONE in SSTAT0 is 315 * set when STCNT goes to 0 316 */ 317 #define STCNT(x) ((x) + 0xC08ul)
318
319 /* 320 * SCSI Status 0 (p. 3-21) 321 * Contains one set of SCSI Interrupt codes 322 * These are most likely of interest to the sequencer 323 */ 324 #defineSSTAT0(x) ((x) + 0xC0Bul)
325 #defineTARGET 0x80 /* Board is a target */ 326 #defineSELDO 0x40 /* Selection Done */ 327 #defineSELDI 0x20 /* Board has been selected */ 328 #defineSELINGO 0x10 /* Selection In Progress */ 329 #defineSWRAP 0x08 /* 24bit counter wrap */ 330 #defineSDONE 0x04 /* STCNT = 0x000000 */ 331 #defineSPIORDY 0x02 /* SCSI PIO Ready */ 332 #defineDMADONE 0x01 /* DMA transfer completed */ 333
334 /* 335 * Clear SCSI Interrupt 1 (p. 3-23) 336 * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. 337 */ 338 #defineCLRSINT1(x) ((x) + 0xC0Cul)
339 #defineCLRSELTIMEO 0x80
340 #defineCLRATNO 0x40
341 #define CLRSCSIRSTI 0x20
342 /* UNUSED 0x10 */ 343 #defineCLRBUSFREE 0x08
344 #defineCLRSCSIPERR 0x04
345 #defineCLRPHASECHG 0x02
346 #define CLRREQINIT 0x01
347
348 /* 349 * SCSI Status 1 (p. 3-24) 350 * These interrupt bits are of interest to the kernel driver 351 */ 352 #defineSSTAT1(x) ((x) + 0xC0Cul)
353 #defineSELTO 0x80
354 #defineATNTARG 0x40
355 #defineSCSIRSTI 0x20
356 #definePHASEMIS 0x10
357 #defineBUSFREE 0x08
358 #defineSCSIPERR 0x04
359 #definePHASECHG 0x02
360 #defineREQINIT 0x01
361
362 /* 363 * SCSI Interrrupt Mode 1 (pp. 3-28,29). 364 * Set bits in this register enable the corresponding 365 * interrupt source. 366 */ 367 #defineSIMODE1(x) ((x) + 0xC11ul)
368 #defineENSELTIMO 0x80
369 #defineENATNTARG 0x40
370 #define ENSCSIRST 0x20
371 #defineENPHASEMIS 0x10
372 #defineENBUSFREE 0x08
373 #defineENSCSIPERR 0x04
374 #defineENPHASECHG 0x02
375 #defineENREQINIT 0x01
376
377 /* 378 * SCSI/Host Address (p. 3-30) 379 * These registers hold the host address for the byte about to be 380 * transfered on the SCSI bus. They are counted up in the same 381 * manner as STCNT is counted down. SHADDR should always be used 382 * to determine the address of the last byte transfered since HADDR 383 * can be squewed by write ahead. 384 */ 385 #define SHADDR(x) ((x) + 0xC14ul)
386
387 /* 388 * Selection/Reselection ID (p. 3-31) 389 * Upper four bits are the device id. The ONEBIT is set when the re/selecting 390 * device did not set its own ID. 391 */ 392 #defineSELID(x) ((x) + 0xC19ul)
393 #define SELID_MASK 0xF0
394 #define ONEBIT 0x08
395 /* UNUSED 0x07 */ 396
397 /* 398 * Serial EEPROM Control (p. 4-92 in 7870 Databook) 399 * Controls the reading and writing of an external serial 1-bit 400 * EEPROM Device. In order to access the serial EEPROM, you must 401 * first set the SEEMS bit that generates a request to the memory 402 * port for access to the serial EEPROM device. When the memory 403 * port is not busy servicing another request, it reconfigures 404 * to allow access to the serial EEPROM. When this happens, SEERDY 405 * gets set high to verify that the memory port access has been 406 * granted. See aic7xxx_read_eprom for detailed information on 407 * the protocol necessary to read the serial EEPROM. 408 */ 409 #defineSEECTL(x) ((x) + 0xC1Eul)
410 #define EXTARBACK 0x80
411 #define EXTARBREQ 0x40
412 #defineSEEMS 0x20
413 #defineSEERDY 0x10
414 #defineSEECS 0x08
415 #defineSEECK 0x04
416 #define SEEDO 0x02
417 #defineSEEDI 0x01
418
419 /* 420 * SCSI Block Control (p. 3-32) 421 * Controls Bus type and channel selection. In a twin channel configuration 422 * addresses 0x00-0x1E are gated to the appropriate channel based on this 423 * register. SELWIDE allows for the coexistence of 8bit and 16bit devices 424 * on a wide bus. 425 */ 426 #defineSBLKCTL(x) ((x) + 0xC1Ful)
427 /* UNUSED 0xC0 */ 428 #defineAUTOFLUSHDIS 0x20 /* used for Rev C check */ 429 /* UNUSED 0x10 */ 430 #defineSELBUSB 0x08
431 /* UNUSED 0x04 */ 432 #defineSELWIDE 0x02
433 /* UNUSED 0x01 */ 434 #defineSELSINGLE 0x00
435
436 /* 437 * Sequencer Control (p. 3-33) 438 * Error detection mode and speed configuration 439 */ 440 #defineSEQCTL(x) ((x) + 0xC60ul)
441 #definePERRORDIS 0x80
442 #define PAUSEDIS 0x40
443 #define FAILDIS 0x20
444 #defineFASTMODE 0x10
445 #define BRKADRINTEN 0x08
446 #define STEP 0x04
447 #defineSEQRESET 0x02
448 #defineLOADRAM 0x01
449
450 /* 451 * Sequencer RAM Data (p. 3-34) 452 * Single byte window into the Scratch Ram area starting at the address 453 * specified by SEQADDR0 and SEQADDR1. To write a full word, simply write 454 * four bytes in sucessesion. The SEQADDRs will increment after the most 455 * significant byte is written 456 */ 457 #defineSEQRAM(x) ((x) + 0xC61ul)
458
459 /* 460 * Sequencer Address Registers (p. 3-35) 461 * Only the first bit of SEQADDR1 holds addressing information 462 */ 463 #defineSEQADDR0(x) ((x) + 0xC62ul)
464 #defineSEQADDR1(x) ((x) + 0xC63ul)
465
466 #defineACCUM(x) ((x) + 0xC64ul) /* accumulator */ 467 #define SINDEX(x) ((x) + 0xC65ul)
468
469 /* 470 * Board Control (p. 3-43) 471 */ 472 #defineBCTL(x) ((x) + 0xC84ul)
473 /* RSVD 0xF0 */ 474 #define ACE 0x08 /* Support for external processors */ 475 /* RSVD 0x06 */ 476 #defineENABLE 0x01
477
478 /* 479 * Bus On/Off Time (p. 3-44) 480 */ 481 #defineBUSTIME(x) ((x) + 0xC85ul)
482 #defineBOFF 0xF0
483 #define BON 0x0F
484
485 /* 486 * Bus Speed (p. 3-45) 487 */ 488 #defineBUSSPD(x) ((x) + 0xC86ul)
489 #defineDFTHRSH 0xC0
490 #define STBOFF 0x38
491 #define STBON 0x07
492
493 /* 494 * Host Control (p. 3-47) R/W 495 * Overal host control of the device. 496 */ 497 #defineHCNTRL(x) ((x) + 0xC87ul)
498 /* UNUSED 0x80 */ 499 #define POWRDN 0x40
500 /* UNUSED 0x20 */ 501 #defineSWINT 0x10
502 #defineIRQMS 0x08
503 #definePAUSE 0x04
504 #defineINTEN 0x02
505 #defineCHIPRST 0x01
506 #defineREQ_PAUSEIRQMS | PAUSE | INTEN 507 #define UNPAUSE_274X IRQMS | INTEN 508 #defineUNPAUSE_284XINTEN 509 #defineUNPAUSE_294XIRQMS | INTEN 510
511 /* 512 * Host Address (p. 3-48) 513 * This register contains the address of the byte about 514 * to be transfered across the host bus. 515 */ 516 #define HADDR(x) ((x) + 0xC88ul)
517
518 /* 519 * SCB Pointer (p. 3-49) 520 * Gate one of the four SCBs into the SCBARRAY window. 521 */ 522 #defineSCBPTR(x) ((x) + 0xC90ul)
523
524 /* 525 * Interrupt Status (p. 3-50) 526 * Status for system interrupts 527 */ 528 #defineINTSTAT(x) ((x) + 0xC91ul)
529 #defineSEQINT_MASK 0xF0 /* SEQINT Status Codes */ 530 #defineBAD_PHASE 0x00
531 #defineSEND_REJECT 0x10
532 #defineNO_IDENT 0x20
533 #defineNO_MATCH 0x30
534 #defineMSG_SDTR 0x40
535 #defineMSG_WDTR 0x50
536 #defineMSG_REJECT 0x60
537 #defineBAD_STATUS 0x70
538 #defineRESIDUAL 0x80
539 #defineABORT_TAG 0x90
540 #defineAWAITING_MSG 0xA0
541 #defineIMMEDDONE 0xB0
542 #defineBRKADRINT 0x08
543 #defineSCSIINT 0x04
544 #defineCMDCMPLT 0x02
545 #defineSEQINT 0x01
546 #defineINT_PEND (BRKADRINT | SEQINT | SCSIINT | CMDCMPLT)
547
548 /* 549 * Hard Error (p. 3-53) 550 * Reporting of catastrophic errors. You usually cannot recover from 551 * these without a full board reset. 552 */ 553 #defineERROR(x) ((x) + 0xC92ul)
554 /* UNUSED 0xF0 */ 555 #definePARERR 0x08
556 #defineILLOPCODE 0x04
557 #defineILLSADDR 0x02
558 #defineILLHADDR 0x01
559
560 /* 561 * Clear Interrupt Status (p. 3-52) 562 */ 563 #defineCLRINT(x) ((x) + 0xC92ul)
564 #define CLRBRKADRINT 0x08
565 #defineCLRSCSIINT 0x04
566 #defineCLRCMDINT 0x02
567 #defineCLRSEQINT 0x01
568
569 /* 570 * SCB Auto Increment (p. 3-59) 571 * Byte offset into the SCB Array and an optional bit to allow auto 572 * incrementing of the address during download and upload operations 573 */ 574 #defineSCBCNT(x) ((x) + 0xC9Aul)
575 #defineSCBAUTO 0x80
576 #define SCBCNT_MASK 0x1F
577
578 /* 579 * Queue In FIFO (p. 3-60) 580 * Input queue for queued SCBs (commands that the seqencer has yet to start) 581 */ 582 #defineQINFIFO(x) ((x) + 0xC9Bul)
583
584 /* 585 * Queue In Count (p. 3-60) 586 * Number of queued SCBs 587 */ 588 #defineQINCNT(x) ((x) + 0xC9Cul)
589
590 /* 591 * Queue Out FIFO (p. 3-61) 592 * Queue of SCBs that have completed and await the host 593 */ 594 #defineQOUTFIFO(x) ((x) + 0xC9Dul)
595
596 /* 597 * Queue Out Count (p. 3-61) 598 * Number of queued SCBs in the Out FIFO 599 */ 600 #defineQOUTCNT(x) ((x) + 0xC9Eul)
601
602 #defineSCBARRAY(x) ((x) + 0xCA0ul)
603
604 /* ---------------- END AIC-7770 Register Definitions ----------------- */ 605
606 /* --------------------- AIC-7870-only definitions -------------------- */ 607
608 #defineDSPCISTATUS(x) ((x) + 0xC86ul)
609 #defineDFTHRESH 0xC0
610
611 /* Scratch RAM offset definitions */ 612
613 /* ---------------------- Scratch RAM Offsets ------------------------- */ 614 /* These offsets are either to values that are initialized by the board's 615 * BIOS or are specified by the Linux sequencer code. If I can figure out 616 * how to read the EISA configuration info at probe time, the cards could 617 * be run without BIOS support installed 618 */ 619
620 /* 621 * 1 byte per target starting at this address for configuration values 622 */ 623 #defineHA_TARG_SCRATCH(x) ((x) + 0xC20ul)
624
625 /* 626 * The sequencer will stick the first byte of any rejected message here so 627 * we can see what is getting thrown away. 628 */ 629 #defineHA_REJBYTE(x) ((x) + 0xC31ul)
630
631 /* 632 * Bit vector of targets that have disconnection disabled. 633 */ 634 #defineHA_DISC_DSB(x) ((x) + 0xC32ul)
635
636 /* 637 * Length of pending message 638 */ 639 #defineHA_MSG_LEN(x) ((x) + 0xC34ul)
640
641 /* 642 * Outgoing Message Body 643 */ 644 #defineHA_MSG_START(x) ((x) + 0xC35ul)
645
646 /* 647 * These are offsets into the card's scratch ram. Some of the values are 648 * specified in the AHA2742 technical reference manual and are initialized 649 * by the BIOS at boot time. 650 */ 651 #defineHA_ARG_1(x) ((x) + 0xC4Aul) /* sdtr <-> rate parameters */ 652 #defineHA_RETURN_1(x) ((x) + 0xC4Aul)
653 #defineSEND_SENSE 0x80
654 #defineSEND_SDTR 0x80
655 #defineSEND_WDTR 0x80
656 #defineSEND_REJ 0x40
657
658 #define SG_COUNT(x) ((x) + 0xC4Dul)
659 #define SG_NEXT(x) ((x) + 0xC4Eul)
660 #define HA_SIGSTATE(x) ((x) + 0xC4Bul) /* value in SCSISIGO */ 661 #defineHA_SCBCOUNT(x) ((x) + 0xC52ul) /* number of hardware SCBs */ 662
663 #defineHA_FLAGS(x) ((x) + 0xC53ul) /* TWIN and WIDE bus flags */ 664 #defineSINGLE_BUS 0x00
665 #defineTWIN_BUS 0x01
666 #defineWIDE_BUS 0x02
667 #defineACTIVE_MSG 0x20
668 #define IDENTIFY_SEEN 0x40
669 #define RESELECTING 0x80
670
671 #defineHA_ACTIVE0(x) ((x) + 0xC54ul) /* Active bits; targets 0-7 */ 672 #defineHA_ACTIVE1(x) ((x) + 0xC55ul) /* Active bits; targets 8-15 */ 673 #defineSAVED_TCL(x) ((x) + 0xC56ul) /* Saved target, channel, LUN */ 674 #defineWAITING_SCBH(x) ((x) + 0xC57ul) /* Head of disconnected targets list. */ 675 #defineWAITING_SCBT(x) ((x) + 0xC58ul) /* Tail of disconnected targets list. */ 676
677 #defineHA_SCSICONF(x) ((x) + 0xC5Aul) /* SCSI config register */ 678 #defineHA_INTDEF(x) ((x) + 0xC5Cul) /* interrupt def'n register */ 679 #defineHA_HOSTCONF(x) ((x) + 0xC5Dul) /* host config def'n register */ 680
681 #defineHA_274_BIOSCTRL(x) ((x) + 0xC5Ful) /* BIOS enabled for 274x */ 682 #defineBIOSMODE 0x30
683 #defineBIOSDISABLED 0x30
684
685 #define MSG_ABORT 0x06
686 #defineMSG_BUS_DEVICE_RESET 0x0C
687 #defineBUS_8_BIT 0x00
688 #defineBUS_16_BIT 0x01
689 #defineBUS_32_BIT 0x02
690
691
692 /* 693 * 694 * Define the format of the SEEPROM registers (16 bits). 695 * 696 */ 697 structseeprom_config{ 698
699 /* 700 * SCSI ID Configuration Flags 701 */ 702 #defineCFXFER 0x0007 /* synchronous transfer rate */ 703 #defineCFSYNCH 0x0008 /* enable synchronous transfer */ 704 #defineCFDISC 0x0010 /* enable disconnection */ 705 #defineCFWIDEB 0x0020 /* wide bus device */ 706 /* UNUSED 0x00C0 */ 707 #define CFSTART 0x0100 /* send start unit SCSI command */ 708 #define CFINCBIOS 0x0200 /* include in BIOS scan */ 709 #define CFRNFOUND 0x0400 /* report even if not found */ 710 /* UNUSED 0xF800 */ 711 unsignedshortdevice_flags[16]; /* words 0-15 */ 712
713 /* 714 * BIOS Control Bits 715 */ 716 #define CFSUPREM 0x0001 /* support all removeable drives */ 717 #define CFSUPREMB 0x0002 /* support removeable drives for boot only */ 718 #define CFBIOSEN 0x0004 /* BIOS enabled */ 719 /* UNUSED 0x0008 */ 720 #define CFSM2DRV 0x0010 /* support more than two drives */ 721 /* UNUSED 0x0060 */ 722 #defineCFEXTEND 0x0080 /* extended translation enabled */ 723 /* UNUSED 0xFF00 */ 724 unsignedshortbios_control; /* word 16 */ 725
726 /* 727 * Host Adapter Control Bits 728 */ 729 /* UNUSED 0x0003 */ 730 #defineCFWSTERM 0x0008 /* SCSI high byte termination (wide card) */ 731 #defineCFSTERM 0x0004 /* SCSI low byte termination (non-wide cards) */ 732 #defineCFSPARITY 0x0010 /* SCSI parity */ 733 /* UNUSED 0x0020 */ 734 #define CFRESETB 0x0040 /* reset SCSI bus at IC initialization */ 735 /* UNUSED 0xFF80 */ 736 unsignedshortadapter_control; /* word 17 */ 737
738 /* 739 * Bus Release, Host Adapter ID 740 */ 741 #defineCFSCSIID 0x000F /* host adapter SCSI ID */ 742 /* UNUSED 0x00F0 */ 743 #defineCFBRTIME 0xFF00 /* bus release time */ 744 unsignedshortbrtime_id; /* word 18 */ 745
746 /* 747 * Maximum targets 748 */ 749 #define CFMAXTARG 0x00FF /* maximum targets */ 750 /* UNUSED 0xFF00 */ 751 unsignedshortmax_targets; /* word 19 */ 752
753 unsignedshort res_1[11]; /* words 20-30 */ 754 unsignedshortchecksum; /* word 31 */ 755
756 };
757
758
759 #defineAIC7XXX_DEBUG 760
761 /* 762 * Pause the sequencer and wait for it to actually stop - this 763 * is important since the sequencer can disable pausing for critical 764 * sections. 765 */ 766 #definePAUSE_SEQUENCER(p) \
767 outb(p->pause, HCNTRL(p->base)); \
768 while ((inb(HCNTRL(p->base)) & PAUSE) == 0) \
769 ; \
770
771 /* 772 * Unpause the sequencer. Unremarkable, yet done often enough to 773 * warrant an easy way to do it. 774 */ 775 #defineUNPAUSE_SEQUENCER(p) \
776 outb(p->unpause, HCNTRL(p->base))
777
778 /* 779 * Restart the sequencer program from address zero 780 */ 781 #defineRESTART_SEQUENCER(p) \
782 do{ \
783 outb(SEQRESET | FASTMODE, SEQCTL(p->base)); \
784 }while (inb(SEQADDR0(p->base)) != 0 && \
785 inb(SEQADDR1(p->base)) != 0); \
786 UNPAUSE_SEQUENCER(p);
787
788 /* 789 * If an error occurs during a data transfer phase, run the comand 790 * to completion - it's easier that way - making a note of the error 791 * condition in this location. This then will modify a DID_OK status 792 * into an appropriate error for the higher-level SCSI code. 793 */ 794 #defineaic7xxx_error(cmd) ((cmd)->SCp.Status)
795
796 /* 797 * Keep track of the targets returned status. 798 */ 799 #defineaic7xxx_status(cmd) ((cmd)->SCp.sent_command)
800
801 /* 802 * The position of the SCSI commands scb within the scb array. 803 */ 804 #defineaic7xxx_position(cmd) ((cmd)->SCp.have_data_in)
805
806 /* 807 * Since the sequencer code DMAs the scatter-gather structures 808 * directly from memory, we use this macro to assert that the 809 * kernel structure hasn't changed. 810 */ 811 #defineSG_STRUCT_CHECK(sg) \
812 ((char *) &(sg).address - (char *) &(sg) != 0 || \
813 (char *) &(sg).length - (char *) &(sg) != 8 || \
814 sizeof((sg).address) != 4 || \
815 sizeof((sg).length) != 4 || \
816 sizeof(sg) != 12)
817
818 /* 819 * "Static" structures. Note that these are NOT initialized 820 * to zero inside the kernel - we have to initialize them all 821 * explicitly. 822 * 823 * We support multiple adapter cards per interrupt, but keep a 824 * linked list of Scsi_Host structures for each IRQ. On an interrupt, 825 * use the IRQ as an index into aic7xxx_boards[] to locate the card 826 * information. 827 */ 828 staticstructScsi_Host *aic7xxx_boards[MAXIRQ + 1];
829
830 /* 831 * When we detect and register the card, it is possible to 832 * have the card raise a spurious interrupt. Because we need 833 * to support multiple cards, we cannot tell which card caused 834 * the spurious interrupt. And, we might not even have added 835 * the card info to the linked list at the time the spurious 836 * interrupt gets raised. This variable is suppose to keep track 837 * of when we are registering a card and how many spurious 838 * interrupts we have encountered. 839 * 840 * 0 - do not allow spurious interrupts. 841 * 1 - allow 1 spurious interrupt 842 * 2 - have 1 spurious interrupt, do not allow any more. 843 * 844 * I've made it an integer instead of a boolean in case we 845 * want to allow more than one spurious interrupt for debugging 846 * purposes. Otherwise, it could just go from true to false to 847 * true (or something like that). 848 * 849 * When the driver detects the cards, we'll set the count to 1 850 * for each card detection and registration. After the registration 851 * of a card completes, we'll set the count back to 0. So far, it 852 * seems to be enough to allow a spurious interrupt only during 853 * card registration; if a spurious interrupt is going to occur, 854 * this is where it happens. 855 * 856 * We should be able to find a way to avoid getting the spurious 857 * interrupt. But until we do, we have to keep this ugly code. 858 */ 859 staticintaic7xxx_spurious_count;
860
861 /* 862 * The driver keeps up to four scb structures per card in memory. Only the 863 * first 26 bytes of the structure are valid for the hardware, the rest used 864 * for driver level bookeeping. 865 */ 866 #defineSCB_DOWNLOAD_SIZE 26 /* amount to actually download */ 867 #defineSCB_UPLOAD_SIZE 26 /* amount to actually upload */ 868
869 structaic7xxx_scb{ 870 /* ------------ Begin hardware supported fields ---------------- */ 871 /*1 */unsignedcharcontrol;
872 #defineSCB_NEEDWDTR 0x80 /* Initiate Wide Negotiation */ 873 #defineSCB_DISCENB 0x40 /* Disconnection Enable */ 874 #defineSCB_TE 0x20 /* Tag enable */ 875 #defineSCB_NEEDSDTR 0x10 /* Initiate Sync Negotiation */ 876 #defineSCB_NEEDDMA 0x08 /* Refresh SCB from host ram */ 877 #defineSCB_DIS 0x04
878 #define SCB_TAG_TYPE 0x03
879 #define SIMPLE_QUEUE 0x00
880 #define HEAD_QUEUE 0x01
881 #define OR_QUEUE 0x02
882 /* ILLEGAL 0x03 */ 883 /*2 */unsignedchartarget_channel_lun; /* 4/1/3 bits */ 884 /*3 */unsignedcharSG_segment_count;
885 /*7 */unsignedcharSG_list_pointer[4] __attribute__ ((packed));
886 /*11*/unsignedcharSCSI_cmd_pointer[4] __attribute__ ((packed));
887 /*12*/unsignedcharSCSI_cmd_length;
888 /*14*/unsignedcharRESERVED[2]; /* must be zero */ 889 /*15*/unsignedchartarget_status;
890 /*18*/unsignedcharresidual_data_count[3];
891 /*19*/unsignedcharresidual_SG_segment_count;
892 /*23*/unsignedchardata_pointer[4] __attribute__ ((packed));
893 /*26*/unsignedchardata_count[3];
894 /*30*/unsignedcharhost_scb[4] __attribute__ ((packed));
895 /*31*/u_charnext_waiting; /* Used to thread SCBs awaiting selection. */ 896 #defineSCB_LIST_NULL 0xFF /* SCB list equivelent to NULL */ 897 #if 0
898 /* 899 * No real point in transferring this to the 900 * SCB registers. 901 */ 902 unsignedcharRESERVED[1];
903 #endif 904
905 /*-----------------end of hardware supported fields----------------*/ 906 structaic7xxx_scb *next; /* next ptr when in free list */ 907 Scsi_Cmnd *cmd; /* Scsi_Cmnd for this scb */ 908 intstate; /* current state of scb */ 909 #defineSCB_FREE 0x00
910 #defineSCB_ACTIVE 0x01
911 #defineSCB_ABORTED 0x02
912 #defineSCB_DEVICE_RESET 0x04
913 #define SCB_IMMED 0x08
914 #define SCB_SENSE 0x10
915 unsignedintposition; /* Position in scb array */ 916 structscatterlistsg;
917 structscatterlistsense_sg;
918 unsignedcharsense_cmd[6]; /* Allocate 6 characters for sense command */ 919 #defineTIMER_ENABLED 0x01
920 #defineTIMER_EXPIRED 0x02
921 #defineTIMED_CMD_DONE 0x04
922 volatileunsignedchartimer_status;
923 #ifndefAIC7XXX_POLL 924 structwait_queue *waiting; /* wait queue for device reset command */ 925 structwait_queuewaitq; /* waiting points to this */ 926 structtimer_listtimer; /* timeout for device reset command */ 927 #endif 928 };
929
930 typedefvoid (*timeout_fn)(unsignedlong);
931
932 staticstruct{ 933 unsignedcharerrno;
934 constchar *errmesg;
935 }hard_error[] = { 936 {ILLHADDR, "Illegal Host Access" },
937 {ILLSADDR, "Illegal Sequencer Address referrenced" },
938 {ILLOPCODE, "Illegal Opcode in sequencer program" },
939 {PARERR, "Sequencer Ram Parity Error" } 940 };
941
942 staticunsignedchar 943 generic_sense[] = {REQUEST_SENSE, 0, 0, 0, 255, 0 };
944
945 /* 946 * The maximum number of SCBs we could have for ANY type 947 * of card. DON'T FORGET TO CHANGE THE SCB MASK IN THE 948 * SEQUENCER CODE IF THIS IS MODIFIED! 949 */ 950 #defineAIC7XXX_MAXSCB 16
951
952 /* 953 * Define a structure used for each host adapter, only one per IRQ. 954 */ 955 structaic7xxx_host{ 956 intbase; /* card base address */ 957 intmaxscb; /* hardware SCBs */ 958 intnumscb; /* current number of scbs */ 959 intextended; /* extended xlate? */ 960 aha_typetype; /* card type */ 961 aha_bus_typebus_type; /* normal/twin/wide bus */ 962 unsignedchara_scanned; /* 0 not scanned, 1 scanned */ 963 unsignedcharb_scanned; /* 0 not scanned, 1 scanned */ 964 unsignedintisr_count; /* Interrupt count */ 965 volatileunsignedcharunpause; /* unpause value for HCNTRL */ 966 volatileunsignedcharpause; /* pause value for HCNTRL */ 967 volatileunsignedshortneedsdtr_copy; /* default config */ 968 volatileunsignedshortneedsdtr;
969 volatileunsignedshortsdtr_pending;
970 volatileunsignedshortneedwdtr_copy; /* default config */ 971 volatileunsignedshortneedwdtr;
972 volatileunsignedshortwdtr_pending;
973 volatileunsignedshortdiscenable; /* Targets allowed to disconnect */ 974 structseeprom_configseeprom;
975 inthave_seeprom;
976 structScsi_Host *next; /* allow for multiple IRQs */ 977 structaic7xxx_scbscb_array[AIC7XXX_MAXSCB]; /* active commands */ 978 structaic7xxx_scb *free_scb; /* list of free SCBs */ 979 #ifdefAIC7XXX_PROC_STATS 980 /* 981 * Statistics Kept: 982 * 983 * Total Xfers (count for each command that has a data xfer), 984 * broken down further by reads && writes. 985 * 986 * Binned sizes, writes && reads: 987 * < 512, 512, 1-2K, 2-4K, 4-8K, 8-16K, 16-32K, 32-64K, 64K-128K, > 128K 988 * 989 * Total amounts read/written above 512 bytes (amts under ignored) 990 */ 991 structaic7xxx_xferstats{ 992 longxfers; /* total xfer count */ 993 longw_total; /* total writes */ 994 longw_total512; /* 512 byte blocks written */ 995 longw_bins[10]; /* binned write */ 996 longr_total; /* total reads */ 997 longr_total512; /* 512 byte blocks read */ 998 longr_bins[10]; /* binned reads */ 999 }stats[2][16][8]; /* channel, target, lun */1000 #endif/* AIC7XXX_PROC_STATS */1001 };
1002
1003 structaic7xxx_host_config{1004 intirq; /* IRQ number */1005 intbase; /* I/O base */1006 intmaxscb; /* hardware SCBs */1007 intunpause; /* unpause value for HCNTRL */1008 intpause; /* pause value for HCNTRL */1009 intscsi_id; /* host SCSI ID */1010 intscsi_id_b; /* host SCSI ID B channel for twin cards */1011 intextended; /* extended xlate? */1012 intbusrtime; /* bus release time */1013 aha_typetype; /* card type */1014 aha_bus_typebus_type; /* normal/twin/wide bus */1015 aha_status_typeparity; /* bus parity enabled/disabled */1016 aha_status_typelow_term; /* bus termination low byte */1017 aha_status_typehigh_term; /* bus termination high byte (wide cards only) */1018 };
1019
1020 /*1021 * Valid SCSIRATE values. (p. 3-17)1022 * Provides a mapping of tranfer periods in ns to the proper value to1023 * stick in the scsiscfr reg to use that transfer rate.1024 */1025 staticstruct{1026 shortperiod;
1027 shortrate;
1028 constchar *english;
1029 }aic7xxx_syncrates[] = {1030 { 100, 0, "10.0" },
1031 { 125, 1, "8.0" },
1032 { 150, 2, "6.67" },
1033 { 175, 3, "5.7" },
1034 { 200, 4, "5.0" },
1035 { 225, 5, "4.4" },
1036 { 250, 6, "4.0" },
1037 { 275, 7, "3.6" }1038 };
1039
1040 staticintnum_aic7xxx_syncrates =
1041 sizeof(aic7xxx_syncrates) / sizeof(aic7xxx_syncrates[0]);
1042
1043 #ifdefAIC7XXX_DEBUG1044
1045 staticvoid1046 debug(constchar *fmt, ...)
/* */1047 {1048 va_listap;
1049 charbuf[256];
1050
1051 va_start(ap, fmt);
1052 vsprintf(buf, fmt, ap);
1053 printk(buf);
1054 va_end(ap);
1055 }1056
1057 staticvoid1058 debug_config(structaic7xxx_host_config *p)
/* */1059 {1060 inthost_conf, scsi_conf;
1061 unsignedcharbrelease;
1062 unsignedchardfthresh;
1063
1064 staticintDFT[] = { 0, 50, 75, 100 };
1065 staticintSST[] = { 256, 128, 64, 32 };
1066 staticconstchar *BUSW[] = { "", "-TWIN", "-WIDE" };
1067
1068 host_conf = inb(HA_HOSTCONF(p->base));
1069 scsi_conf = inb(HA_SCSICONF(p->base));
1070
1071 /*1072 * The 7870 gets the bus release time and data FIFO threshold1073 * from the serial EEPROM (stored in the config structure) and1074 * scsi_conf register respectively. The 7770 gets the bus1075 * release time and data FIFO threshold from the scsi_conf and1076 * host_conf registers respectively.1077 */1078 if ((p->type == AIC_274x) || (p->type == AIC_284x))
1079 {1080 dfthresh = (host_conf >> 6);
1081 }1082 else1083 {1084 dfthresh = (scsi_conf >> 6);
1085 }1086
1087 brelease = p->busrtime;
1088 if (brelease == 0)
1089 {1090 brelease = 2;
1091 }1092
1093 switch (p->type)
1094 {1095 caseAIC_274x:
1096 printk("AIC7770%s AT EISA SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1097 break;
1098
1099 caseAIC_284x:
1100 printk("AIC7770%s AT VLB SLOT %d:\n", BUSW[p->bus_type], p->base >> 12);
1101 break;
1102
1103 caseAIC_7870:
1104 printk("AIC7870%s (PCI-bus):\n", BUSW[p->bus_type]);
1105 break;
1106
1107 caseAIC_7850:
1108 printk("AIC7850%s (PCI-bus):\n", BUSW[p->bus_type]);
1109 break;
1110
1111 caseAIC_7872:
1112 printk("AIC7872%s (PCI-bus):\n", BUSW[p->bus_type]);
1113 break;
1114
1115 default:
1116 panic("aic7xxx debug_config: internal error\n");
1117 }1118
1119 printk(" irq %d\n"
1120 " bus release time %d bclks\n"
1121 " data fifo threshold %d%%\n",
1122 p->irq,
1123 brelease,
1124 DFT[dfthresh]);
1125
1126 printk(" SCSI CHANNEL A:\n"
1127 " scsi id %d\n"
1128 " scsi selection timeout %d ms\n"
1129 " scsi bus reset at power-on %sabled\n",
1130 scsi_conf & 0x07,
1131 SST[(scsi_conf >> 3) & 0x03],
1132 (scsi_conf & 0x40) ? "en" : "dis");
1133
1134 if (((p->type == AIC_274x) || (p->type == AIC_284x)) && p->parity == AIC_UNKNOWN)
1135 {1136 /*1137 * Set the parity for 7770 based cards.1138 */1139 p->parity = (scsi_conf & 0x20) ? AIC_ENABLED : AIC_DISABLED;
1140 }1141 if (p->parity != AIC_UNKNOWN)
1142 {1143 printk(" scsi bus parity %sabled\n",
1144 (p->parity == AIC_ENABLED) ? "en" : "dis");
1145 }1146
1147 if (p->type == AIC_274x)
1148 {1149 p->low_term = (scsi_conf & 0x80) ? AIC_ENABLED : AIC_DISABLED;
1150 }1151 if (p->low_term != AIC_UNKNOWN)
1152 {1153 printk(" scsi bus termination (low byte) %sabled\n",
1154 (p->low_term == AIC_ENABLED) ? "en" : "dis");
1155 }1156 if ((p->bus_type == AIC_WIDE) && (p->high_term != AIC_UNKNOWN))
1157 {1158 printk(" scsi bus termination (high byte) %sabled\n",
1159 (p->high_term == AIC_ENABLED) ? "en" : "dis");
1160 }1161 }1162
1163 staticvoid1164 debug_scb(structaic7xxx_scb *scb)
/* */1165 {1166 printk("control 0x%x, tcl 0x%x, sg_count %d, sg_ptr 0x%x, cmdp 0x%x, cmdlen %d\n",
1167 scb->control, scb->target_channel_lun, scb->SG_segment_count,
1168 (scb->SG_list_pointer[3] << 24) | (scb->SG_list_pointer[2] << 16) |
1169 (scb->SG_list_pointer[1] << 8) | scb->SG_list_pointer[0],
1170 (scb->SCSI_cmd_pointer[3] << 24) | (scb->SCSI_cmd_pointer[2] << 16) |
1171 (scb->SCSI_cmd_pointer[1] << 8) | scb->SCSI_cmd_pointer[0],
1172 scb->SCSI_cmd_length);
1173 printk("reserved 0x%x, target status 0x%x, resid SG count %d, resid data count %d\n",
1174 (scb->RESERVED[1] << 8) | scb->RESERVED[0], scb->target_status,
1175 scb->residual_SG_segment_count, (scb->residual_data_count[2] << 16) |
1176 (scb->residual_data_count[1] << 8) | scb->residual_data_count[0]);
1177 printk("data ptr 0x%x, data count %d, host scb 0x%x, next waiting %d\n",
1178 (scb->data_pointer[3] << 24) | (scb->data_pointer[2] << 16) |
1179 (scb->data_pointer[1] << 8) | scb->data_pointer[0],
1180 (scb->data_count[2] << 16) | (scb->data_count[1] << 8) | scb->data_count[0],
1181 (unsignedint) scb->host_scb, scb->next_waiting);
1182 printk("next ptr 0x%lx, Scsi Cmnd 0x%lx, state 0x%x, position %d\n",
1183 (unsignedlong) scb->next, (unsignedlong) scb->cmd, scb->state,
1184 scb->position);
1185 }1186
1187 #else1188 # definedebug(fmt, args...)
1189 # definedebug_config(x)
1190 # definedebug_scb(x)
1191 #endifAIC7XXX_DEBUG1192
1193 /*1194 * XXX - these options apply unilaterally to _all_ 274x/284x/294x1195 * cards in the system. This should be fixed, but then,1196 * does anyone really have more than one in a machine?1197 */1198 staticintaic7xxx_extended = 0; /* extended translation on? */1199 staticintaic7xxx_no_reset = 0; /* no resetting of SCSI bus */1200
1201 /*+F*************************************************************************1202 * Function:1203 * aic7xxx_setup1204 *1205 * Description:1206 * Handle Linux boot parameters.1207 *-F*************************************************************************/1208 void1209 aic7xxx_setup(char *s, int *dummy)
/* */1210 {1211 inti;
1212 char *p;
1213
1214 staticstruct{1215 constchar *name;
1216 int *flag;
1217 }options[] = {1218 { "extended", &aic7xxx_extended},
1219 { "no_reset", &aic7xxx_no_reset},
1220 {NULL, NULL}1221 };
1222
1223 for (p = strtok(s, ","); p; p = strtok(NULL, ","))
1224 {1225 for (i = 0; options[i].name; i++)
1226 {1227 if (!strcmp(options[i].name, p))
1228 {1229 *(options[i].flag) = !0;
1230 }1231 }1232 }1233 }1234
1235 /*+F*************************************************************************1236 * Function:1237 * aic7xxx_loadseq1238 *1239 * Description:1240 * Load the sequencer code into the controller memory.1241 *-F*************************************************************************/1242 staticvoid1243 aic7xxx_loadseq(intbase)
/* */1244 {1245 staticunsignedcharseqprog[] = {1246 /*1247 * Each sequencer instruction is 29 bits1248 * long (fill in the excess with zeroes)1249 * and has to be loaded from least -> most1250 * significant byte, so this table has the1251 * byte ordering reversed.1252 */1253 # include "aic7xxx_seq.h"
1254 };
1255
1256 /*1257 * When the AIC-7770 is paused (as on chip reset), the1258 * sequencer address can be altered and a sequencer1259 * program can be loaded by writing it, byte by byte, to1260 * the sequencer RAM port - the Adaptec documentation1261 * recommends using REP OUTSB to do this, hence the inline1262 * assembly. Since the address autoincrements as we load1263 * the program, reset it back to zero afterward. Disable1264 * sequencer RAM parity error detection while loading, and1265 * make sure the LOADRAM bit is enabled for loading.1266 */1267 outb(PERRORDIS | SEQRESET | LOADRAM, SEQCTL(base));
1268
1269 asmvolatile("cld\n\t"
1270 "rep\n\t"
1271 "outsb"
1272 : /* no output */1273 :"S" (seqprog), "c" (sizeof(seqprog)), "d" (SEQRAM(base))
1274 :"si", "cx", "dx");
1275
1276 /*1277 * WARNING! This is a magic sequence! After extensive1278 * experimentation, it seems that you MUST turn off the1279 * LOADRAM bit before you play with SEQADDR again, else1280 * you will end up with parity errors being flagged on1281 * your sequencer program. (You would also think that1282 * turning off LOADRAM and setting SEQRESET to reset the1283 * address to zero would work, but you need to do it twice1284 * for it to take effect on the address. Timing problem?)1285 */1286 do{1287 /*1288 * Actually, reset it until1289 * the address shows up as1290 * zero just to be safe..1291 */1292 outb(SEQRESET | FASTMODE, SEQCTL(base));
1293 }while ((inb(SEQADDR0(base)) != 0) && (inb(SEQADDR1(base)) != 0));
1294 }1295
1296 /*+F*************************************************************************1297 * Function:1298 * aic7xxx_delay1299 *1300 * Description:1301 * Delay for specified amount of time.1302 *-F*************************************************************************/1303 staticvoid1304 aic7xxx_delay(intseconds)
/* */1305 {1306 unsignedlongi;
1307
1308 i = jiffies + (seconds * HZ); /* compute time to stop */1309
1310 while (jiffies < i)
1311 {1312 ; /* Do nothing! */1313 }1314 }1315
1316 #ifdefAIC7XXX_POLL1317 /*+F*************************************************************************1318 * Function:1319 * aic7xxx_poll_scb1320 *1321 * Description:1322 * Function to poll for command completion when in aborting an SCB.1323 *-F*************************************************************************/1324 staticvoid1325 aic7xxx_poll_scb(structaic7xxx_host *p,
/* */1326 structaic7xxx_scb *scb,
1327 unsignedlongtimeout_ticks)
1328 {1329 unsignedlongtimer_expiration = jiffies + timeout_ticks;
1330
1331 while ((jiffies < timer_expiration) && !(scb->timer_status & TIMED_CMD_DONE))
1332 {1333 udelay(1000); /* delay for 1 msec. */1334 }1335 }1336
1337 #else1338 /*+F*************************************************************************1339 * Function:1340 * aic7xxx_scb_timeout1341 *1342 * Description:1343 * Called when a SCB reset command times out. The input is actually1344 * a pointer to the SCB.1345 *-F*************************************************************************/1346 staticvoid1347 aic7xxx_scb_timeout(unsignedlongdata)
/* */1348 {1349 structaic7xxx_scb *scb = (structaic7xxx_scb *) data;
1350
1351 scb->timer_status |= TIMER_EXPIRED;
1352 wake_up(&(scb->waiting));
1353 }1354
1355 /*+F*************************************************************************1356 * Function:1357 * aic7xxx_scb_untimeout1358 *1359 * Description:1360 * This function clears the timeout and wakes up a waiting SCB.1361 *-F*************************************************************************/1362 staticvoid1363 aic7xxx_scb_untimeout(structaic7xxx_scb *scb)
/* */1364 {1365 if (scb->timer_status & TIMER_ENABLED)
1366 {1367 scb->timer_status = TIMED_CMD_DONE;
1368 wake_up(&(scb->waiting));
1369 }1370 }1371 #endif1372
1373 /*+F*************************************************************************1374 * Function:1375 * aic7xxx_scb_tsleep1376 *1377 * Description:1378 * Emulates a BSD tsleep where a process can sleep for a specified1379 * amount of time, but may be awakened before that. Linux provides1380 * a sleep_on, wake_up, add_timer, and del_timer which can be used to1381 * emulate tsleep, but there's not enough information available on1382 * how to use them. For now, we'll just poll for SCB completion.1383 *1384 * The parameter ticks is the number of clock ticks1385 * to wait before a timeout. A 0 is returned if the scb does not1386 * timeout, 1 is returned for a timeout.1387 *-F*************************************************************************/1388 staticint1389 aic7xxx_scb_tsleep(structaic7xxx_host *p,
/* */1390 structaic7xxx_scb *scb,
1391 unsignedlongticks)
1392 {1393 scb->timer_status = TIMER_ENABLED;
1394 #ifdefAIC7XXX_POLL1395 UNPAUSE_SEQUENCER(p);
1396 aic7xxx_poll_scb(p, scb, ticks);
1397 #else1398 scb->waiting = &(scb->waitq);
1399 scb->timer.expires = jiffies + ticks;
1400 scb->timer.data = (unsignedlong) scb;
1401 scb->timer.function = (timeout_fn) aic7xxx_scb_timeout;
1402 add_timer(&scb->timer);
1403 UNPAUSE_SEQUENCER(p);
1404 sleep_on(&(scb->waiting));
1405 del_timer(&scb->timer);
1406 #endif1407 if (!(scb->timer_status & TIMED_CMD_DONE))
1408 {1409 scb->timer_status = 0x0;
1410 return (1);
1411 }1412 else1413 {1414 scb->timer_status = 0x0;
1415 return (0);
1416 }1417 }1418
1419 /*+F*************************************************************************1420 * Function:1421 * rcs_version1422 *1423 * Description:1424 * Return a string containing just the RCS version number from either1425 * an Id or Revison RCS clause.1426 *-F*************************************************************************/1427 constchar *
1428 rcs_version(constchar *version_info)
/* */1429 {1430 staticcharbuf[10];
1431 char *bp, *ep;
1432
1433 bp = NULL;
1434 strcpy(buf, "????");
1435 if (!strncmp(version_info, "$Id: ", 5))
1436 {1437 if ((bp = strchr(version_info, ' ')) != NULL)
1438 {1439 bp++;
1440 if ((bp = strchr(bp, ' ')) != NULL)
1441 {1442 bp++;
1443 }1444 }1445 }1446 else1447 {1448 if (!strncmp(version_info, "$Revision: ", 11))
1449 {1450 if ((bp = strchr(version_info, ' ')) != NULL)
1451 {1452 bp++;
1453 }1454 }1455 }1456
1457 if (bp != NULL)
1458 {1459 if ((ep = strchr(bp, ' ')) != NULL)
1460 {1461 registerintlen = ep - bp;
1462
1463 strncpy(buf, bp, len);
1464 buf[len] = '\0';
1465 }1466 }1467
1468 returnbuf;
1469 }1470
1471 /*+F*************************************************************************1472 * Function:1473 * aic7xxx_info1474 *1475 * Description:1476 * Return a string describing the driver.1477 *-F*************************************************************************/1478 constchar *
1479 aic7xxx_info(structScsi_Host *notused)
/* */1480 {1481 staticcharbuffer[128];
1482
1483 strcpy(buffer, "Adaptec AHA274x/284x/294x (EISA/VLB/PCI-Fast SCSI) ");
1484 strcat(buffer, rcs_version(AIC7XXX_C_VERSION));
1485 strcat(buffer, "/");
1486 strcat(buffer, rcs_version(AIC7XXX_H_VERSION));
1487 strcat(buffer, "/");
1488 strcat(buffer, rcs_version(AIC7XXX_SEQ_VER));
1489
1490 returnbuffer;
1491 }1492
1493 /*+F*************************************************************************1494 * Function:1495 * aic7xxx_length1496 *1497 * Description:1498 * How much data should be transferred for this SCSI command? Stop1499 * at segment sg_last if it's a scatter-gather command so we can1500 * compute underflow easily.1501 *-F*************************************************************************/1502 staticunsigned1503 aic7xxx_length(Scsi_Cmnd *cmd, intsg_last)
/* */1504 {1505 inti, segments;
1506 unsignedlength;
1507 structscatterlist *sg;
1508
1509 segments = cmd->use_sg - sg_last;
1510 sg = (structscatterlist *) cmd->buffer;
1511
1512 if (cmd->use_sg)
1513 {1514 for (i = length = 0; (i < cmd->use_sg) && (i < segments); i++)
1515 {1516 length += sg[i].length;
1517 }1518 }1519 else1520 {1521 length = cmd->request_bufflen;
1522 }1523
1524 return (length);
1525 }1526
1527 /*+F*************************************************************************1528 * Function:1529 * aic7xxx_scsirate1530 *1531 * Description:1532 * Look up the valid period to SCSIRATE conversion in our table1533 *-F*************************************************************************/1534 staticvoid1535 aic7xxx_scsirate(unsignedchar *scsirate, unsignedcharperiod,
/* */1536 unsignedcharoffset, inttarget, charchannel)
1537 {1538 inti;
1539
1540 for (i = 0; i < num_aic7xxx_syncrates; i++)
1541 {1542 if ((aic7xxx_syncrates[i].period - period) >= 0)
1543 {1544 *scsirate = (aic7xxx_syncrates[i].rate << 4) | (offset & 0x0F);
1545 printk("aic7xxx: target %d, channel %c, now synchronous at %sMb/s, "
1546 "offset = 0x%x\n",
1547 target, channel, aic7xxx_syncrates[i].english, offset);
1548 return;
1549 }1550 }1551
1552 /*1553 * Default to asyncronous transfer1554 */1555 *scsirate = 0;
1556 printk("aic7xxx: target %d, channel %c, using asynchronous transfers\n",
1557 target, channel);
1558 }1559
1560 /*+F*************************************************************************1561 * Function:1562 * aic7xxx_putscb1563 *1564 * Description:1565 * Transfer a SCB to the controller.1566 *-F*************************************************************************/1567 staticvoid1568 aic7xxx_putscb(intbase, structaic7xxx_scb *scb)
/* */1569 {1570 /*1571 * All we need to do, is to output the position1572 * of the SCB in the SCBARRAY to the QINFIFO1573 * of the host adapter.1574 */1575 outb(scb->position, QINFIFO(base));
1576 }1577
1578 /*+F*************************************************************************1579 * Function:1580 * aic7xxx_putscb_dma1581 *1582 * Description:1583 * DMA a SCB to the controller.1584 *-F*************************************************************************/1585 staticvoid1586 aic7xxx_putscb_dma(intbase, structaic7xxx_scb *scb)
/* */1587 {1588 /*1589 * By turning on the SCB auto increment, any reference1590 * to the SCB I/O space postincrements the SCB address1591 * we're looking at. So turn this on and dump the relevant1592 * portion of the SCB to the card.1593 */1594 outb(SCBAUTO, SCBCNT(base));
1595
1596 asmvolatile("cld\n\t"
1597 "rep\n\t"
1598 "outsb"
1599 : /* no output */1600 :"S" (scb), "c" (31), "d" (SCBARRAY(base))
1601 :"si", "cx", "dx");
1602
1603 outb(0, SCBCNT(base));
1604 }1605
1606 /*+F*************************************************************************1607 * Function:1608 * aic7xxx_getscb1609 *1610 * Description:1611 * Get a SCB from the controller.1612 *-F*************************************************************************/1613 staticvoid1614 aic7xxx_getscb(intbase, structaic7xxx_scb *scb)
/* */1615 {1616 /*1617 * This is almost identical to aic7xxx_putscb().1618 */1619 outb(SCBAUTO, SCBCNT(base));
1620
1621 asmvolatile("cld\n\t"
1622 "rep\n\t"
1623 "insb"
1624 : /* no output */1625 :"D" (scb), "c" (SCB_UPLOAD_SIZE), "d" (SCBARRAY(base))
1626 :"di", "cx", "dx");
1627
1628 outb(0, SCBCNT(base));
1629 }1630
1631 /*+F*************************************************************************1632 * Function:1633 * aic7xxx_match_scb1634 *1635 * Description:1636 * Checks to see if an scb matches the target/channel as specified.1637 * If target is ALL_TARGETS (-1), then we're looking for any device1638 * on the specified channel; this happens when a channel is going1639 * to be reset and all devices on that channel must be aborted.1640 *-F*************************************************************************/1641 staticint1642 aic7xxx_match_scb(structaic7xxx_scb *scb, inttarget, charchannel)
/* */1643 {1644 inttarg = (scb->target_channel_lun >> 4) & 0x0F;
1645 charchan = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1646
1647 if (target == ALL_TARGETS)
1648 {1649 return (chan == channel);
1650 }1651 else1652 {1653 return ((chan == channel) && (targ == target));
1654 }1655 }1656
1657 /*+F*************************************************************************1658 * Function:1659 * aic7xxx_unbusy_target1660 *1661 * Description:1662 * Set the specified target inactive.1663 *-F*************************************************************************/1664 staticvoid1665 aic7xxx_unbusy_target(unsignedchartarget, charchannel, intbase)
/* */1666 {1667 unsignedcharactive;
1668 unsignedlongactive_port = HA_ACTIVE0(base);
1669
1670 if ((target > 0x07) || (channel == 'B'))
1671 {1672 /*1673 * targets on the Second channel or above id 7 store info in byte two1674 * of HA_ACTIVE1675 */1676 active_port++;
1677 }1678 active = inb(active_port);
1679 active &= ~(0x01 << (target & 0x07));
1680 outb(active_port, active);
1681 }1682
1683 /*+F*************************************************************************1684 * Function:1685 * aic7xxx_done1686 *1687 * Description:1688 * Calls the higher level scsi done function and frees the scb.1689 *-F*************************************************************************/1690 staticvoid1691 aic7xxx_done(structaic7xxx_host *p, structaic7xxx_scb *scb)
/* */1692 {1693 longflags;
1694 Scsi_Cmnd *cmd = scb->cmd;
1695
1696 if (scb->timer_status & TIMER_ENABLED)
1697 {1698 #ifdefAIC7XXX_POLL1699 scb->timer_status |= TIMED_CMD_DONE;
1700 #else1701 aic7xxx_scb_untimeout(scb);
1702 #endif1703 }1704 else1705 {1706 /*1707 * This is a critical section, since we don't want the1708 * queue routine mucking with the host data.1709 */1710 save_flags(flags);
1711 cli();
1712
1713 /*1714 * Process the command after marking the scb as free1715 * and adding it to the free list.1716 */1717 scb->state = SCB_FREE;
1718 scb->next = p->free_scb;
1719 p->free_scb = &(p->scb_array[scb->position]);
1720 scb->cmd = NULL;
1721
1722 restore_flags(flags);
1723
1724 cmd->scsi_done(cmd);
1725 }1726 }1727
1728 /*+F*************************************************************************1729 * Function:1730 * aic7xxx_add_waiting_scb1731 *1732 * Description:1733 * Add this SCB to the "waiting for selection" list.1734 *-F*************************************************************************/1735 staticvoid1736 aic7xxx_add_waiting_scb(u_longbase,
/* */1737 structaic7xxx_scb *scb,
1738 insert_typewhere)
1739 {1740 unsignedcharhead, tail;
1741 unsignedcharcurscb;
1742
1743 curscb = inb(SCBPTR(base));
1744 head = inb(WAITING_SCBH(base));
1745 tail = inb(WAITING_SCBT(base));
1746 if (head == SCB_LIST_NULL)
1747 {1748 /*1749 * List was empty1750 */1751 head = scb->position;
1752 tail = SCB_LIST_NULL;
1753 }1754 else1755 {1756 if (where == LIST_HEAD)
1757 {1758 outb(scb->position, SCBPTR(base));
1759 outb(head, SCBARRAY(base) + 30);
1760 head = scb->position;
1761 }1762 else1763 {1764 if (tail == SCB_LIST_NULL)
1765 {1766 /*1767 * List had one element1768 */1769 tail = scb->position;
1770 outb(head, SCBPTR(base));
1771 outb(tail, SCBARRAY(base) + 30);
1772 }1773 else1774 {1775 if (where == LIST_SECOND)
1776 {1777 unsignedcharthird_scb;
1778
1779 outb(head, SCBPTR(base));
1780 third_scb = inb(SCBARRAY(base) + 30);
1781 outb(scb->position, SCBARRAY(base) + 30);
1782 outb(scb->position, SCBPTR(base));
1783 outb(third_scb, SCBARRAY(base) + 30);
1784 }1785 else1786 {1787 outb(tail, SCBPTR(base));
1788 tail = scb->position;
1789 outb(tail, SCBARRAY(base) + 30);
1790 }1791 }1792 }1793 }1794 outb(head, WAITING_SCBH(base));
1795 outb(tail, WAITING_SCBT(base));
1796 outb(curscb, SCBPTR(base));
1797 }1798
1799 /*+F*************************************************************************1800 * Function:1801 * aic7xxx_abort_waiting_scb1802 *1803 * Description:1804 * Manipulate the waiting for selection list and return the1805 * scb that follows the one that we remove.1806 *-F*************************************************************************/1807 staticunsignedchar1808 aic7xxx_abort_waiting_scb(structaic7xxx_host *p, structaic7xxx_scb *scb,
/* */1809 unsignedcharprev, unsignedchartimedout_scb)
1810 {1811 unsignedcharcurscb, next;
1812 inttarget = (scb->target_channel_lun >> 4) & 0x0F;
1813 charchannel = (scb->target_channel_lun & SELBUSB) ? 'B' : 'A';
1814 intbase = p->base;
1815
1816 /*1817 * Select the SCB we want to abort and1818 * pull the next pointer out of it.1819 */1820 curscb = inb(SCBPTR(base));
1821 outb(scb->position, SCBPTR(base));
1822 next = inb(SCBARRAY(base) + 30);
1823
1824 /*1825 * Clear the necessary fields1826 */1827 outb(SCB_NEEDDMA, SCBARRAY(base));
1828 outb(SCB_LIST_NULL, SCBARRAY(base) + 30);
1829 aic7xxx_unbusy_target(target, channel, base);
1830
1831 /*1832 * Update the waiting list1833 */1834 if (prev == SCB_LIST_NULL)
1835 {1836 /*1837 * First in the list1838 */1839 outb(next, WAITING_SCBH(base));
1840 }1841 else1842 {1843 /*1844 * Select the scb that pointed to us and update its next pointer.1845 */1846 outb(prev, SCBPTR(base));
1847 outb(next, SCBARRAY(base) + 30);
1848 }1849 /*1850 * Update the tale pointer1851 */1852 if (inb(WAITING_SCBT(base)) == scb->position)
1853 {1854 outb(prev, WAITING_SCBT(base));
1855 }1856
1857 /*1858 * Point us back at the original scb position1859 * and inform the SCSI system that the command1860 * has been aborted.1861 */1862 outb(curscb, SCBPTR(base));
1863 scb->state |= SCB_ABORTED;
1864 scb->cmd->result = (DID_RESET << 16);
1865 aic7xxx_done(p, scb);
1866
1867 return (next);
1868 }1869
1870 /*+F*************************************************************************1871 * Function:1872 * aic7xxx_reset_device1873 *1874 * Description:1875 * The device at the given target/channel has been reset. Abort1876 * all active and queued scbs for that target/channel.1877 *-F*************************************************************************/1878 staticint1879 aic7xxx_reset_device(structaic7xxx_host *p, inttarget, charchannel,
/* */1880 unsignedchartimedout_scb)
1881 {1882 intbase = p->base;
1883 structaic7xxx_scb *scb;
1884 unsignedcharactive_scb;
1885 inti = 0;
1886 intfound = 0;
1887
1888 /*1889 * Restore this when we're done1890 */1891 active_scb = inb(SCBPTR(base));
1892
1893 /*1894 * Search the QINFIFO.1895 */1896 {1897 intsaved_queue[AIC7XXX_MAXSCB];
1898 intqueued = inb(QINCNT(base));
1899
1900 for (i = 0; i < (queued - found); i++)
1901 {1902 saved_queue[i] = inb(QINFIFO(base));
1903 scb = &(p->scb_array[saved_queue[i]]);
1904 if (aic7xxx_match_scb(scb, target, channel))
1905 {1906 /*1907 * We found an scb that needs to be aborted.1908 */1909 scb->state |= SCB_ABORTED;
1910 scb->cmd->result = (DID_RESET << 16);
1911 aic7xxx_done(p, scb);
1912 outb(scb->position, SCBPTR(base));
1913 outb(SCB_NEEDDMA, SCBARRAY(base));
1914 i--;
1915 found++;
1916 }1917 }1918 /*1919 * Now put the saved scbs back.1920 */1921 for (queued = 0; queued < i; queued++)
1922 {1923 outb(saved_queue[queued], QINFIFO(base));
1924 }1925 }1926
1927 /*1928 * Search waiting for selection list.1929 */1930 {1931 unsignedcharnext, prev;
1932
1933 next = inb(WAITING_SCBH(base)); /* Start at head of list. */1934 prev = SCB_LIST_NULL;
1935
1936 while (next != SCB_LIST_NULL)
1937 {1938 scb = &(p->scb_array[next]);
1939 /*1940 * Select the SCB.1941 */1942 if (aic7xxx_match_scb(scb, target, channel))
1943 {1944 next = aic7xxx_abort_waiting_scb(p, scb, prev, timedout_scb);
1945 found++;
1946 }1947 else1948 {1949 outb(scb->position, SCBPTR(base));
1950 prev = next;
1951 next = inb(SCBARRAY(base) + 30);
1952 }1953 }1954 }1955
1956 /*1957 * Go through the entire SCB array now and look for1958 * commands for this target that are active. These1959 * are other (most likely tagged) commands that1960 * were disconnected when the reset occured.1961 */1962 for(i = 0; i < p->numscb; i++)
1963 {1964 scb = &(p->scb_array[i]);
1965 if ((scb->state & SCB_ACTIVE) && aic7xxx_match_scb(scb, target, channel))
1966 {1967 /*1968 * Ensure the target is "free"1969 */1970 aic7xxx_unbusy_target(target, channel, base);
1971 outb(scb->position, SCBPTR(base));
1972 outb(SCB_NEEDDMA, SCBARRAY(base));
1973 scb->state |= SCB_ABORTED;
1974 scb->cmd->result = (DID_RESET << 16);
1975 aic7xxx_done(p, scb);
1976 found++;
1977 }1978 }1979
1980 outb(active_scb, SCBPTR(base));
1981 return (found);
1982 }1983
1984 /*+F*************************************************************************1985 * Function:1986 * aic7xxx_reset_current_bus1987 *1988 * Description:1989 * Reset the current SCSI bus.1990 *-F*************************************************************************/1991 staticvoid1992 aic7xxx_reset_current_bus(intbase)
/* */1993 {1994 outb(SCSIRSTO, SCSISEQ(base));
1995 udelay(1000);
1996 outb(0, SCSISEQ(base));
1997 }1998
1999 /*+F*************************************************************************2000 * Function:2001 * aic7xxx_reset_channel2002 *2003 * Description:2004 * Reset the channel.2005 *-F*************************************************************************/2006 staticint2007 aic7xxx_reset_channel(structaic7xxx_host *p, charchannel,
/* */2008 unsignedchartimedout_scb)
2009 {2010 intbase = p->base;
2011 unsignedcharsblkctl;
2012 charcur_channel;
2013 unsignedlongoffset, offset_max;
2014 intfound;
2015
2016 /*2017 * Clean up all the state information for the2018 * pending transactions on this bus.2019 */2020 found = aic7xxx_reset_device(p, ALL_TARGETS, channel, timedout_scb);
2021
2022 if (channel == 'B')
2023 {2024 p->needsdtr |= (p->needsdtr_copy & 0xFF00);
2025 p->sdtr_pending &= 0x00FF;
2026 outb(0, HA_ACTIVE1(base));
2027 offset = HA_TARG_SCRATCH(base) + 8;
2028 offset_max = HA_TARG_SCRATCH(base) + 16;
2029 }2030 else2031 {2032 if (p->bus_type == AIC_WIDE)
2033 {2034 p->needsdtr = p->needsdtr_copy;
2035 p->needwdtr = p->needwdtr_copy;
2036 p->sdtr_pending = 0;
2037 p->wdtr_pending = 0;
2038 outb(0, HA_ACTIVE0(base));
2039 outb(0, HA_ACTIVE1(base));
2040 offset = HA_TARG_SCRATCH(base);
2041 offset_max = HA_TARG_SCRATCH(base) + 16;
2042 }2043 else2044 {2045 p->needsdtr |= (p->needsdtr_copy & 0x00FF);
2046 p->sdtr_pending &= 0xFF00;
2047 outb(0, HA_ACTIVE0(base));
2048 offset = HA_TARG_SCRATCH(base);
2049 offset_max = HA_TARG_SCRATCH(base) + 8;
2050 }2051 }2052 while (offset < offset_max)
2053 {2054 /*2055 * Revert to async/narrow transfers2056 * until we renegotiate.2057 */2058 u_chartarg_scratch;
2059 targ_scratch = inb(offset);
2060 targ_scratch &= SXFR;
2061 outb(targ_scratch, offset);
2062 offset++;
2063 }2064
2065 /*2066 * Reset the bus and unpause/restart the controller2067 */2068
2069 /*2070 * Case 1: Command for another bus is active2071 */2072 sblkctl = inb(SBLKCTL(base));
2073 cur_channel = (sblkctl & SELBUSB) ? 'B' : 'A';
2074 if (cur_channel != channel)
2075 {2076 /*2077 * Stealthily reset the other bus without upsetting the current bus2078 */2079 outb(sblkctl ^ SELBUSB, SBLKCTL(base));
2080 aic7xxx_reset_current_bus(base);
2081 outb(sblkctl, SBLKCTL(base));
2082 UNPAUSE_SEQUENCER(p);
2083 }2084 /*2085 * Case 2: A command from this bus is active or we're idle2086 */2087 else2088 {2089 aic7xxx_reset_current_bus(base);
2090 RESTART_SEQUENCER(p);
2091 }2092
2093 returnfound;
2094 }2095
2096 /*+F*************************************************************************2097 * Function:2098 * aic7xxx_isr2099 *2100 * Description:2101 * SCSI controller interrupt handler.2102 *2103 * NOTE: Since we declared this using SA_INTERRUPT, interrupts should2104 * be disabled all through this function unless we say otherwise.2105 *-F*************************************************************************/2106 staticvoid2107 aic7xxx_isr(intirq, structpt_regs * regs)
/* */2108 {2109 intbase, intstat;
2110 structaic7xxx_host *p;
2111 structaic7xxx_scb *scb;
2112 unsignedcharha_flags, transfer;
2113 unsignedcharscsi_id, bus_width;
2114 unsignedcharoffset, rate, scratch, scratch_offset;
2115 unsignedcharmax_offset, rej_byte;
2116 unsignedshorttarget_mask, active;
2117 charchannel;
2118 void *addr;
2119 intactual;
2120 intscb_index;
2121 Scsi_Cmnd *cmd;
2122
2123 p = (structaic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2124
2125 /*2126 * Search for the host with a pending interrupt. If we can't find2127 * one, then we've encountered a spurious interrupt.2128 */2129 while ((p != NULL) && !(inb(INTSTAT(p->base)) & INT_PEND))
2130 {2131 if (p->next == NULL)
2132 {2133 p = NULL;
2134 }2135 else2136 {2137 p = (structaic7xxx_host *) p->next->hostdata;
2138 }2139 }2140
2141 if (p == NULL)
2142 {2143 if (aic7xxx_spurious_count == 1)
2144 {2145 aic7xxx_spurious_count = 2;
2146 printk("aic7xxx_isr: Encountered spurious interrupt.\n");
2147 return;
2148 }2149 else2150 {2151 /*2152 * The best we can do is to set p back to head of list and process2153 * the erroneous interrupt - most likely a BRKADRINT.2154 */2155 p = (structaic7xxx_host *) aic7xxx_boards[irq]->hostdata;
2156 }2157 }2158
2159 /*2160 * Keep track of interrupts for /proc/scsi2161 */2162 p->isr_count++;
2163
2164 if ((p->a_scanned == 0) && (p->isr_count == 1))
2165 {2166 /*2167 * We must only have one card at this IRQ and it must have been2168 * added to the board data before the spurious interrupt occurred.2169 * It is sufficient that we check isr_count and not the spurious2170 * interrupt count.2171 */2172 printk("aic7xxx_isr: Encountered spurious interrupt.\n");
2173 return;
2174 }2175
2176 base = p->base;
2177 /*2178 * Handle all the interrupt sources - especially for SCSI2179 * interrupts, we won't get a second chance at them.2180 */2181 intstat = inb(INTSTAT(base));
2182
2183 if (intstat & BRKADRINT)
2184 {2185 inti;
2186 unsignedcharerrno = inb(ERROR(base));
2187
2188 printk("aic7xxx_isr: brkadrint (0x%x):\n", errno);
2189 for (i = 0; i < NUMBER(hard_error); i++)
2190 {2191 if (errno & hard_error[i].errno)
2192 {2193 printk(" %s\n", hard_error[i].errmesg);
2194 }2195 }2196
2197 panic("aic7xxx_isr: brkadrint, error = 0x%x, seqaddr = 0x%x\n",
2198 inb(ERROR(base)), (inb(SEQADDR1(base)) << 8) | inb(SEQADDR0(base)));
2199 }2200
2201 if (intstat & SEQINT)
2202 {2203 /*2204 * Although the sequencer is paused immediately on2205 * a SEQINT, an interrupt for a SCSIINT condition will2206 * unpaused the sequencer before this point.2207 */2208 PAUSE_SEQUENCER(p);
2209
2210 scsi_id = (inb(SCSIID(base)) >> 4) & 0x0F;
2211 scratch_offset = scsi_id;
2212 channel = 'A';
2213 if (inb(SBLKCTL(base)) & SELBUSB)
2214 {2215 channel = 'B';
2216 scratch_offset += 8;
2217 }2218 target_mask = (0x01 << scratch_offset);
2219
2220 switch (intstat & SEQINT_MASK)
2221 {2222 caseBAD_PHASE:
2223 panic("aic7xxx_isr: unknown scsi bus phase\n");
2224 break;
2225
2226 caseSEND_REJECT:
2227 rej_byte = inb(HA_REJBYTE(base));
2228 if (rej_byte != 0x20)
2229 {2230 debug("aic7xxx_isr warning: issuing message reject, 1st byte 0x%x\n",
2231 rej_byte);
2232 }2233 else2234 {2235 scb_index = inb(SCBPTR(base));
2236 scb = &(p->scb_array[scb_index]);
2237 printk("aic7xxx_isr warning: Tagged message rejected for target %d,"
2238 " channel %c.\n", scsi_id, channel);
2239 scb->cmd->device->tagged_supported = 0;
2240 scb->cmd->device->tagged_queue = 0;
2241 }2242 break;
2243
2244 caseNO_IDENT:
2245 panic("aic7xxx_isr: Target %d, channel %c, did not send an IDENTIFY "
2246 "message. SAVED_TCL = 0x%x\n",
2247 scsi_id, channel, inb(SAVED_TCL(base)));
2248 break;
2249
2250 caseNO_MATCH:
2251 printk("aic7xxx_isr: No active SCB for reconnecting target %d, "
2252 "channel %c - issuing ABORT\n", scsi_id, channel);
2253 printk("SAVED_TCL = 0x%x\n", inb(SAVED_TCL(base)));
2254 aic7xxx_unbusy_target(scsi_id, channel, base);
2255 outb(SCB_NEEDDMA, SCBARRAY(base));
2256
2257 outb(CLRSELTIMEO, CLRSINT1(base));
2258 RESTART_SEQUENCER(p);
2259 break;
2260
2261 caseMSG_SDTR:
2262 /*2263 * Help the sequencer to translate the negotiated2264 * transfer rate. Transfer is 1/4 the period2265 * in ns as is returned by the sync negotiation2266 * message. So, we must multiply by four.2267 */2268 transfer = (inb(HA_ARG_1(base)) << 2);
2269 offset = inb(ACCUM(base));
2270 scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2271 /*2272 * The maximum offset for a wide device is 0x08; for a2273 * 8-bit bus device the maximum offset is 0x0F.2274 */2275 if (scratch & WIDEXFER)
2276 {2277 max_offset = 0x08;
2278 }2279 else2280 {2281 max_offset = 0x0F;
2282 }2283 aic7xxx_scsirate(&rate, transfer, MIN(offset, max_offset), scsi_id, channel);
2284 /*2285 * Preserve the wide transfer flag.2286 */2287 scratch = rate | (scratch & WIDEXFER);
2288 outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2289 outb(scratch, SCSIRATE(base));
2290 if ((scratch & 0x0F) == 0)
2291 {/*2292 * The requested rate was so low that asynchronous transfers2293 * are faster (not to mention the controller won't support2294 * them), so we issue a reject to ensure we go to asynchronous2295 * transfers.2296 */2297 outb(SEND_REJ, HA_RETURN_1(base));
2298 }2299 else2300 {2301 /*2302 * See if we initiated Sync Negotiation2303 */2304 if (p->sdtr_pending & target_mask)
2305 {2306 /*2307 * Don't send an SDTR back to the target.2308 */2309 outb(0, HA_RETURN_1(base));
2310 }2311 else2312 {2313 /*2314 * Send our own SDTR in reply.2315 */2316 printk("aic7xxx_isr: Sending SDTR!!\n");
2317 outb(SEND_SDTR, HA_RETURN_1(base));
2318 }2319 }2320 /*2321 * Clear the flags.2322 */2323 p->needsdtr &= ~target_mask;
2324 p->sdtr_pending &= ~target_mask;
2325 #if 0
2326 scb_index = inb(SCBPTR(base));
2327 scb = &(p->scb_array[scb_index]);
2328 debug_scb(scb);
2329 #endif2330
2331 break;
2332
2333 caseMSG_WDTR:
2334 {2335 bus_width = inb(ACCUM(base));
2336 printk("aic7xxx_isr: Received MSG_WDTR, scsi_id %d, channel %c "
2337 "needwdtr = 0x%x\n", scsi_id, channel, p->needwdtr);
2338 scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2339
2340 if (p->wdtr_pending & target_mask)
2341 {2342 /*2343 * Don't send an WDTR back to the target, since we asked first.2344 */2345 outb(0, HA_RETURN_1(base));
2346 switch (bus_width)
2347 {2348 caseBUS_8_BIT:
2349 scratch &= 0x7F;
2350 break;
2351
2352 caseBUS_16_BIT:
2353 printk("aic7xxx_isr: target %d, channel %c, using 16 bit transfers\n",
2354 scsi_id, channel);
2355 scratch |= 0x80;
2356 break;
2357 }2358 }2359 else2360 {2361 /*2362 * Send our own WDTR in reply.2363 */2364 printk("aic7xxx_isr: Will send WDTR!!\n");
2365 switch (bus_width)
2366 {2367 caseBUS_8_BIT:
2368 scratch &= 0x7F;
2369 break;
2370
2371 caseBUS_32_BIT:
2372 /*2373 * Negotiate 16 bits.2374 */2375 bus_width = BUS_16_BIT;
2376 /* Yes, we mean to fall thru here. */2377
2378 caseBUS_16_BIT:
2379 printk("aic7xxx_isr: target %d, channel %c, using 16 bit transfers\n",
2380 scsi_id, channel);
2381 scratch |= 0x80;
2382 break;
2383 }2384 outb(bus_width | SEND_WDTR, HA_RETURN_1(base));
2385 }2386 p->needwdtr &= ~target_mask;
2387 p->wdtr_pending &= ~target_mask;
2388 outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2389 outb(scratch, SCSIRATE(base));
2390 break;
2391 }2392
2393 caseMSG_REJECT:
2394 {2395 /*2396 * What we care about here is if we had an2397 * outstanding SDTR or WDTR message for this2398 * target. If we did, this is a signal that2399 * the target is refusing negotiation.2400 */2401
2402 scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2403
2404 if (p->wdtr_pending & target_mask)
2405 {2406 /*2407 * note 8bit xfers and clear flag2408 */2409 scratch &= 0x7F;
2410 p->needwdtr &= ~target_mask;
2411 p->wdtr_pending &= ~target_mask;
2412 outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2413 printk("aic7xxx: target %d, channel %c, refusing WIDE negotiation. "
2414 "Using 8 bit transfers\n", scsi_id, channel);
2415 }2416 else2417 {2418 if (p->sdtr_pending & target_mask)
2419 {2420 /*2421 * note asynch xfers and clear flag2422 */2423 scratch &= 0xF0;
2424 p->needsdtr &= ~target_mask;
2425 p->sdtr_pending &= ~target_mask;
2426 outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2427 printk("aic7xxx: target %d, channel %c, refusing syncronous negotiation. "
2428 "Using asyncronous transfers\n", scsi_id, channel);
2429 }2430 /*2431 * Otherwise, we ignore it.2432 */2433 }2434 outb(scratch, HA_TARG_SCRATCH(base) + scratch_offset);
2435 outb(scratch, SCSIRATE(base));
2436 break;
2437 }2438
2439 caseBAD_STATUS:
2440 scb_index = inb(SCBPTR(base));
2441 scb = &(p->scb_array[scb_index]);
2442 outb(0, HA_RETURN_1(base)); /* CHECK_CONDITION may change this */2443 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2444 {2445 printk("aic7xxx_isr: referenced scb not valid "
2446 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2447 intstat, scb_index, scb->state, (unsignedint) scb->cmd);
2448 }2449 else2450 {2451 cmd = scb->cmd;
2452 aic7xxx_getscb(base, scb);
2453 aic7xxx_status(cmd) = scb->target_status;
2454
2455 cmd->result |= scb->target_status;
2456
2457 switch (status_byte(scb->target_status))
2458 {2459 caseGOOD:
2460 printk("aic7xxx_isr: Interrupted for status of 0???\n");
2461 break;
2462
2463 caseCHECK_CONDITION:
2464 if ((aic7xxx_error(cmd) == 0) && !(cmd->flags & WAS_SENSE))
2465 {2466 unsignedchartcl;
2467 unsignedcharcontrol;
2468 void *req_buf;
2469
2470 tcl = scb->target_channel_lun;
2471 /*2472 * Send a sense command to the requesting target.2473 */2474 cmd->flags |= WAS_SENSE;
2475 memcpy((void *) scb->sense_cmd, (void *) generic_sense,
2476 sizeof(generic_sense));
2477
2478 scb->sense_cmd[1] = (cmd->lun << 5);
2479 scb->sense_cmd[4] = sizeof(cmd->sense_buffer);
2480
2481 scb->sense_sg.address = (char *) &cmd->sense_buffer;
2482 scb->sense_sg.length = sizeof(cmd->sense_buffer);
2483 req_buf = &scb->sense_sg;
2484 cmd->cmd_len = COMMAND_SIZE(cmd->cmnd[0]);
2485 control = scb->control;
2486 memset(scb, 0, SCB_DOWNLOAD_SIZE);
2487 scb->control = control & SCB_DISCENB;
2488 scb->target_channel_lun = tcl;
2489 addr = scb->sense_cmd;
2490 scb->SCSI_cmd_length = COMMAND_SIZE(scb->sense_cmd[0]);
2491 memcpy(scb->SCSI_cmd_pointer, &addr,
2492 sizeof(scb->SCSI_cmd_pointer));
2493 scb->SG_segment_count = 1;
2494 memcpy(scb->SG_list_pointer, &req_buf,
2495 sizeof(scb->SG_list_pointer));
2496 scb->data_count[0] = scb->sense_sg.length & 0xFF;
2497 scb->data_count[1] = (scb->sense_sg.length >> 8) & 0xFF;
2498 scb->data_count[2] = (scb->sense_sg.length >> 16) & 0xFF;
2499 memcpy(scb->data_pointer, &(scb->sense_sg.address), 4);
2500
2501 outb(SCBAUTO, SCBCNT(base));
2502 asmvolatile("cld\n\t"
2503 "rep\n\t"
2504 "outsb"
2505 : /* no output */2506 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
2507 :"si", "cx", "dx");
2508 outb(0, SCBCNT(base));
2509 outb(SCB_LIST_NULL, (SCBARRAY(base) + 30));
2510 /*2511 * Ensure that the target is "BUSY" so we don't get overlapping2512 * commands if we happen to be doing tagged I/O.2513 */2514 active = inb(HA_ACTIVE0(base)) | (inb(HA_ACTIVE1(base)) << 8);
2515 active |= target_mask;
2516 outb(active & 0xFF, HA_ACTIVE0(base));
2517 outb((active >> 8) & 0xFF, HA_ACTIVE1(base));
2518
2519 aic7xxx_add_waiting_scb(base, scb, LIST_HEAD);
2520 outb(SEND_SENSE, HA_RETURN_1(base));
2521 }/* first time sense, no errors */2522 else2523 {2524 /*2525 * Indicate that we asked for sense, have the sequencer do2526 * a normal command complete, and have the scsi driver handle2527 * this condition.2528 */2529 cmd->flags |= ASKED_FOR_SENSE;
2530 }2531 break;
2532
2533 caseBUSY:
2534 printk("aic7xxx_isr: Target busy\n");
2535 if (!aic7xxx_error(cmd))
2536 {2537 aic7xxx_error(cmd) = DID_BUS_BUSY;
2538 }2539 break;
2540
2541 caseQUEUE_FULL:
2542 printk("aic7xxx_isr: Queue full\n");
2543 if (!aic7xxx_error(cmd))
2544 {2545 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2546 }2547 break;
2548
2549 default:
2550 printk("aic7xxx_isr: Unexpected target status 0x%x\n",
2551 scb->target_status);
2552 if (!aic7xxx_error(cmd))
2553 {2554 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2555 }2556 break;
2557 }/* end switch */2558 }/* end else of */2559 break;
2560
2561 caseRESIDUAL:
2562 scb_index = inb(SCBPTR(base));
2563 scb = &(p->scb_array[scb_index]);
2564 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2565 {2566 printk("aic7xxx_isr: referenced scb not valid "
2567 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2568 intstat, scb_index, scb->state, (unsignedint) scb->cmd);
2569 }2570 else2571 {2572 cmd = scb->cmd;
2573 /*2574 * Don't destroy valid residual information with2575 * residual coming from a check sense operation.2576 */2577 if (!(cmd->flags & WAS_SENSE))
2578 {2579 /*2580 * We had an underflow. At this time, there's only2581 * one other driver that bothers to check for this,2582 * and cmd->underflow seems to be set rather half-2583 * heartedly in the higher-level SCSI code.2584 */2585 actual = aic7xxx_length(cmd, scb->residual_SG_segment_count);
2586
2587 actual -= ((inb(SCBARRAY(base + 17)) << 16) |
2588 (inb(SCBARRAY(base + 16)) << 8) |
2589 inb(SCBARRAY(base + 15)));
2590
2591 if (actual < cmd->underflow)
2592 {2593 printk("aic7xxx: target %d underflow - "
2594 "wanted (at least) %u, got %u, count=%d\n",
2595 cmd->target, cmd->underflow, actual, inb(SCBARRAY(base + 18)));
2596 aic7xxx_error(cmd) = DID_RETRY_COMMAND;
2597 aic7xxx_status(cmd) = scb->target_status;
2598 }2599 }2600 }2601 break;
2602
2603 caseABORT_TAG:
2604 scb_index = inb(SCBPTR(base));
2605 scb = &(p->scb_array[scb_index]);
2606 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2607 {2608 printk("aic7xxx_isr: referenced scb not valid "
2609 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2610 intstat, scb_index, scb->state, (unsignedint) scb->cmd);
2611 }2612 else2613 {2614 cmd = scb->cmd;
2615 /*2616 * We didn't recieve a valid tag back from the target2617 * on a reconnect.2618 */2619 printk("aic7xxx_isr: invalid tag recieved on channel %c "
2620 "target %d, lun %d -- sending ABORT_TAG\n",
2621 channel, scsi_id, cmd->lun & 0x07);
2622
2623 cmd->result = (DID_RETRY_COMMAND << 16);
2624 aic7xxx_done(p, scb);
2625 }2626 break;
2627
2628 caseAWAITING_MSG:
2629 scb_index = inb(SCBPTR(base));
2630 scb = &(p->scb_array[scb_index]);
2631 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2632 {2633 printk("aic7xxx_isr: referenced scb not valid "
2634 "during seqint 0x%x scb(%d) state(%x), cmd(%x)\n",
2635 intstat, scb_index, scb->state, (unsignedint) scb->cmd);
2636 }2637 else2638 {2639 /*2640 * This SCB had a zero length command, informing the sequencer2641 * that we wanted to send a special message to this target.2642 * We only do this for BUS_DEVICE_RESET messages currently.2643 */2644 if (scb->state & SCB_DEVICE_RESET)
2645 {2646 outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
2647 outb(1, HA_MSG_LEN(base));
2648 }2649 else2650 {2651 panic("aic7xxx_isr: AWAITING_SCB for an SCB that does "
2652 "not have a waiting message");
2653 }2654 }2655 break;
2656
2657 caseIMMEDDONE:
2658 scb_index = inb(SCBPTR(base));
2659 scb = &(p->scb_array[scb_index]);
2660 if (scb->state & SCB_DEVICE_RESET)
2661 {2662 intfound;
2663
2664 /*2665 * Go back to async/narrow transfers and renogiate.2666 */2667 aic7xxx_unbusy_target(scsi_id, channel, base);
2668 p->needsdtr |= (p->needsdtr_copy & target_mask);
2669 p->needwdtr |= (p->needwdtr_copy & target_mask);
2670 p->sdtr_pending &= ~target_mask;
2671 p->wdtr_pending &= ~target_mask;
2672 scratch = inb(HA_TARG_SCRATCH(base) + scratch_offset);
2673 scratch &= SXFR;
2674 outb(scratch, HA_TARG_SCRATCH(base));
2675 found = aic7xxx_reset_device(p, (int) scsi_id, channel, SCB_LIST_NULL);
2676 }2677 else2678 {2679 panic("aic7xxx_isr: Immediate complete for unknown operation.\n");
2680 }2681 break;
2682
2683 default: /* unknown */2684 debug("aic7xxx_isr: seqint, intstat = 0x%x, scsisigi = 0x%x\n",
2685 intstat, inb(SCSISIGI(base)));
2686 break;
2687 }2688 outb(CLRSEQINT, CLRINT(base));
2689 UNPAUSE_SEQUENCER(p);
2690 }2691
2692 if (intstat & SCSIINT)
2693 {2694 intstatus = inb(SSTAT1(base));
2695
2696 scb_index = inb(SCBPTR(base));
2697 scb = &(p->scb_array[scb_index]);
2698 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2699 {2700 printk("aic7xxx_isr: no command for scb (scsiint)\n");
2701 /*2702 * Turn off the interrupt and set status2703 * to zero, so that it falls through the2704 * reset of the SCSIINT code.2705 */2706 outb(status, CLRSINT1(base));
2707 UNPAUSE_SEQUENCER(p);
2708 outb(CLRSCSIINT, CLRINT(base));
2709 status = 0;
2710 scb = NULL;
2711 }2712 else2713 {2714 cmd = scb->cmd;
2715
2716 /*2717 * Only the SCSI Status 1 register has information2718 * about exceptional conditions that we'd have a2719 * SCSIINT about; anything in SSTAT0 will be handled2720 * by the sequencer. Note that there can be multiple2721 * bits set.2722 */2723 if (status & SELTO)
2724 {2725 unsignedchartarget_mask = (1 << (cmd->target & 0x07));
2726 unsignedcharwaiting;
2727
2728 /*2729 * Hardware selection timer has expired. Turn2730 * off SCSI selection sequence.2731 */2732 outb(ENRSELI, SCSISEQ(base));
2733 cmd->result = (DID_TIME_OUT << 16);
2734 /*2735 * Clear an pending messages for the timed out2736 * target and mark the target as free.2737 */2738 ha_flags = inb(HA_FLAGS(base));
2739 outb(ha_flags & ~ACTIVE_MSG, HA_FLAGS(base));
2740
2741 if (scb->target_channel_lun & 0x88)
2742 {2743 active = inb(HA_ACTIVE1(base));
2744 active = active & ~(target_mask);
2745 outb(active, HA_ACTIVE1(base));
2746 }2747 else2748 {2749 active = inb(HA_ACTIVE0(base));
2750 active &= ~(target_mask);
2751 outb(active, HA_ACTIVE0(base));
2752 }2753
2754 outb(SCB_NEEDDMA, SCBARRAY(base));
2755
2756 /*2757 * Shut off the offending interrupt sources, reset2758 * the sequencer address to zero and unpause it,2759 * then call the high-level SCSI completion routine.2760 *2761 * WARNING! This is a magic sequence! After many2762 * hours of guesswork, turning off the SCSI interrupts2763 * in CLRSINT? does NOT clear the SCSIINT bit in2764 * INTSTAT. By writing to the (undocumented, unused2765 * according to the AIC-7770 manual) third bit of2766 * CLRINT, you can clear INTSTAT. But, if you do it2767 * while the sequencer is paused, you get a BRKADRINT2768 * with an Illegal Host Address status, so the2769 * sequencer has to be restarted first.2770 */2771 outb(CLRSELTIMEO, CLRSINT1(base));
2772
2773 outb(CLRSCSIINT, CLRINT(base));
2774
2775 /*2776 * Shift the waiting for selection queue forward2777 */2778 waiting = inb(WAITING_SCBH(base));
2779 outb(waiting, SCBPTR(base));
2780 waiting = inb(SCBARRAY(base) + 30);
2781 outb(waiting, WAITING_SCBH(base));
2782
2783 RESTART_SEQUENCER(p);
2784 aic7xxx_done(p, scb);
2785 #if 0
2786 printk("aic7xxx_isr: SELTO scb(%d) state(%x), cmd(%x)\n",
2787 scb->position, scb->state, (unsignedint) scb->cmd);
2788 #endif2789 }2790 else2791 {2792 if (status & SCSIPERR)
2793 {2794 /*2795 * A parity error has occurred during a data2796 * transfer phase. Flag it and continue.2797 */2798 printk("aic7xxx: parity error on target %d, "
2799 "channel %d, lun %d\n",
2800 cmd->target,
2801 cmd->channel & 0x01,
2802 cmd->lun & 0x07);
2803 aic7xxx_error(cmd) = DID_PARITY;
2804
2805 /*2806 * Clear interrupt and resume as above.2807 */2808 outb(CLRSCSIPERR, CLRSINT1(base));
2809 UNPAUSE_SEQUENCER(p);
2810
2811 outb(CLRSCSIINT, CLRINT(base));
2812 scb = NULL;
2813 }2814 else2815 {2816 if (!(status & BUSFREE))
2817 {2818 /*2819 * We don't know what's going on. Turn off the2820 * interrupt source and try to continue.2821 */2822 printk("aic7xxx_isr: sstat1 = 0x%x\n", status);
2823 outb(status, CLRSINT1(base));
2824 UNPAUSE_SEQUENCER(p);
2825 outb(CLRSCSIINT, CLRINT(base));
2826 scb = NULL;
2827 }2828 }2829 }2830 }/* else */2831 }2832
2833 if (intstat & CMDCMPLT)
2834 {2835 intcomplete;
2836
2837 /*2838 * The sequencer will continue running when it2839 * issues this interrupt. There may be >1 commands2840 * finished, so loop until we've processed them all.2841 */2842 do{2843 complete = inb(QOUTFIFO(base));
2844
2845 scb = &(p->scb_array[complete]);
2846 if ((scb->state != SCB_ACTIVE) || (scb->cmd == NULL))
2847 {2848 printk("aic7xxx warning: "
2849 "no command for scb %d (cmdcmplt)\n"
2850 "QOUTCNT = %d, SCB state = 0x%x, CMD = 0x%x, pos = %d\n",
2851 complete, inb(QOUTFIFO(base)),
2852 scb->state, (unsignedint) scb->cmd, scb->position);
2853 outb(CLRCMDINT, CLRINT(base));
2854 continue;
2855 }2856 cmd = scb->cmd;
2857
2858 cmd->result = (aic7xxx_error(cmd) << 16) | aic7xxx_status(cmd);
2859 if ((cmd->flags & WAS_SENSE) && !(cmd->flags & ASKED_FOR_SENSE))
2860 {2861 /*2862 * Got sense information.2863 */2864 cmd->flags &= ASKED_FOR_SENSE;
2865 }2866 #if 0
2867 printk("aic7xxx_intr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2868 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2869 #endif2870
2871 /*2872 * Clear interrupt status before checking2873 * the output queue again. This eliminates2874 * a race condition whereby a command could2875 * complete between the queue poll and the2876 * interrupt clearing, so notification of the2877 * command being complete never made it back2878 * up to the kernel.2879 */2880 outb(CLRCMDINT, CLRINT(base));
2881 aic7xxx_done(p, scb);
2882 #if 0
2883 if (scb != &p->scb_array[scb->position])
2884 {2885 printk("aic7xxx_isr: (complete) address mismatch, pos %d\n", scb->position);
2886 }2887 printk("aic7xxx_isr: (complete) state = %d, cmd = 0x%x, free = 0x%x\n",
2888 scb->state, (unsignedint) scb->cmd, (unsignedint) p->free_scb);
2889 #endif2890
2891 #ifdefAIC7XXX_PROC_STATS2892 /*2893 * XXX: we should actually know how much actually transferred2894 * XXX: for each command, but apparently that's too difficult.2895 */2896 actual = aic7xxx_length(cmd, 0);
2897 if (((cmd->flags & WAS_SENSE) == 0) && (actual > 0))
2898 {2899 structaic7xxx_xferstats *sp;
2900 long *ptr;
2901 intx;
2902
2903 sp = &p->stats[cmd->channel & 0x01][cmd->target & 0x0F][cmd->lun & 0x07];
2904 sp->xfers++;
2905
2906 if (cmd->request.cmd == WRITE)
2907 {2908 sp->w_total++;
2909 sp->w_total512 += (actual >> 9);
2910 ptr = sp->w_bins;
2911 }2912 else2913 {2914 sp->r_total++;
2915 sp->r_total512 += (actual >> 9);
2916 ptr = sp->r_bins;
2917 }2918 for (x = 9; x <= 17; x++)
2919 {2920 if (actual < (1 << x))
2921 {2922 ptr[x - 9]++;
2923 break;
2924 }2925 }2926 if (x > 17)
2927 {2928 ptr[x - 9]++;
2929 }2930 }2931 #endif/* AIC7XXX_PROC_STATS */2932
2933 }while (inb(QOUTCNT(base)));
2934 }2935 }2936
2937 /*+F*************************************************************************2938 * Function:2939 * aic7xxx_probe2940 *2941 * Description:2942 * Probing for EISA boards: it looks like the first two bytes2943 * are a manufacturer code - three characters, five bits each:2944 *2945 * BYTE 0 BYTE 1 BYTE 2 BYTE 32946 * ?1111122 22233333 PPPPPPPP RRRRRRRR2947 *2948 * The characters are baselined off ASCII '@', so add that value2949 * to each to get the real ASCII code for it. The next two bytes2950 * appear to be a product and revision number, probably vendor-2951 * specific. This is what is being searched for at each port,2952 * and what should probably correspond to the ID= field in the2953 * ECU's .cfg file for the card - if your card is not detected,2954 * make sure your signature is listed in the array.2955 *2956 * The fourth byte's lowest bit seems to be an enabled/disabled2957 * flag (rest of the bits are reserved?).2958 *-F*************************************************************************/2959 staticaha_type2960 aic7xxx_probe(intslot, intbase)
/* */2961 {2962 inti;
2963 unsignedcharbuf[4];
2964
2965 staticstruct{2966 intn;
2967 unsignedcharsignature[sizeof(buf)];
2968 aha_typetype;
2969 }AIC7xxx[] = {2970 { 4, { 0x04, 0x90, 0x77, 0x71 }, AIC_274x}, /* host adapter 274x */2971 { 4, { 0x04, 0x90, 0x77, 0x70 }, AIC_274x}, /* motherboard 274x */2972 { 4, { 0x04, 0x90, 0x77, 0x56 }, AIC_284x}, /* 284x, BIOS enabled */2973 { 4, { 0x04, 0x90, 0x77, 0x57 }, AIC_284x}/* 284x, BIOS disabled */2974 };
2975
2976 /*2977 * The VL-bus cards need to be primed by2978 * writing before a signature check.2979 */2980 for (i = 0; i < sizeof(buf); i++)
2981 {2982 outb(0x80 + i, base);
2983 buf[i] = inb(base + i);
2984 }2985
2986 for (i = 0; i < NUMBER(AIC7xxx); i++)
2987 {2988 /*2989 * Signature match on enabled card?2990 */2991 if (!memcmp(buf, AIC7xxx[i].signature, AIC7xxx[i].n))
2992 {2993 if (inb(base + 4) & 1)
2994 {2995 return (AIC7xxx[i].type);
2996 }2997
2998 printk("aic7xxx disabled at slot %d, ignored\n", slot);
2999 }3000 }3001
3002 return (AIC_NONE);
3003 }3004
3005 /*+F*************************************************************************3006 * Function:3007 * read_seeprom3008 *3009 * Description:3010 * Reads the serial EEPROM and returns 1 if successful and 0 if3011 * not successful.3012 *3013 * The instruction set of the 93C46 chip is as follows:3014 *3015 * Start OP3016 * Function Bit Code Address Data Description3017 * -------------------------------------------------------------------3018 * READ 1 10 A5 - A0 Reads data stored in memory,3019 * starting at specified address3020 * EWEN 1 00 11XXXX Write enable must preceed3021 * all programming modes3022 * ERASE 1 11 A5 - A0 Erase register A5A4A3A2A1A03023 * WRITE 1 01 A5 - A0 D15 - D0 Writes register3024 * ERAL 1 00 10XXXX Erase all registers3025 * WRAL 1 00 01XXXX D15 - D0 Writes to all registers3026 * EWDS 1 00 00XXXX Disables all programming3027 * instructions3028 * *Note: A value of X for address is a don't care condition.3029 *3030 * The 93C46 has a four wire interface: clock, chip select, data in, and3031 * data out. In order to perform one of the above functions, you need3032 * to enable the chip select for a clock period (typically a minimum of3033 * 1 usec, with the clock high and low a minimum of 750 and 250 nsec3034 * respectively. While the chip select remains high, you can clock in3035 * the instructions (above) starting with the start bit, followed by the3036 * OP code, Address, and Data (if needed). For the READ instruction, the3037 * requested 16-bit register contents is read from the data out line but3038 * is preceded by an initial zero (leading 0, followed by 16-bits, MSB3039 * first). The clock cycling from low to high initiates the next data3040 * bit to be sent from the chip.3041 *3042 * The 7870 interface to the 93C46 serial EEPROM is through the SEECTL3043 * register. After successful arbitration for the memory port, the3044 * SEECS bit of the SEECTL register is connected to the chip select.3045 * The SEECK, SEEDO, and SEEDI are connected to the clock, data out,3046 * and data in lines respectively. The SEERDY bit of SEECTL is useful3047 * in that it gives us an 800 nsec timer. After a write to the SEECTL3048 * register, the SEERDY goes high 800 nsec later. The one exception3049 * to this is when we first request access to the memory port. The3050 * SEERDY goes high to signify that access has been granted and, for3051 * this case, has no implied timing.3052 *3053 *-F*************************************************************************/3054 staticint3055 read_seeprom(intbase, structseeprom_config *sc)
/* */3056 {3057 inti = 0, k = 0;
3058 unsignedlongtimeout;
3059 unsignedchartemp;
3060 unsignedshortchecksum = 0;
3061 unsignedshort *seeprom = (unsignedshort *) sc;
3062 structseeprom_cmd{3063 unsignedcharlen;
3064 unsignedcharbits[3];
3065 };
3066 structseeprom_cmdseeprom_read = {3, {1, 1, 0}};
3067
3068 #defineCLOCK_PULSE(p) \
3069 while ((inb(SEECTL(base)) & SEERDY) == 0) \
3070 { \
3071 ; /* Do nothing */ \
3072 }3073
3074 /*3075 * Request access of the memory port. When access is3076 * granted, SEERDY will go high. We use a 1 second3077 * timeout which should be near 1 second more than3078 * is needed. Reason: after the 7870 chip reset, there3079 * should be no contention.3080 */3081 outb(SEEMS, SEECTL(base));
3082 timeout = jiffies + 100; /* 1 second timeout */3083 while ((jiffies < timeout) && ((inb(SEECTL(base)) & SEERDY) == 0))
3084 {3085 ; /* Do nothing! Wait for access to be granted. */3086 }3087 if ((inb(SEECTL(base)) & SEERDY) == 0)
3088 {3089 outb(0, SEECTL(base));
3090 return (0);
3091 }3092
3093 /*3094 * Read the first 32 registers of the seeprom. For the 7870,3095 * the 93C46 SEEPROM is a 1024-bit device with 64 16-bit registers3096 * but only the first 32 are used by Adaptec BIOS. The loop3097 * will range from 0 to 31.3098 */3099 for (k = 0; k < (sizeof(*sc) / 2); k++)
3100 {3101 /*3102 * Send chip select for one clock cycle.3103 */3104 outb(SEEMS | SEECK | SEECS, SEECTL(base));
3105 CLOCK_PULSE(base);
3106
3107 /*3108 * Now we're ready to send the read command followed by the3109 * address of the 16-bit register we want to read.3110 */3111 for (i = 0; i < seeprom_read.len; i++)
3112 {3113 temp = SEEMS | SEECS | (seeprom_read.bits[i] << 1);
3114 outb(temp, SEECTL(base));
3115 CLOCK_PULSE(base);
3116 temp = temp ^ SEECK;
3117 outb(temp, SEECTL(base));
3118 CLOCK_PULSE(base);
3119 }3120 /*3121 * Send the 6 bit address (MSB first, LSB last).3122 */3123 for (i = 5; i >= 0; i--)
3124 {3125 temp = k;
3126 temp = (temp >> i) & 1; /* Mask out all but lower bit. */3127 temp = SEEMS | SEECS | (temp << 1);
3128 outb(temp, SEECTL(base));
3129 CLOCK_PULSE(base);
3130 temp = temp ^ SEECK;
3131 outb(temp, SEECTL(base));
3132 CLOCK_PULSE(base);
3133 }3134
3135 /*3136 * Now read the 16 bit register. An initial 0 precedes the3137 * register contents which begins with bit 15 (MSB) and ends3138 * with bit 0 (LSB). The initial 0 will be shifted off the3139 * top of our word as we let the loop run from 0 to 16.3140 */3141 for (i = 0; i <= 16; i++)
3142 {3143 temp = SEEMS | SEECS;
3144 outb(temp, SEECTL(base));
3145 CLOCK_PULSE(base);
3146 temp = temp ^ SEECK;
3147 seeprom[k] = (seeprom[k] << 1) | (inb(SEECTL(base)) & SEEDI);
3148 outb(temp, SEECTL(base));
3149 CLOCK_PULSE(base);
3150 }3151
3152 /*3153 * The serial EEPROM has a checksum in the last word. Keep a3154 * running checksum for all words read except for the last3155 * word. We'll verify the checksum after all words have been3156 * read.3157 */3158 if (k < (sizeof(*sc) / 2) - 1)
3159 {3160 checksum = checksum + seeprom[k];
3161 }3162
3163 /*3164 * Reset the chip select for the next command cycle.3165 */3166 outb(SEEMS, SEECTL(base));
3167 CLOCK_PULSE(base);
3168 outb(SEEMS | SEECK, SEECTL(base));
3169 CLOCK_PULSE(base);
3170 outb(SEEMS, SEECTL(base));
3171 CLOCK_PULSE(base);
3172 }3173
3174 /*3175 * Release access to the memory port and the serial EEPROM.3176 */3177 outb(0, SEECTL(base));
3178
3179 #if 0
3180 printk("Computed checksum 0x%x, checksum read 0x%x\n", checksum, sc->checksum);
3181 printk("Serial EEPROM:");
3182 for (k = 0; k < (sizeof(*sc) / 2); k++)
3183 {3184 if (((k % 8) == 0) && (k != 0))
3185 {3186 printk("\n ");
3187 }3188 printk(" 0x%x", seeprom[k]);
3189 }3190 printk("\n");
3191 #endif3192
3193 if (checksum != sc->checksum)
3194 {3195 printk("aic7xxx: SEEPROM checksum error, ignoring SEEPROM settings.\n");
3196 return (0);
3197 }3198
3199 return (1);
3200 }3201
3202 /*+F*************************************************************************3203 * Function:3204 * detect_maxscb3205 *3206 * Description:3207 * Return the maximum number of SCB's allowed for a given controller.3208 *-F*************************************************************************/3209 staticint3210 detect_maxscb(aha_typetype, intbase)
/* */3211 {3212 unsignedcharsblkctl_reg;
3213 intmaxscb = 0;
3214
3215 switch (type)
3216 {3217 caseAIC_274x:
3218 caseAIC_284x:
3219 /*3220 * Check for Rev C or E boards. Rev E boards can supposedly have3221 * more than 4 SCBs, while the Rev C boards are limited to 4 SCBs.3222 * Until we know how to access more than 4 SCBs for the Rev E chips,3223 * we limit them, along with the Rev C chips, to 4 SCBs.3224 *3225 * The Rev E boards have a read/write autoflush bit in the3226 * SBLKCTL registor, while in the Rev C boards it is read only.3227 */3228 sblkctl_reg = inb(SBLKCTL(base)) ^ AUTOFLUSHDIS;
3229 outb(sblkctl_reg, SBLKCTL(base));
3230 if (inb(SBLKCTL(base)) == sblkctl_reg)
3231 {3232 /*3233 * We detected a Rev E board.3234 */3235 printk("aic7770: Rev E and subsequent; using 4 SCB's\n");
3236 outb(sblkctl_reg ^ AUTOFLUSHDIS, SBLKCTL(base));
3237 maxscb = 4;
3238 }3239 else3240 {3241 printk("aic7770: Rev C and previous; using 4 SCB's\n");
3242 maxscb = 4;
3243 }3244 break;
3245
3246 caseAIC_7850:
3247 maxscb = 3;
3248 break;
3249
3250 caseAIC_7870:
3251 maxscb = 16;
3252 break;
3253
3254 caseAIC_7872:
3255 /*3256 * Really has 255, but we'll wait to verify that we access3257 * them the same way and do not have to set the card to3258 * use the memory port to access external SCB RAM.3259 */3260 maxscb = 16;
3261 break;
3262
3263 caseAIC_NONE:
3264 /*3265 * This should never happen... But just in case.3266 */3267 break;
3268 }3269
3270 return (maxscb);
3271 }3272
3273 /*+F*************************************************************************3274 * Function:3275 * aic7xxx_register3276 *3277 * Description:3278 * Register a Adaptec aic7xxx chip SCSI controller with the kernel.3279 *-F*************************************************************************/3280 staticint3281 aic7xxx_register(Scsi_Host_Template *template, aha_typetype,
/* */3282 intbase, unsignedcharirq)
3283 {3284 staticconstchar * board_name[] = {"", "274x", "284x", "7870", "7850", "7872"};
3285 inti;
3286 unsignedcharsblkctl;
3287 intmax_targets;
3288 intfound = 1;
3289 intbios_disabled = 0;
3290 unsignedchartarget_settings;
3291 unsignedcharscsi_conf, host_conf;
3292 inthave_seeprom = 0;
3293 structScsi_Host *host;
3294 structaic7xxx_host *p;
3295 structaic7xxx_host_configconfig;
3296 structseeprom_configsc;
3297
3298 config.type = type;
3299 config.base = base;
3300 config.irq = irq;
3301 config.parity = AIC_UNKNOWN;
3302 config.low_term = AIC_UNKNOWN;
3303 config.high_term = AIC_UNKNOWN;
3304 config.busrtime = 0;
3305
3306 /*3307 * Lock out other contenders for our i/o space.3308 */3309 request_region(MINREG(base), MAXREG(base) - MINREG(base), "aic7xxx");
3310
3311 switch (type)
3312 {3313 caseAIC_274x:
3314 #if 0
3315 printk("aha274x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
3316 #endif3317 /*3318 * For some 274x boards, we must clear the CHIPRST bit3319 * and pause the sequencer. For some reason, this makes3320 * the driver work. For 284x boards, we give it a3321 * CHIPRST just like the 294x boards.3322 *3323 * Use the BIOS settings to determine the interrupt3324 * trigger type (level or edge) and use this value3325 * for pausing and unpausing the sequencer.3326 */3327 config.unpause = (inb(HCNTRL(config.base)) & IRQMS) | INTEN;
3328 config.pause = config.unpause | PAUSE;
3329 config.extended = aic7xxx_extended;
3330
3331 /*3332 * I don't think we need to kick the reset again, the initial probe3333 * does a reset, it seems that this is kicking a dead horse here.3334 * So... I will try to just verify that the chip has come out of the3335 * reset state and continue the same as the 284x.3336 * In the Calgary version of the driver:3337 * 1) Chip Reset3338 * 2) Set unpause to IRQMS | INTEN3339 * 3) If an interrupt occured without any commands queued, the3340 * unpause was set to just INTEN3341 * I changed the initial reset code to just mask in the CHIPRST bit3342 * and try to leave the other settings alone.3343 *3344 * I don't think we need the warning about chip reset not being clear.3345 * On both my test machines (2842 & 2940), they work just fine with a3346 * HCNTRL() of 0x5 (PAUSE | CHIPRST). Notice though, the 274x also3347 * adds the INTEN flag, where neither the 284x or 294x do.3348 */3349 outb(config.pause | CHIPRST, HCNTRL(config.base));
3350 aic7xxx_delay(1);
3351 if (inb(HCNTRL(config.base)) & CHIPRST)
3352 {3353 printk("aic7xxx_register: Chip reset not cleared; clearing manually.\n");
3354 }3355 outb(config.pause, HCNTRL(config.base));
3356
3357 /*3358 * Just to be on the safe side with the 274x, we will re-read the irq3359 * since there was some issue about reseting the board.3360 */3361 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
3362 if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3363 {3364 bios_disabled = 1;
3365 }3366 host_conf = inb(HA_HOSTCONF(config.base));
3367 config.busrtime = host_conf & 0x3C;
3368 /* XXX Is this valid for motherboard based controllers? */3369 /* Setup the FIFO threshold and the bus off time */3370 outb(host_conf & DFTHRSH, BUSSPD(config.base));
3371 outb((host_conf << 2) & BOFF, BUSTIME(config.base));
3372
3373 /*3374 * A reminder until this can be detected automatically.3375 */3376 printk("aha274x: extended translation %sabled\n",
3377 config.extended ? "en" : "dis");
3378 break;
3379
3380 caseAIC_284x:
3381 #if 0
3382 printk("aha284x: aic7770 hcntrl=0x%x\n", inb(HCNTRL(config.base)));
3383 #endif3384 outb(CHIPRST, HCNTRL(config.base));
3385 config.unpause = UNPAUSE_284X;
3386 config.pause = REQ_PAUSE; /* DWG would like to be like the rest */3387 config.extended = aic7xxx_extended;
3388 config.irq = inb(HA_INTDEF(config.base)) & 0x0F;
3389 if ((inb(HA_274_BIOSCTRL(base)) & BIOSMODE) == BIOSDISABLED)
3390 {3391 bios_disabled = 1;
3392 }3393 host_conf = inb(HA_HOSTCONF(config.base));
3394 config.busrtime = host_conf & 0x3C;
3395 /* XXX Is this valid for motherboard based controllers? */3396 /* Setup the FIFO threshold and the bus off time */3397 outb(host_conf & DFTHRSH, BUSSPD(config.base));
3398 outb((host_conf << 2) & BOFF, BUSTIME(config.base));
3399
3400 /*3401 * A reminder until this can be detected automatically.3402 */3403 printk("aha284x: extended translation %sabled\n",
3404 config.extended ? "en" : "dis");
3405 break;
3406
3407 caseAIC_7850:
3408 caseAIC_7870:
3409 caseAIC_7872:
3410 #if 0
3411 printk("aic%s hcntrl=0x%x\n", board_name[type], inb(HCNTRL(config.base)));
3412 #endif3413
3414 outb(CHIPRST, HCNTRL(config.base));
3415 config.unpause = UNPAUSE_294X;
3416 config.pause = config.unpause | PAUSE;
3417 config.extended = aic7xxx_extended;
3418 config.scsi_id = 7;
3419
3420 printk("aic78xx: Reading SEEPROM... ");
3421 have_seeprom = read_seeprom(base, &sc);
3422 if (!have_seeprom)
3423 {3424 printk("aic78xx: unable to read SEEPROM\n");
3425 }3426 else3427 {3428 printk("done\n");
3429 config.extended = ((sc.bios_control & CFEXTEND) >> 7);
3430 config.scsi_id = (sc.brtime_id & CFSCSIID);
3431 config.parity = (sc.adapter_control & CFSPARITY) ?
3432 AIC_ENABLED : AIC_DISABLED;
3433 config.low_term = (sc.adapter_control & CFSTERM) ?
3434 AIC_ENABLED : AIC_DISABLED;
3435 config.high_term = (sc.adapter_control & CFWSTERM) ?
3436 AIC_ENABLED : AIC_DISABLED;
3437 config.busrtime = ((sc.brtime_id & CFBRTIME) >> 8);
3438 }3439
3440 /*3441 * XXX - force data fifo threshold to 100%. Why does this3442 * need to be done?3443 */3444 outb(inb(DSPCISTATUS(config.base)) | DFTHRESH, DSPCISTATUS(config.base));
3445 outb(config.scsi_id | DFTHRESH, HA_SCSICONF(config.base));
3446
3447 /*3448 * In case we are a wide card, place scsi ID in second conf byte.3449 */3450 outb(config.scsi_id, (HA_SCSICONF(config.base) + 1));
3451
3452 /*3453 * A reminder until this can be detected automatically.3454 */3455 printk("aic%s: extended translation %sabled\n", board_name[type],
3456 config.extended ? "en" : "dis");
3457 break;
3458
3459 default:
3460 panic("aic7xxx_register: internal error\n");
3461 }3462
3463 config.maxscb = detect_maxscb(type, base);
3464
3465 if ((config.type == AIC_274x) || (config.type == AIC_284x))
3466 {3467 if (config.pause & IRQMS)
3468 {3469 printk("aic7xxx: Using Level Sensitive Interrupts\n");
3470 }3471 else3472 {3473 printk("aic7xxx: Using Edge Triggered Interrupts\n");
3474 }3475 }3476
3477 /*3478 * Read the bus type from the SBLKCTL register. Set the FLAGS3479 * register in the sequencer for twin and wide bus cards.3480 */3481 sblkctl = inb(SBLKCTL(base)) & 0x0F; /* mask out upper two bits */3482 switch (sblkctl)
3483 {3484 caseSELSINGLE: /* narrow/normal bus */3485 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3486 config.bus_type = AIC_SINGLE;
3487 outb(SINGLE_BUS, HA_FLAGS(base));
3488 break;
3489
3490 caseSELWIDE: /* Wide bus */3491 config.scsi_id = inb(HA_SCSICONF(base) + 1) & 0x0F;
3492 config.bus_type = AIC_WIDE;
3493 printk("aic7xxx: Enabling wide channel of %s-Wide\n",
3494 board_name[config.type]);
3495 outb(WIDE_BUS, HA_FLAGS(base));
3496 break;
3497
3498 caseSELBUSB: /* Twin bus */3499 config.scsi_id = inb(HA_SCSICONF(base)) & 0x07;
3500 #ifdefAIC7XXX_TWIN_SUPPORT3501 config.scsi_id_b = inb(HA_SCSICONF(base) + 1) & 0x07;
3502 config.bus_type = AIC_TWIN;
3503 printk("aic7xxx: Enabled channel B of %s-Twin\n",
3504 board_name[config.type]);
3505 outb(TWIN_BUS, HA_FLAGS(base));
3506 #else3507 config.bus_type = AIC_SINGLE;
3508 printk("aic7xxx: Channel B of %s-Twin will be ignored\n",
3509 board_name[config.type]);
3510 outb(0, HA_FLAGS(base));
3511 #endif3512 break;
3513
3514 default:
3515 printk("aic7xxx is an unsupported type 0x%x, please "
3516 "mail deang@ims.com\n", inb(SBLKCTL(base)));
3517 outb(0, HA_FLAGS(base));
3518 return (0);
3519 }3520
3521 /*3522 * Clear the upper two bits. For the 294x cards, clearing the3523 * upper two bits, will take the card out of diagnostic mode3524 * and make the host adatper LED follow bus activity (will not3525 * always be on).3526 */3527 outb(sblkctl, SBLKCTL(base));
3528
3529 /*3530 * The IRQ level in i/o port 4 maps directly onto the real3531 * IRQ number. If it's ok, register it with the kernel.3532 *3533 * NB. the Adaptec documentation says the IRQ number is only3534 * in the lower four bits; the ECU information shows the3535 * high bit being used as well. Which is correct?3536 *3537 * The 294x cards (PCI) get their interrupt from PCI BIOS.3538 */3539 if (((config.type == AIC_274x) || (config.type == AIC_284x))
3540 && (config.irq < 9 || config.irq > 15))
3541 {3542 printk("aic7xxx uses unsupported IRQ level, ignoring\n");
3543 return (0);
3544 }3545
3546 /*3547 * Check the IRQ to see if it is shared by another aic7xxx3548 * controller. If it is and sharing of IRQs is not defined,3549 * then return 0 hosts found. If sharing of IRQs is allowed3550 * or the IRQ is not shared by another host adapter, then3551 * proceed.3552 */3553 #ifndefAIC7XXX_SHARE_IRQS3554 if (aic7xxx_boards[config.irq] != NULL)
3555 {3556 printk("aic7xxx_register: Sharing of IRQs is not configured.\n");
3557 return (0);
3558 }3559 #endif3560
3561 /*3562 * Print out debugging information before re-enabling3563 * the card - a lot of registers on it can't be read3564 * when the sequencer is active.3565 */3566 debug_config(&config);
3567
3568 /*3569 * Before registry, make sure that the offsets of the3570 * struct scatterlist are what the sequencer will expect,3571 * otherwise disable scatter-gather altogether until someone3572 * can fix it. This is important since the sequencer will3573 * DMA elements of the SG array in while executing commands.3574 */3575 if (template->sg_tablesize != SG_NONE)
3576 {3577 structscatterlistsg;
3578
3579 if (SG_STRUCT_CHECK(sg))
3580 {3581 printk("aic7xxx warning: kernel scatter-gather "
3582 "structures changed, disabling it\n");
3583 template->sg_tablesize = SG_NONE;
3584 }3585 }3586
3587 /*3588 * Register each "host" and fill in the returned Scsi_Host3589 * structure as best we can. Some of the parameters aren't3590 * really relevant for bus types beyond ISA, and none of the3591 * high-level SCSI code looks at it anyway. Why are the fields3592 * there? Also save the pointer so that we can find the3593 * information when an IRQ is triggered.3594 */3595 host = scsi_register(template, sizeof(structaic7xxx_host));
3596 host->can_queue = config.maxscb;
3597 host->cmd_per_lun = AIC7XXX_CMDS_PER_LUN;
3598 host->this_id = config.scsi_id;
3599 host->irq = config.irq;
3600 if (config.bus_type == AIC_WIDE)
3601 {3602 host->max_id = 16;
3603 }3604 if (config.bus_type == AIC_TWIN)
3605 {3606 host->max_channel = 1;
3607 }3608
3609 p = (structaic7xxx_host *) host->hostdata;
3610
3611 /*3612 * Initialize the scb array by setting the state to free.3613 */3614 for (i = 0; i < AIC7XXX_MAXSCB; i++)
3615 {3616 p->scb_array[i].state = SCB_FREE;
3617 p->scb_array[i].next = NULL;
3618 p->scb_array[i].cmd = NULL;
3619 }3620
3621 p->isr_count = 0;
3622 p->a_scanned = 0;
3623 p->b_scanned = 0;
3624 p->base = config.base;
3625 p->maxscb = config.maxscb;
3626 p->numscb = 0;
3627 p->extended = config.extended;
3628 p->type = config.type;
3629 p->bus_type = config.bus_type;
3630 p->have_seeprom = have_seeprom;
3631 p->seeprom = sc;
3632 p->free_scb = NULL;
3633 p->next = NULL;
3634
3635 p->unpause = config.unpause;
3636 p->pause = config.pause;
3637
3638 if (aic7xxx_boards[config.irq] == NULL)
3639 {3640 /*3641 * Warning! This must be done before requesting the irq. It is3642 * possible for some boards to raise an interrupt as soon as3643 * they are enabled. So when we request the irq from the Linux3644 * kernel, an interrupt is triggered immediately. Therefore, we3645 * must ensure the board data is correctly set before the request.3646 */3647 aic7xxx_boards[config.irq] = host;
3648
3649 /*3650 * Register IRQ with the kernel.3651 */3652 if (request_irq(config.irq, aic7xxx_isr, SA_INTERRUPT, "aic7xxx"))
3653 {3654 printk("aic7xxx couldn't register irq %d, ignoring\n", config.irq);
3655 aic7xxx_boards[config.irq] = NULL;
3656 return (0);
3657 }3658 }3659 else3660 {3661 /*3662 * We have found a host adapter sharing an IRQ of a previously3663 * registered host adapter. Add this host adapter's Scsi_Host3664 * to the beginning of the linked list of hosts at the same IRQ.3665 */3666 p->next = aic7xxx_boards[config.irq];
3667 aic7xxx_boards[config.irq] = host;
3668 }3669
3670 /*3671 * Load the sequencer program, then re-enable the board -3672 * resetting the AIC-7770 disables it, leaving the lights3673 * on with nobody home. On the PCI bus you *may* be home,3674 * but then your mailing address is dynamically assigned3675 * so no one can find you anyway :-)3676 */3677 printk("aic7xxx: Downloading sequencer code..");
3678 aic7xxx_loadseq(base);
3679
3680 /*3681 * Set Fast Mode and Enable the board3682 */3683 outb(FASTMODE, SEQCTL(base));
3684
3685 if ((p->type == AIC_274x) || (p->type == AIC_284x))
3686 {3687 outb(ENABLE, BCTL(base));
3688 }3689
3690 printk("done.\n");
3691
3692 /*3693 * Set the SCSI Id, SXFRCTL1, and SIMODE1, for both channels3694 */3695 if (p->bus_type == AIC_TWIN)
3696 {3697 /*3698 * The device is gated to channel B after a chip reset,3699 * so set those values first.3700 */3701 outb(config.scsi_id_b, SCSIID(base));
3702 scsi_conf = inb(HA_SCSICONF(base) + 1) & (ENSPCHK | STIMESEL);
3703 outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3704 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3705 /*3706 * Select Channel A3707 */3708 outb(SELSINGLE, SBLKCTL(base));
3709 }3710 outb(config.scsi_id, SCSIID(base));
3711 scsi_conf = inb(HA_SCSICONF(base)) & (ENSPCHK | STIMESEL);
3712 outb(scsi_conf | ENSTIMER | ACTNEGEN | STPWEN, SXFRCTL1(base));
3713 outb(ENSELTIMO | ENSCSIPERR, SIMODE1(base));
3714
3715 /*3716 * Look at the information that board initialization or the board3717 * BIOS has left us. In the lower four bits of each target's3718 * scratch space any value other than 0 indicates that we should3719 * initiate synchronous transfers. If it's zero, the user or the3720 * BIOS has decided to disable synchronous negotiation to that3721 * target so we don't activate the needsdtr flag.3722 */3723 p->needsdtr_copy = 0;
3724 p->sdtr_pending = 0;
3725 p->needwdtr_copy = 0;
3726 p->wdtr_pending = 0;
3727 if (p->bus_type == AIC_SINGLE)
3728 {3729 max_targets = 8;
3730 }3731 else3732 {3733 max_targets = 16;
3734 }3735 /*3736 * Grab the disconnection disable table and invert it for our needs3737 */3738 if (have_seeprom)
3739 {3740 p->discenable = 0;
3741 }3742 else3743 {3744 if (bios_disabled)
3745 {3746 printk("aic7xxx : Host Adapter Bios disabled. Using default SCSI "
3747 "device parameters\n");
3748 p->discenable = 0xFFFF;
3749 }3750 else3751 {3752 p->discenable = ~(inw(HA_DISC_DSB(base)));
3753 }3754 }3755
3756 for (i = 0; i < max_targets; i++)
3757 {3758 if (have_seeprom)
3759 {3760 target_settings = ((sc.device_flags[i] & CFXFER) << 4);
3761 if (sc.device_flags[i] & CFSYNCH)
3762 {3763 p->needsdtr_copy |= (0x01 << i);
3764 }3765 if ((sc.device_flags[i] & CFWIDEB) && (p->bus_type == AIC_WIDE))
3766 {3767 p->needwdtr_copy |= (0x01 << i);
3768 }3769 if (sc.device_flags[i] & CFDISC)
3770 {3771 p->discenable |= (0x01 << i);
3772 }3773 }3774 else3775 {3776 target_settings = inb(HA_TARG_SCRATCH(base) + i);
3777 if (target_settings & 0x0F)
3778 {3779 p->needsdtr_copy |= (0x01 << i);
3780 /*3781 * Default to asynchronous transfers (0 offset)3782 */3783 target_settings &= 0xF0;
3784 }3785 /*3786 * If we are not wide, forget WDTR. This makes the driver3787 * work on some cards that don't leave these fields cleared3788 * when BIOS is not installed.3789 */3790 if ((target_settings & 0x80) && (p->bus_type == AIC_WIDE))
3791 {3792 p->needwdtr_copy |= (0x01 << i);
3793 target_settings &= 0x7F;
3794 }3795 }3796 outb(target_settings, (HA_TARG_SCRATCH(base) + i));
3797 }3798
3799 p->needsdtr = p->needsdtr_copy;
3800 p->needwdtr = p->needwdtr_copy;
3801 #if 0
3802 printk("NeedSdtr = 0x%x, 0x%x\n", p->needsdtr_copy, p->needsdtr);
3803 printk("NeedWdtr = 0x%x, 0x%x\n", p->needwdtr_copy, p->needwdtr);
3804 #endif3805
3806 /*3807 * Clear the control byte for every SCB so that the sequencer3808 * doesn't get confused and think that one of them is valid3809 */3810 for (i = 0; i < config.maxscb; i++)
3811 {3812 outb(i, SCBPTR(base));
3813 outb(0, SCBARRAY(base));
3814 }3815
3816 /*3817 * For reconnecting targets, the sequencer code needs to3818 * know how many SCBs it has to search through.3819 */3820 outb(config.maxscb, HA_SCBCOUNT(base));
3821
3822 /*3823 * Clear the active flags - no targets are busy.3824 */3825 outb(0, HA_ACTIVE0(base));
3826 outb(0, HA_ACTIVE1(base));
3827
3828 /*3829 * We don't have any waiting selections3830 */3831 outb(SCB_LIST_NULL, WAITING_SCBH(base));
3832 outb(SCB_LIST_NULL, WAITING_SCBT(base));
3833
3834 /*3835 * Reset the SCSI bus. Is this necessary?3836 * There may be problems for a warm boot without resetting3837 * the SCSI bus. Either BIOS settings in scratch RAM3838 * will not get reinitialized, or devices may stay at3839 * previous negotiated settings (SDTR and WDTR) while3840 * the driver will think that no negotiations have been3841 * performed.3842 *3843 * Some devices need a long time to "settle" after a SCSI3844 * bus reset.3845 */3846
3847 if (!aic7xxx_no_reset)
3848 {3849 printk("Resetting the SCSI bus...\n");
3850 if (p->bus_type == AIC_TWIN)
3851 {3852 /*3853 * Select channel B.3854 */3855 outb(SELBUSB, SBLKCTL(base));
3856 outb(SCSIRSTO, SCSISEQ(base));
3857 udelay(1000);
3858 outb(0, SCSISEQ(base));
3859 /*3860 * Select channel A.3861 */3862 outb(SELSINGLE, SBLKCTL(base));
3863 }3864
3865 outb(SCSIRSTO, SCSISEQ(base));
3866 udelay(1000);
3867 outb(0, SCSISEQ(base));
3868 aic7xxx_delay(AIC7XXX_RESET_DELAY);
3869 }3870
3871 /*3872 * Unpause the sequencer before returning and enable3873 * interrupts - we shouldn't get any until the first3874 * command is sent to us by the high-level SCSI code.3875 */3876 UNPAUSE_SEQUENCER(p);
3877 return (found);
3878 }3879
3880 /*+F*************************************************************************3881 * Function:3882 * aic7xxx_detect3883 *3884 * Description:3885 * Try to detect and register an Adaptec 7770 or 7870 SCSI controller.3886 *-F*************************************************************************/3887 int3888 aic7xxx_detect(Scsi_Host_Template *template)
/* */3889 {3890 aha_typetype = AIC_NONE;
3891 intfound = 0, slot, base;
3892 unsignedcharirq = 0;
3893 inti;
3894
3895 template->proc_dir = &proc_scsi_aic7xxx;
3896
3897 /*3898 * Since we may allow sharing of IRQs, it is imperative3899 * that we "null-out" the aic7xxx_boards array. It is3900 * not guaranteed to be initialized to 0 (NULL). We use3901 * a NULL entry to indicate that no prior hosts have3902 * been found/registered for that IRQ.3903 */3904 for (i = 0; i <= MAXIRQ; i++)
3905 {3906 aic7xxx_boards[i] = NULL;
3907 }3908
3909 /*3910 * Initialize the spurious count to 0.3911 */3912 aic7xxx_spurious_count = 0;
3913
3914 /*3915 * EISA/VL-bus card signature probe.3916 */3917 for (slot = MINSLOT; slot <= MAXSLOT; slot++)
3918 {3919 base = SLOTBASE(slot);
3920
3921 if (check_region(MINREG(base), MAXREG(base) - MINREG(base)))
3922 {3923 /*3924 * Some other driver has staked a3925 * claim to this i/o region already.3926 */3927 continue;
3928 }3929
3930 type = aic7xxx_probe(slot, HID0(base));
3931 if (type != AIC_NONE)
3932 {3933 /*3934 * We found a card, allow 1 spurious interrupt.3935 */3936 aic7xxx_spurious_count = 1;
3937
3938 #if 0
3939 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
3940 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
3941 irq = inb(HA_INTDEF(base)) & 0x0F;
3942 #endif3943
3944 /*3945 * We "find" a AIC-7770 if we locate the card3946 * signature and we can set it up and register3947 * it with the kernel without incident.3948 */3949 found += aic7xxx_register(template, type, base, irq);
3950
3951 /*3952 * Disallow spurious interrupts.3953 */3954 aic7xxx_spurious_count = 0;
3955 }3956 }3957
3958 #ifdefCONFIG_PCI3959
3960 #defineDEVREVID 0x08
3961 #defineDEVCONFIG 0x40
3962 #defineDEVSTATUS 0x41
3963 #defineRAMPSM 0x02
3964
3965 /*3966 * PCI-bus probe.3967 */3968 if (pcibios_present())
3969 {3970 interror;
3971 intdone = 0;
3972 unsignedintio_port;
3973 unsignedshortindex = 0;
3974 unsignedcharpci_bus, pci_device_fn;
3975 unsignedchardevrevid, devconfig, devstatus;
3976 charrev_id[] = {'B', 'C', 'D'};
3977
3978 while (!done)
3979 {3980 if ((!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3981 PCI_DEVICE_ID_ADAPTEC_7870,
3982 index, &pci_bus, &pci_device_fn)) ||
3983 (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3984 PCI_DEVICE_ID_ADAPTEC_7871,
3985 index, &pci_bus, &pci_device_fn)))
3986 {3987 type = AIC_7870;
3988 }3989 else3990 {3991 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
3992 PCI_DEVICE_ID_ADAPTEC_7850,
3993 index, &pci_bus, &pci_device_fn))
3994 {3995 type = AIC_7850;
3996 }3997 else3998 {3999 if (!pcibios_find_device(PCI_VENDOR_ID_ADAPTEC,
4000 PCI_DEVICE_ID_ADAPTEC_7872,
4001 index, &pci_bus, &pci_device_fn))
4002 {4003 type = AIC_7872;
4004 }4005 else4006 {4007 type = AIC_NONE;
4008 done = 1;
4009 }4010 }4011 }4012
4013 if (!done)
4014 {4015 /*4016 * Read esundry information from PCI BIOS.4017 */4018 error = pcibios_read_config_dword(pci_bus, pci_device_fn,
4019 PCI_BASE_ADDRESS_0, &io_port);
4020
4021 if (error)
4022 {4023 panic("aic7xxx_detect: error 0x%x reading i/o port.\n", error);
4024 }4025
4026 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4027 PCI_INTERRUPT_LINE, &irq);
4028 if (error)
4029 {4030 panic("aic7xxx_detect: error %d reading irq.\n", error);
4031 }4032
4033 /*4034 * Make the base I/O register look like EISA and VL-bus.4035 */4036 base = io_port - 0xC01;
4037
4038 /*4039 * I don't think we need to bother with allowing4040 * spurious interrupts for the 787x/7850, but what4041 * the hey.4042 */4043 aic7xxx_spurious_count = 1;
4044
4045 #if 0
4046 printk("aic7xxx: hcntrl=0x%x\n", inb(HCNTRL(base)));
4047 #endif4048 outb(inb(HCNTRL(base)) | CHIPRST, HCNTRL(base));
4049
4050 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4051 DEVREVID, &devrevid);
4052 if (devrevid < 3)
4053 {4054 printk("aic7xxx_detect: AIC-7870 Rev %c\n", rev_id[devrevid]);
4055 }4056 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4057 DEVCONFIG, &devconfig);
4058 error = pcibios_read_config_byte(pci_bus, pci_device_fn,
4059 DEVSTATUS, &devstatus);
4060 printk("aic7xxx_detect: devconfig 0x%x, devstatus 0x%x\n",
4061 devconfig, devstatus);
4062 if (devstatus & RAMPSM)
4063 {4064 printk("aic7xxx_detect: detected external SCB RAM, "
4065 "mail deang@ims.com for test patch");
4066 }4067
4068 found += aic7xxx_register(template, type, base, irq);
4069
4070 /*4071 * Disable spurious interrupts.4072 */4073 aic7xxx_spurious_count = 0;
4074
4075 index++;
4076 }4077 }4078 }4079 #endifCONFIG_PCI4080
4081 template->name = aic7xxx_info(NULL);
4082 return (found);
4083 }4084
4085
4086 /*+F*************************************************************************4087 * Function:4088 * aic7xxx_buildscb4089 *4090 * Description:4091 * Build a SCB.4092 *-F*************************************************************************/4093 staticvoid4094 aic7xxx_buildscb(structaic7xxx_host *p,
/* */4095 Scsi_Cmnd *cmd,
4096 structaic7xxx_scb *scb)
4097 {4098 void *addr;
4099 unsignedshortmask;
4100 structscatterlist *sg;
4101
4102 /*4103 * Setup the control byte if we need negotiation and have not4104 * already requested it.4105 */4106 #ifdefAIC7XXX_TAGGED_QUEUEING4107 if (cmd->device->tagged_supported)
4108 {4109 if (cmd->device->tagged_queue == 0)
4110 {4111 printk("aic7xxx_buildscb: Enabling tagged queuing for target %d, "
4112 "channel %d\n", cmd->target, cmd->channel);
4113 cmd->device->tagged_queue = 1;
4114 cmd->device->current_tag = 1; /* enable tagging */4115 }4116 cmd->tag = cmd->device->current_tag;
4117 cmd->device->current_tag++;
4118 scb->control |= SCB_TE;
4119 }4120 #endif4121 mask = (0x01 << (cmd->target | (cmd->channel << 3)));
4122 if (p->discenable & mask)
4123 {4124 scb->control |= SCB_DISCENB;
4125 }4126 if ((p->needwdtr & mask) && !(p->wdtr_pending & mask))
4127 {4128 p->wdtr_pending |= mask;
4129 scb->control |= SCB_NEEDWDTR;
4130 #if 0
4131 printk("Sending WDTR request to target %d.\n", cmd->target);
4132 #endif4133 }4134 else4135 {4136 if ((p->needsdtr & mask) && !(p->sdtr_pending & mask))
4137 {4138 p->sdtr_pending |= mask;
4139 scb->control |= SCB_NEEDSDTR;
4140 #if 0
4141 printk("Sending SDTR request to target %d.\n", cmd->target);
4142 #endif4143 }4144 }4145
4146 #if 0
4147 printk("aic7xxx_queue: target %d, cmd 0x%x (size %u), wdtr 0x%x, mask 0x%x\n",
4148 cmd->target, cmd->cmnd[0], cmd->cmd_len, p->needwdtr, mask);
4149 #endif4150 scb->target_channel_lun = ((cmd->target << 4) & 0xF0) |
4151 ((cmd->channel & 0x01) << 3) | (cmd->lun & 0x07);
4152
4153 /*4154 * The interpretation of request_buffer and request_bufflen4155 * changes depending on whether or not use_sg is zero; a4156 * non-zero use_sg indicates the number of elements in the4157 * scatter-gather array.4158 */4159
4160 /*4161 * XXX - this relies on the host data being stored in a4162 * little-endian format.4163 */4164 addr = cmd->cmnd;
4165 scb->SCSI_cmd_length = cmd->cmd_len;
4166 memcpy(scb->SCSI_cmd_pointer, &addr, sizeof(scb->SCSI_cmd_pointer));
4167
4168 if (cmd->use_sg)
4169 {4170 #if 0
4171 debug("aic7xxx_buildscb: SG used, %d segments, length %u\n",
4172 cmd->use_sg, length);
4173 #endif4174 scb->SG_segment_count = cmd->use_sg;
4175 memcpy(scb->SG_list_pointer, &cmd->request_buffer,
4176 sizeof(scb->SG_list_pointer));
4177 memcpy(&sg, &cmd->request_buffer, sizeof(sg));
4178 memcpy(scb->data_pointer, &(sg[0].address), sizeof(scb->data_pointer));
4179 scb->data_count[0] = sg[0].length & 0xFF;
4180 scb->data_count[1] = (sg[0].length >> 8) & 0xFF;
4181 scb->data_count[2] = (sg[0].length >> 16) & 0xFF;
4182 }4183 else4184 {4185 #if 0
4186 debug("aic7xxx_buildscb: Creating scatterlist, addr=0x%lx, length=%d.\n",
4187 (unsignedlong) cmd->request_buffer, cmd->request_bufflen);
4188 #endif4189 if (cmd->request_bufflen == 0)
4190 {4191 /*4192 * In case the higher level SCSI code ever tries to send a zero4193 * length command, ensure the SCB indicates no data. The driver4194 * will interpret a zero length command as a Bus Device Reset.4195 */4196 scb->SG_segment_count = 0;
4197 memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4198 memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4199 memset(scb->data_count, 0, sizeof(scb->data_count));
4200 }4201 else4202 {4203 scb->SG_segment_count = 1;
4204 scb->sg.address = (char *) cmd->request_buffer;
4205 scb->sg.length = cmd->request_bufflen;
4206 addr = &scb->sg;
4207 memcpy(scb->SG_list_pointer, &addr, sizeof(scb->SG_list_pointer));
4208 scb->data_count[0] = scb->sg.length & 0xFF;
4209 scb->data_count[1] = (scb->sg.length >> 8) & 0xFF;
4210 scb->data_count[2] = (scb->sg.length >> 16) & 0xFF;
4211 memcpy(scb->data_pointer, &cmd->request_buffer, sizeof(scb->data_pointer));
4212 }4213 }4214 }4215
4216 /*+F*************************************************************************4217 * Function:4218 * aic7xxx_queue4219 *4220 * Description:4221 * Queue a SCB to the controller.4222 *-F*************************************************************************/4223 int4224 aic7xxx_queue(Scsi_Cmnd *cmd, void (*fn)(Scsi_Cmnd *))
/* */4225 {4226 longflags;
4227 structaic7xxx_host *p;
4228 structaic7xxx_scb *scb;
4229 unsignedcharcurscb;
4230
4231 p = (structaic7xxx_host *) cmd->host->hostdata;
4232
4233 /*4234 * Check to see if channel was scanned.4235 */4236 if (!p->a_scanned && (cmd->channel == 0))
4237 {4238 printk("aic7xxx: Scanning channel A for devices.\n");
4239 p->a_scanned = 1;
4240 }4241 else4242 {4243 if (!p->b_scanned && (cmd->channel == 1))
4244 {4245 printk("aic7xxx: Scanning channel B for devices.\n");
4246 p->b_scanned = 1;
4247 }4248 }4249
4250 #if 0
4251 debug("aic7xxx_queue: cmd 0x%x (size %u), target %d, channel %d, lun %d\n",
4252 cmd->cmnd[0], cmd->cmd_len, cmd->target, cmd->channel,
4253 cmd->lun & 0x07);
4254 #endif4255
4256 /*4257 * This is a critical section, since we don't want the4258 * interrupt routine mucking with the host data or the4259 * card. Since the kernel documentation is vague on4260 * whether or not we are in a cli/sti pair already, save4261 * the flags to be on the safe side.4262 */4263 save_flags(flags);
4264 cli();
4265
4266 /*4267 * Find a free slot in the SCB array to load this command4268 * into. Since can_queue is set to the maximum number of4269 * SCBs for the card, we should always find one.4270 *4271 * First try to find an scb in the free list. If there are4272 * none in the free list, then check the current number of4273 * of scbs and take an unused one from the scb array.4274 */4275 scb = p->free_scb;
4276 if (scb != NULL)
4277 {/* found one in the free list */4278 p->free_scb = scb->next; /* remove and update head of list */4279 /*4280 * Warning! For some unknown reason, the scb at the head4281 * of the free list is not the same address that it should4282 * be. That's why we set the scb pointer taken by the4283 * position in the array. The scb at the head of the list4284 * should match this address, but it doesn't.4285 */4286 scb = &(p->scb_array[scb->position]);
4287 scb->control = 0;
4288 scb->state = SCB_ACTIVE;
4289 }4290 else4291 {4292 if (p->numscb >= p->maxscb)
4293 {4294 panic("aic7xxx_queue: couldn't find a free scb\n");
4295 }4296 else4297 {4298 /*4299 * Initialize the scb within the scb array. The4300 * position within the array is the position on4301 * the board that it will be loaded.4302 */4303 scb = &(p->scb_array[p->numscb]);
4304 memset(scb, 0, sizeof(*scb));
4305
4306 scb->position = p->numscb;
4307 p->numscb++;
4308 scb->state = SCB_ACTIVE;
4309 scb->next_waiting = SCB_LIST_NULL;
4310 memcpy(scb->host_scb, &scb, sizeof(scb));
4311 scb->control = SCB_NEEDDMA;
4312 PAUSE_SEQUENCER(p);
4313 curscb = inb(SCBPTR(p->base));
4314 outb(scb->position, SCBPTR(p->base));
4315 aic7xxx_putscb_dma(p->base, scb);
4316 outb(curscb, SCBPTR(p->base));
4317 UNPAUSE_SEQUENCER(p);
4318 scb->control = 0;
4319 }4320 }4321
4322 scb->cmd = cmd;
4323 aic7xxx_position(cmd) = scb->position;
4324 #if 0
4325 debug_scb(scb);
4326 #endif;
4327
4328 /*4329 * Construct the SCB beforehand, so the sequencer is4330 * paused a minimal amount of time.4331 */4332 aic7xxx_buildscb(p, cmd, scb);
4333
4334 #if 0
4335 if (scb != &p->scb_array[scb->position])
4336 {4337 printk("aic7xxx_queue: address of scb by position does not match scb address\n");
4338 }4339 printk("aic7xxx_queue: SCB pos=%d, cmdptr=0x%x, state=%d, freescb=0x%x\n",
4340 scb->position, (unsignedint) scb->cmd,
4341 scb->state, (unsignedint) p->free_scb);
4342 #endif4343 /*4344 * Pause the sequencer so we can play with its registers -4345 * wait for it to acknowledge the pause.4346 *4347 * XXX - should the interrupts be left on while doing this?4348 */4349 PAUSE_SEQUENCER(p);
4350
4351 /*4352 * Save the SCB pointer and put our own pointer in - this4353 * selects one of the four banks of SCB registers. Load4354 * the SCB, then write its pointer into the queue in FIFO4355 * and restore the saved SCB pointer.4356 */4357 aic7xxx_putscb(p->base, scb);
4358
4359 /*4360 * Make sure the Scsi_Cmnd pointer is saved, the struct it4361 * points to is set up properly, and the parity error flag4362 * is reset, then unpause the sequencer and watch the fun4363 * begin.4364 */4365 cmd->scsi_done = fn;
4366 aic7xxx_error(cmd) = DID_OK;
4367 aic7xxx_status(cmd) = 0;
4368 scb->timer_status = 0x0;
4369 cmd->result = 0;
4370 memset(&cmd->sense_buffer, 0, sizeof(cmd->sense_buffer));
4371
4372 UNPAUSE_SEQUENCER(p);
4373 #if 0
4374 printk("aic7xxx_queue: After - cmd = 0x%lx, scb->cmd = 0x%lx, pos = %d\n",
4375 (long) cmd, (long) scb->cmd, scb->position);
4376 #endif;
4377 restore_flags(flags);
4378 return (0);
4379 }4380
4381 /*+F*************************************************************************4382 * Function:4383 * aic7xxx_abort_scb4384 *4385 * Description:4386 * Abort an scb. If the scb has not previously been aborted, then4387 * we attempt to send a BUS_DEVICE_RESET message to the target. If4388 * the scb has previously been unsuccessfully aborted, then we will4389 * reset the channel and have all devices renegotiate.4390 *-F*************************************************************************/4391 staticvoid4392 aic7xxx_abort_scb(structaic7xxx_host *p, structaic7xxx_scb *scb)
/* */4393 {4394 intbase = p->base;
4395 intfound = 0;
4396 charchannel = scb->target_channel_lun & SELBUSB ? 'B': 'A';
4397
4398 /*4399 * Ensure that the card doesn't do anything4400 * behind our back.4401 */4402 PAUSE_SEQUENCER(p);
4403
4404 /*4405 * First, determine if we want to do a bus reset or simply a bus device4406 * reset. If this is the first time that a transaction has timed out,4407 * just schedule a bus device reset. Otherwise, we reset the bus and4408 * abort all pending I/Os on that bus.4409 */4410 if (scb->state & SCB_ABORTED)
4411 {4412 /*4413 * Been down this road before. Do a full bus reset.4414 */4415 found = aic7xxx_reset_channel(p, channel, scb->position);
4416 }4417 else4418 {4419 unsignedcharactive_scb, control;
4420 structaic7xxx_scb *active_scbp;
4421
4422 /*4423 * Send a Bus Device Reset Message:4424 * The target we select to send the message to may be entirely4425 * different than the target pointed to by the scb that timed4426 * out. If the command is in the QINFIFO or the waiting for4427 * selection list, its not tying up the bus and isn't responsible4428 * for the delay so we pick off the active command which should4429 * be the SCB selected by SCBPTR. If its disconnected or active,4430 * we device reset the target scbp points to. Although it may4431 * be that this target is not responsible for the delay, it may4432 * may also be that we're timing out on a command that just takes4433 * too much time, so we try the bus device reset there first.4434 */4435 active_scb = inb(SCBPTR(base));
4436 active_scbp = &(p->scb_array[active_scb]);
4437 control = inb(SCBARRAY(base));
4438
4439 /*4440 * Test to see if scbp is disconnected4441 */4442 outb(scb->position, SCBPTR(base));
4443 if (inb(SCBARRAY(base)) & SCB_DIS)
4444 {4445 scb->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4446 scb->SG_segment_count = 0;
4447 memset(scb->SG_list_pointer, 0, sizeof(scb->SG_list_pointer));
4448 memset(scb->data_pointer, 0, sizeof(scb->data_pointer));
4449 memset(scb->data_count, 0, sizeof(scb->data_count));
4450 outb(SCBAUTO, SCBCNT(base));
4451 asmvolatile("cld\n\t"
4452 "rep\n\t"
4453 "outsb"
4454 : /* no output */4455 :"S" (scb), "c" (SCB_DOWNLOAD_SIZE), "d" (SCBARRAY(base))
4456 :"si", "cx", "dx");
4457 outb(0, SCBCNT(base));
4458 aic7xxx_add_waiting_scb(base, scb, LIST_SECOND);
4459 aic7xxx_scb_tsleep(p, scb, 2 * HZ); /* unpauses the sequencer */4460 }4461 else4462 {4463 /*4464 * Is the active SCB really active?4465 */4466 if ((active_scbp->state & SCB_ACTIVE) && (control & SCB_NEEDDMA))
4467 {4468 unsignedcharflags = inb(HA_FLAGS(base));
4469 if (flags & ACTIVE_MSG)
4470 {4471 /*4472 * If we're in a message phase, tacking on another message4473 * may confuse the target totally. The bus is probably wedged,4474 * so reset the channel.4475 */4476 channel = (active_scbp->target_channel_lun & SELBUSB) ? 'B': 'A';
4477 aic7xxx_reset_channel(p, channel, scb->position);
4478 }4479 else4480 {4481 /*4482 * Load the message buffer and assert attention.4483 */4484 active_scbp->state |= (SCB_DEVICE_RESET | SCB_ABORTED);
4485 outb(flags | ACTIVE_MSG, HA_FLAGS(base));
4486 outb(1, HA_MSG_LEN(base));
4487 outb(MSG_BUS_DEVICE_RESET, HA_MSG_START(base));
4488 if (active_scbp->target_channel_lun != scb->target_channel_lun)
4489 {4490 /*4491 * XXX - We would like to increment the timeout on scb, but4492 * access to that routine is denied because it is hidden4493 * in scsi.c. If we were able to do this, it would give4494 * scb a new lease on life.4495 */4496 ;
4497 }4498 aic7xxx_scb_tsleep(p, active_scbp, 2 * HZ);
4499 }4500 }4501 else4502 {4503 /*4504 * No active command to single out, so reset4505 * the bus for the timed out target.4506 */4507 aic7xxx_reset_channel(p, channel, scb->position);
4508 }4509 }4510 }4511 }4512
4513 /*+F*************************************************************************4514 * Function:4515 * aic7xxx_abort4516 *4517 * Description:4518 * Abort the current SCSI command(s).4519 *-F*************************************************************************/4520 int4521 aic7xxx_abort(Scsi_Cmnd *cmd)
/* */4522 {4523 structaic7xxx_scb *scb;
4524 structaic7xxx_host *p;
4525 longflags;
4526
4527 p = (structaic7xxx_host *) cmd->host->hostdata;
4528 scb = &(p->scb_array[aic7xxx_position(cmd)]);
4529
4530 save_flags(flags);
4531 cli();
4532
4533 aic7xxx_abort_scb(p, scb);
4534
4535 restore_flags(flags);
4536 return (0);
4537 }4538
4539 /*+F*************************************************************************4540 * Function:4541 * aic7xxx_reset4542 *4543 * Description:4544 * Resetting the bus always succeeds - is has to, otherwise the4545 * kernel will panic! Try a surgical technique - sending a BUS4546 * DEVICE RESET message - on the offending target before pulling4547 * the SCSI bus reset line.4548 *-F*************************************************************************/4549 int4550 aic7xxx_reset(Scsi_Cmnd *cmd)
/* */4551 {4552 return (aic7xxx_abort(cmd));
4553 }4554
4555 /*+F*************************************************************************4556 * Function:4557 * aic7xxx_biosparam4558 *4559 * Description:4560 * Return the disk geometry for the given SCSI device.4561 *-F*************************************************************************/4562 int4563 aic7xxx_biosparam(Disk *disk, kdev_tdev, intgeom[])
/* */4564 {4565 intheads, sectors, cylinders;
4566 structaic7xxx_host *p;
4567
4568 p = (structaic7xxx_host *) disk->device->host->hostdata;
4569
4570 /*4571 * XXX - if I could portably find the card's configuration4572 * information, then this could be autodetected instead4573 * of left to a boot-time switch.4574 */4575 heads = 64;
4576 sectors = 32;
4577 cylinders = disk->capacity / (heads * sectors);
4578
4579 if (p->extended && cylinders > 1024)
4580 {4581 heads = 255;
4582 sectors = 63;
4583 cylinders = disk->capacity / (255 * 63);
4584 }4585
4586 geom[0] = heads;
4587 geom[1] = sectors;
4588 geom[2] = cylinders;
4589
4590 return (0);
4591 }4592
4593 #include "aic7xxx_proc.c"
4594
4595 #ifdefMODULE4596 /* Eventually this will go into an include file, but this will be later */4597 Scsi_Host_Templatedriver_template = AIC7XXX;
4598
4599 #include "scsi_module.c"
4600 #endif4601
4602 /*4603 * Overrides for Emacs so that we almost follow Linus's tabbing style.4604 * Emacs will notice this stuff at the end of the file and automatically4605 * adjust the settings for this buffer only. This must remain at the end4606 * of the file.4607 * ---------------------------------------------------------------------------4608 * Local variables:4609 * c-indent-level: 24610 * c-brace-imaginary-offset: 04611 * c-brace-offset: -24612 * c-argdecl-indent: 24613 * c-label-offset: -24614 * c-continued-statement-offset: 24615 * c-continued-brace-offset: 04616 * indent-tabs-mode: nil4617 * tab-width: 84618 * End:4619 */