This source file includes following definitions.
- pci_lookup_dev
- pci_strbioserr
- pci_strclass
- pci_strvendor
- pci_strdev
- burst_bridge
- sprint_dev_config
- get_pci_list
- pci_malloc
- scan_bus
- pci_init
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8
9 #include <linux/config.h>
10 #include <linux/ptrace.h>
11 #include <linux/types.h>
12 #include <linux/kernel.h>
13 #include <linux/bios32.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16
17 #include <asm/page.h>
18
19 struct pci_bus pci_root;
20 struct pci_dev *pci_devices = 0;
21
22
23
24
25
26
27
28
29
30
31
32 #define DEVICE(vid,did,name) \
33 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), 0xff}
34
35 #define BRIDGE(vid,did,name,bridge) \
36 {PCI_VENDOR_ID_##vid, PCI_DEVICE_ID_##did, (name), (bridge)}
37
38
39
40
41
42
43 struct pci_dev_info dev_info[] = {
44 DEVICE( NCR, NCR_53C810, "53c810"),
45 DEVICE( NCR, NCR_53C820, "53c820"),
46 DEVICE( NCR, NCR_53C825, "53c825"),
47 DEVICE( NCR, NCR_53C815, "53c815"),
48 DEVICE( ATI, ATI_68800, "68800AX"),
49 DEVICE( ATI, ATI_215CT222, "215CT222"),
50 DEVICE( ATI, ATI_210888CX, "210888CX"),
51 DEVICE( ATI, ATI_210888GX, "210888GX"),
52 DEVICE( VLSI, VLSI_82C592, "82C592-FC1"),
53 DEVICE( VLSI, VLSI_82C593, "82C593-FC1"),
54 DEVICE( ADL, ADL_2301, "2301"),
55 DEVICE( NS, NS_87410, "87410"),
56 DEVICE( TSENG, TSENG_W32P_2, "ET4000W32P"),
57 DEVICE( TSENG, TSENG_W32P_b, "ET4000W32P rev B"),
58 DEVICE( TSENG, TSENG_W32P_c, "ET4000W32P rev C"),
59 DEVICE( TSENG, TSENG_W32P_d, "ET4000W32P rev D"),
60 DEVICE( WEITEK, WEITEK_P9000, "P9000"),
61 DEVICE( WEITEK, WEITEK_P9100, "P9100"),
62 BRIDGE( DEC, DEC_BRD, "DC21050", 0x00),
63 DEVICE( DEC, DEC_TULIP, "DC21040"),
64 DEVICE( DEC, DEC_TGA, "DC21030"),
65 DEVICE( DEC, DEC_TULIP_FAST, "DC21140"),
66 DEVICE( DEC, DEC_FDDI, "DEFPA"),
67 DEVICE( DEC, DEC_TULIP_PLUS, "DC21041"),
68 DEVICE( CIRRUS, CIRRUS_5430, "GD 5430"),
69 DEVICE( CIRRUS, CIRRUS_5434_4, "GD 5434"),
70 DEVICE( CIRRUS, CIRRUS_5434_8, "GD 5434"),
71 DEVICE( CIRRUS, CIRRUS_6729, "CL 6729"),
72 DEVICE( CIRRUS, CIRRUS_7542, "CL 7542"),
73 DEVICE( AMD, AMD_LANCE, "79C970"),
74 DEVICE( AMD, AMD_SCSI, "53C974"),
75 DEVICE( TRIDENT, TRIDENT_9420, "TG 9420"),
76 DEVICE( TRIDENT, TRIDENT_9440, "TG 9440"),
77 DEVICE( TRIDENT, TRIDENT_9660, "TG 9660"),
78 DEVICE( AI, AI_M1435, "M1435"),
79 DEVICE( MATROX, MATROX_MGA_2, "Atlas PX2085"),
80 DEVICE( MATROX, MATROX_MIL ,"Millenium"),
81 DEVICE( MATROX, MATROX_MGA_IMP, "MGA Impression"),
82 DEVICE( CT, CT_65545, "65545"),
83 DEVICE( FD, FD_36C70, "TMC-18C30"),
84 DEVICE( SI, SI_503, "85C503"),
85 DEVICE( SI, SI_501, "85C501"),
86 DEVICE( SI, SI_496, "85C496"),
87 DEVICE( SI, SI_601, "85C601"),
88 DEVICE( SI, SI_5511, "85C5511"),
89 DEVICE( SI, SI_5513, "85C5513"),
90 DEVICE( HP, HP_J2585A, "J2585A"),
91 #if 0
92 DEVICE( SMC, SMC_37C665, "FDC 37C665"),
93 DEVICE( SMC, SMC_37C922, "FDC 37C922"),
94 #else
95 DEVICE( PCTECH, PCTECH_RZ1000, "RZ1000 (buggy)"),
96 #endif
97 DEVICE( DPT, DPT, "SmartCache/Raid"),
98 DEVICE( OPTI, OPTI_82C557, "82C557"),
99 DEVICE( OPTI, OPTI_82C558, "82C558"),
100 DEVICE( OPTI, OPTI_82C621, "82C621"),
101 DEVICE( OPTI, OPTI_82C822, "82C822"),
102 DEVICE( BUSLOGIC, BUSLOGIC_946C_2,"946C"),
103 DEVICE( BUSLOGIC, BUSLOGIC_946C, "946C"),
104 DEVICE( PROMISE, PROMISE_5300, "DC5030"),
105 DEVICE( N9, N9_I128, "Imagine 128"),
106 DEVICE( UMC, UMC_UM8673F, "UM8673F"),
107 BRIDGE( UMC, UMC_UM8891A, "UM8891A", 0x01),
108 DEVICE( UMC, UMC_UM8886A, "UM8886A"),
109 BRIDGE( UMC, UMC_UM8881F, "UM8881F", 0x02),
110 DEVICE( UMC, UMC_UM8886F, "UM8886F"),
111 DEVICE( UMC, UMC_UM9017F, "UM9017F"),
112 DEVICE( X, X_AGX016, "ITT AGX016"),
113 DEVICE( QLOGIC, QLOGIC_ISP1020, "ISP1020"),
114 DEVICE( QLOGIC, QLOGIC_ISP1022, "ISP1022"),
115 DEVICE( LEADTEK, LEADTEK_805, "S3 805"),
116 DEVICE( CONTAQ, CONTAQ_82C599, "82C599"),
117 DEVICE( CMD, CMD_640, "640 (buggy)"),
118 DEVICE( CMD, CMD_646, "646"),
119 DEVICE( VISION, VISION_QD8500, "QD-8500"),
120 DEVICE( VISION, VISION_QD8580, "QD-8580"),
121 DEVICE( WINBOND, WINBOND_83769, "W83769F"),
122 DEVICE( 3COM, 3COM_3C590, "3C590 10bT"),
123 DEVICE( 3COM, 3COM_3C595TX, "3C595 100bTX"),
124 DEVICE( 3COM, 3COM_3C595T4, "3C595 100bT4"),
125 DEVICE( 3COM, 3COM_3C595MII, "3C595 100b-MII"),
126 DEVICE( AL, AL_M1445, "M1445"),
127 DEVICE( AL, AL_M1449, "M1449"),
128 DEVICE( AL, AL_M1451, "M1451"),
129 DEVICE( AL, AL_M1461, "M1461"),
130 DEVICE( AL, AL_M4803, "M4803"),
131 DEVICE( IMS, IMS_8849, "8849"),
132 DEVICE( REALTEK, REALTEK_8029, "8029"),
133 DEVICE( VIA, VIA_82C505, "VT 82C505"),
134 DEVICE( VIA, VIA_82C561, "VT 82C561"),
135 DEVICE( VIA, VIA_82C576, "VT 82C576 3V"),
136 DEVICE( VORTEX, VORTEX_GDT, "GDT 6000b"),
137 DEVICE( EF, EF_ATM, "155P-MF1"),
138 DEVICE( IMAGINGTECH, IMAGINGTECH_ICPCI, "MVC IC-PCI"),
139 DEVICE( PLX, PLX_9060, "PCI9060 i960 bridge"),
140 DEVICE( ALLIANCE, ALLIANCE_PROVIDEO, "Provideo"),
141 DEVICE( MUTECH, MUTECH_MV1000, "MV-1000"),
142 DEVICE( ZEINET, ZEINET_1221, "1221"),
143 DEVICE( CYCLADES, CYCLADES_Y, "Cyclome-Y"),
144 DEVICE( SYMPHONY, SYMPHONY_101, "82C101"),
145 DEVICE( TEKRAM, TEKRAM_DC290, "DC-290"),
146 DEVICE( AVANCE, AVANCE_2302, "ALG-2302"),
147 DEVICE( S3, S3_811, "Trio32/Trio64"),
148 DEVICE( S3, S3_868, "Vision 868"),
149 DEVICE( S3, S3_928, "Vision 928-P"),
150 DEVICE( S3, S3_864_1, "Vision 864-P"),
151 DEVICE( S3, S3_864_2, "Vision 864-P"),
152 DEVICE( S3, S3_964_1, "Vision 964-P"),
153 DEVICE( S3, S3_964_2, "Vision 964-P"),
154 DEVICE( S3, S3_968, "Vision 968"),
155 DEVICE( INTEL, INTEL_82375, "82375EB"),
156 BRIDGE( INTEL, INTEL_82424, "82424ZX Saturn", 0x00),
157 DEVICE( INTEL, INTEL_82378, "82378IB"),
158 DEVICE( INTEL, INTEL_82430, "82430ZX Aries"),
159 BRIDGE( INTEL, INTEL_82434, "82434LX Mercury/Neptune", 0x00),
160 DEVICE( INTEL, INTEL_7116, "SAA7116"),
161 DEVICE( INTEL, INTEL_82596, "82596"),
162 DEVICE( INTEL, INTEL_82865, "82865"),
163 DEVICE( INTEL, INTEL_82437, "82437"),
164 DEVICE( INTEL, INTEL_82371_0, "82371 Triton PIIX"),
165 DEVICE( INTEL, INTEL_82371_1, "82371 Triton PIIX"),
166 DEVICE( INTEL, INTEL_P6, "Experimental P6 bridge"),
167 DEVICE( ADAPTEC, ADAPTEC_7850, "AIC-7850"),
168 DEVICE( ADAPTEC, ADAPTEC_7870, "AIC-7870"),
169 DEVICE( ADAPTEC, ADAPTEC_7871, "AIC-7871"),
170 DEVICE( ADAPTEC, ADAPTEC_7872, "AIC-7872"),
171 DEVICE( ADAPTEC, ADAPTEC_7880, "AIC-7880U"),
172 DEVICE( ADAPTEC, ADAPTEC_7881, "AIC-7881U"),
173 DEVICE( ADAPTEC, ADAPTEC_7882, "AIC-7882U"),
174 DEVICE( ATRONICS, ATRONICS_2015, "IDE-2015PL"),
175 DEVICE( HER, HER_STING, "Stingray"),
176 DEVICE( HER, HER_STINGARK, "Stingray ARK 2000PV")
177 };
178
179
180 #ifdef CONFIG_PCI_OPTIMIZE
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197 struct optimization_type {
198 const char *type;
199 const char *off;
200 const char *on;
201 } bridge_optimization[] = {
202 {"Cache L2", "write trough", "write back"},
203 {"CPU-PCI posted write", "off", "on"},
204 {"CPU-Memory posted write", "off", "on"},
205 {"PCI-Memory posted write", "off", "on"},
206 {"PCI burst", "off", "on"}
207 };
208
209 #define NUM_OPTIMIZATIONS \
210 (sizeof(bridge_optimization) / sizeof(bridge_optimization[0]))
211
212 struct bridge_mapping_type {
213 unsigned char addr;
214 unsigned char mask;
215 unsigned char value;
216 } bridge_mapping[] = {
217
218
219
220
221
222
223
224 {0x0 ,0x02 ,0x02 },
225 {0x53 ,0x02 ,0x02 },
226 {0x53 ,0x01 ,0x01 },
227 {0x54 ,0x01 ,0x01 },
228 {0x54 ,0x02 ,0x02 },
229
230
231
232
233
234 {0x50 ,0x10 ,0x00 },
235 {0x51 ,0x40 ,0x40 },
236 {0x0 ,0x0 ,0x0 },
237 {0x0 ,0x0 ,0x0 },
238 {0x0 ,0x0 ,0x0 },
239
240
241
242
243
244
245 {0x0 ,0x1 ,0x1 },
246 {0x0 ,0x2 ,0x0 },
247 {0x0 ,0x0 ,0x0 },
248 {0x0 ,0x0 ,0x0 },
249 {0x0 ,0x0 ,0x0 }
250 };
251
252 #endif
253
254
255
256
257
258 struct pci_dev_info *pci_lookup_dev(unsigned int vendor, unsigned int dev)
259 {
260 int min = 0,
261 max = sizeof(dev_info)/sizeof(dev_info[0]) - 1;
262
263 for ( ; ; )
264 {
265 int i = (min + max) >> 1;
266 long order;
267
268 order = dev_info[i].vendor - (long) vendor;
269 if (!order)
270 order = dev_info[i].device - (long) dev;
271
272 if (order < 0)
273 {
274 min = i + 1;
275 if ( min > max )
276 return 0;
277 continue;
278 }
279
280 if (order > 0)
281 {
282 max = i - 1;
283 if ( min > max )
284 return 0;
285 continue;
286 }
287
288 return & dev_info[ i ];
289 }
290 }
291
292
293 const char *pci_strbioserr (int error)
294 {
295 switch (error) {
296 case PCIBIOS_SUCCESSFUL: return "SUCCESSFUL";
297 case PCIBIOS_FUNC_NOT_SUPPORTED: return "FUNC_NOT_SUPPORTED";
298 case PCIBIOS_BAD_VENDOR_ID: return "SUCCESSFUL";
299 case PCIBIOS_DEVICE_NOT_FOUND: return "DEVICE_NOT_FOUND";
300 case PCIBIOS_BAD_REGISTER_NUMBER: return "BAD_REGISTER_NUMBER";
301 case PCIBIOS_SET_FAILED: return "SET_FAILED";
302 case PCIBIOS_BUFFER_TOO_SMALL: return "BUFFER_TOO_SMALL";
303 default: return "Unknown error status";
304 }
305 }
306
307
308 const char *pci_strclass (unsigned int class)
309 {
310 switch (class >> 8) {
311 case PCI_CLASS_NOT_DEFINED: return "Non-VGA device";
312 case PCI_CLASS_NOT_DEFINED_VGA: return "VGA compatible device";
313
314 case PCI_CLASS_STORAGE_SCSI: return "SCSI storage controller";
315 case PCI_CLASS_STORAGE_IDE: return "IDE interface";
316 case PCI_CLASS_STORAGE_FLOPPY: return "Floppy disk controller";
317 case PCI_CLASS_STORAGE_IPI: return "IPI bus controller";
318 case PCI_CLASS_STORAGE_RAID: return "RAID bus controller";
319 case PCI_CLASS_STORAGE_OTHER: return "Unknown mass storage controller";
320
321 case PCI_CLASS_NETWORK_ETHERNET: return "Ethernet controller";
322 case PCI_CLASS_NETWORK_TOKEN_RING: return "Token ring network controller";
323 case PCI_CLASS_NETWORK_FDDI: return "FDDI network controller";
324 case PCI_CLASS_NETWORK_ATM: return "ATM network controller";
325 case PCI_CLASS_NETWORK_OTHER: return "Network controller";
326
327 case PCI_CLASS_DISPLAY_VGA: return "VGA compatible controller";
328 case PCI_CLASS_DISPLAY_XGA: return "XGA compatible controller";
329 case PCI_CLASS_DISPLAY_OTHER: return "Display controller";
330
331 case PCI_CLASS_MULTIMEDIA_VIDEO: return "Multimedia video controller";
332 case PCI_CLASS_MULTIMEDIA_AUDIO: return "Multimedia audio controller";
333 case PCI_CLASS_MULTIMEDIA_OTHER: return "Multimedia controller";
334
335 case PCI_CLASS_MEMORY_RAM: return "RAM memory";
336 case PCI_CLASS_MEMORY_FLASH: return "FLASH memory";
337 case PCI_CLASS_MEMORY_OTHER: return "Memory";
338
339 case PCI_CLASS_BRIDGE_HOST: return "Host bridge";
340 case PCI_CLASS_BRIDGE_ISA: return "ISA bridge";
341 case PCI_CLASS_BRIDGE_EISA: return "EISA bridge";
342 case PCI_CLASS_BRIDGE_MC: return "MicroChannel bridge";
343 case PCI_CLASS_BRIDGE_PCI: return "PCI bridge";
344 case PCI_CLASS_BRIDGE_PCMCIA: return "PCMCIA bridge";
345 case PCI_CLASS_BRIDGE_NUBUS: return "NuBus bridge";
346 case PCI_CLASS_BRIDGE_CARDBUS: return "CardBus bridge";
347 case PCI_CLASS_BRIDGE_OTHER: return "Bridge";
348
349 case PCI_CLASS_COMMUNICATION_SERIAL: return "Serial controller";
350 case PCI_CLASS_COMMUNICATION_PARALLEL: return "Parallel controller";
351 case PCI_CLASS_COMMUNICATION_OTHER: return "Communication controller";
352
353 case PCI_CLASS_SYSTEM_PIC: return "PIC";
354 case PCI_CLASS_SYSTEM_DMA: return "DMA controller";
355 case PCI_CLASS_SYSTEM_TIMER: return "Timer";
356 case PCI_CLASS_SYSTEM_RTC: return "RTC";
357 case PCI_CLASS_SYSTEM_OTHER: return "System peripheral";
358
359 case PCI_CLASS_INPUT_KEYBOARD: return "Keyboard controller";
360 case PCI_CLASS_INPUT_PEN: return "Digitizer Pen";
361 case PCI_CLASS_INPUT_MOUSE: return "Mouse controller";
362 case PCI_CLASS_INPUT_OTHER: return "Input device controller";
363
364 case PCI_CLASS_DOCKING_GENERIC: return "Generic Docking Station";
365 case PCI_CLASS_DOCKING_OTHER: return "Docking Station";
366
367 case PCI_CLASS_PROCESSOR_386: return "386";
368 case PCI_CLASS_PROCESSOR_486: return "486";
369 case PCI_CLASS_PROCESSOR_PENTIUM: return "Pentium";
370 case PCI_CLASS_PROCESSOR_ALPHA: return "Alpha";
371 case PCI_CLASS_PROCESSOR_POWERPC: return "Power PC";
372 case PCI_CLASS_PROCESSOR_CO: return "Co-processor";
373
374 case PCI_CLASS_SERIAL_FIREWIRE: return "FireWire (IEEE 1394)";
375 case PCI_CLASS_SERIAL_ACCESS: return "ACCESS Bus";
376 case PCI_CLASS_SERIAL_SSA: return "SSA";
377 case PCI_CLASS_SERIAL_FIBER: return "Fiber Channel";
378
379 default: return "Unknown class";
380 }
381 }
382
383
384 const char *pci_strvendor(unsigned int vendor)
385 {
386 switch (vendor) {
387 case PCI_VENDOR_ID_NCR: return "NCR";
388 case PCI_VENDOR_ID_ADAPTEC: return "Adaptec";
389 case PCI_VENDOR_ID_DPT: return "DPT";
390 case PCI_VENDOR_ID_S3: return "S3 Inc.";
391 case PCI_VENDOR_ID_OPTI: return "OPTI";
392 case PCI_VENDOR_ID_UMC: return "UMC";
393 case PCI_VENDOR_ID_DEC: return "DEC";
394 case PCI_VENDOR_ID_MATROX: return "Matrox";
395 case PCI_VENDOR_ID_INTEL: return "Intel";
396 #if 0
397 case PCI_VENDOR_ID_SMC: return "SMC";
398 #else
399 case PCI_VENDOR_ID_PCTECH: return "PCTECH";
400 #endif
401 case PCI_VENDOR_ID_ATI: return "ATI";
402 case PCI_VENDOR_ID_WEITEK: return "Weitek";
403 case PCI_VENDOR_ID_CIRRUS: return "Cirrus Logic";
404 case PCI_VENDOR_ID_BUSLOGIC: return "BusLogic";
405 case PCI_VENDOR_ID_N9: return "Number Nine";
406 case PCI_VENDOR_ID_AI: return "Acer Incorporated";
407 case PCI_VENDOR_ID_AL: return "Acer Labs";
408 case PCI_VENDOR_ID_TSENG: return "Tseng'Lab";
409 case PCI_VENDOR_ID_CMD: return "CMD";
410 case PCI_VENDOR_ID_VISION: return "Vision";
411 case PCI_VENDOR_ID_AMD: return "AMD";
412 case PCI_VENDOR_ID_VLSI: return "VLSI";
413 case PCI_VENDOR_ID_ADL: return "Advance Logic";
414 case PCI_VENDOR_ID_SYMPHONY: return "Symphony";
415 case PCI_VENDOR_ID_TRIDENT: return "Trident";
416 case PCI_VENDOR_ID_CONTAQ: return "Contaq";
417 case PCI_VENDOR_ID_NS: return "NS";
418 case PCI_VENDOR_ID_VIA: return "VIA Technologies";
419 case PCI_VENDOR_ID_SI: return "Silicon Integrated Systems";
420 case PCI_VENDOR_ID_LEADTEK: return "Leadtek Research";
421 case PCI_VENDOR_ID_IMS: return "IMS";
422 case PCI_VENDOR_ID_ZEINET: return "ZeiNet";
423 case PCI_VENDOR_ID_EF: return "Efficient Networks";
424 case PCI_VENDOR_ID_HER: return "Hercules";
425 case PCI_VENDOR_ID_ATRONICS: return "Atronics";
426 case PCI_VENDOR_ID_CT: return "Chips & Technologies";
427 case PCI_VENDOR_ID_FD: return "Future Domain";
428 case PCI_VENDOR_ID_WINBOND: return "Winbond";
429 case PCI_VENDOR_ID_3COM: return "3Com";
430 case PCI_VENDOR_ID_PROMISE: return "Promise Technology";
431 case PCI_VENDOR_ID_QLOGIC: return "Q Logic";
432 case PCI_VENDOR_ID_X: return "X TECHNOLOGY";
433 case PCI_VENDOR_ID_ACC: return "ACC MICROELECTRONICS";
434 case PCI_VENDOR_ID_VORTEX: return "VORTEX";
435 case PCI_VENDOR_ID_HP: return "Hewlett Packard";
436 case PCI_VENDOR_ID_IMAGINGTECH: return "Imaging Technology";
437 case PCI_VENDOR_ID_CYCLADES: return "Cyclades";
438 case PCI_VENDOR_ID_OLICOM: return "Olicom";
439 case PCI_VENDOR_ID_IBM: return "IBM";
440 case PCI_VENDOR_ID_AVANCE: return "Avance";
441 case PCI_VENDOR_ID_ALLIANCE: return "Alliance";
442 default: return "Unknown vendor";
443 }
444 }
445
446
447 const char *pci_strdev(unsigned int vendor, unsigned int device)
448 {
449 struct pci_dev_info *info;
450
451 info = pci_lookup_dev(vendor, device);
452 return info ? info->name : "Unknown device";
453 }
454
455
456
457
458
459
460 static void burst_bridge(unsigned char bus, unsigned char devfn,
461 unsigned char pos, int turn_on)
462 {
463 #ifdef CONFIG_PCI_OPTIMIZE
464 struct bridge_mapping_type *bmap;
465 unsigned char val;
466 int i;
467
468 pos *= NUM_OPTIMIZATIONS;
469 printk("PCI bridge optimization.\n");
470 for (i = 0; i < NUM_OPTIMIZATIONS; i++) {
471 printk(" %s: ", bridge_optimization[i].type);
472 bmap = &bridge_mapping[pos + i];
473 if (!bmap->addr) {
474 printk("Not supported.");
475 } else {
476 pcibios_read_config_byte(bus, devfn, bmap->addr, &val);
477 if ((val & bmap->mask) == bmap->value) {
478 printk("%s.", bridge_optimization[i].on);
479 if (!turn_on) {
480 pcibios_write_config_byte(bus, devfn,
481 bmap->addr,
482 (val | bmap->mask)
483 - bmap->value);
484 printk("Changed! Now %s.", bridge_optimization[i].off);
485 }
486 } else {
487 printk("%s.", bridge_optimization[i].off);
488 if (turn_on) {
489 pcibios_write_config_byte(bus, devfn,
490 bmap->addr,
491 (val & (0xff - bmap->mask))
492 + bmap->value);
493 printk("Changed! Now %s.", bridge_optimization[i].on);
494 }
495 }
496 }
497 printk("\n");
498 }
499 #endif
500 }
501
502
503
504
505
506
507
508
509 static int sprint_dev_config(struct pci_dev *dev, char *buf, int size)
510 {
511 unsigned long base;
512 unsigned int l, class_rev, bus, devfn;
513 unsigned short vendor, device, status;
514 unsigned char bist, latency, min_gnt, max_lat;
515 int reg, len = 0;
516 const char *str;
517
518 bus = dev->bus->number;
519 devfn = dev->devfn;
520
521 pcibios_read_config_dword(bus, devfn, PCI_CLASS_REVISION, &class_rev);
522 pcibios_read_config_word (bus, devfn, PCI_VENDOR_ID, &vendor);
523 pcibios_read_config_word (bus, devfn, PCI_DEVICE_ID, &device);
524 pcibios_read_config_word (bus, devfn, PCI_STATUS, &status);
525 pcibios_read_config_byte (bus, devfn, PCI_BIST, &bist);
526 pcibios_read_config_byte (bus, devfn, PCI_LATENCY_TIMER, &latency);
527 pcibios_read_config_byte (bus, devfn, PCI_MIN_GNT, &min_gnt);
528 pcibios_read_config_byte (bus, devfn, PCI_MAX_LAT, &max_lat);
529 if (len + 80 > size) {
530 return -1;
531 }
532 len += sprintf(buf + len, " Bus %2d, device %3d, function %2d:\n",
533 bus, PCI_SLOT(devfn), PCI_FUNC(devfn));
534
535 if (len + 80 > size) {
536 return -1;
537 }
538 len += sprintf(buf + len, " %s: %s %s (rev %d).\n ",
539 pci_strclass(class_rev >> 8), pci_strvendor(vendor),
540 pci_strdev(vendor, device), class_rev & 0xff);
541
542 if (!pci_lookup_dev(vendor, device)) {
543 len += sprintf(buf + len,
544 "Vendor id=%x. Device id=%x.\n ",
545 vendor, device);
546 }
547
548 str = 0;
549 switch (status & PCI_STATUS_DEVSEL_MASK) {
550 case PCI_STATUS_DEVSEL_FAST: str = "Fast devsel. "; break;
551 case PCI_STATUS_DEVSEL_MEDIUM: str = "Medium devsel. "; break;
552 case PCI_STATUS_DEVSEL_SLOW: str = "Slow devsel. "; break;
553 }
554 if (len + strlen(str) > size) {
555 return -1;
556 }
557 len += sprintf(buf + len, str);
558
559 if (status & PCI_STATUS_FAST_BACK) {
560 # define fast_b2b_capable "Fast back-to-back capable. "
561 if (len + strlen(fast_b2b_capable) > size) {
562 return -1;
563 }
564 len += sprintf(buf + len, fast_b2b_capable);
565 # undef fast_b2b_capable
566 }
567
568 if (bist & PCI_BIST_CAPABLE) {
569 # define BIST_capable "BIST capable. "
570 if (len + strlen(BIST_capable) > size) {
571 return -1;
572 }
573 len += sprintf(buf + len, BIST_capable);
574 # undef BIST_capable
575 }
576
577 if (dev->irq) {
578 if (len + 40 > size) {
579 return -1;
580 }
581 len += sprintf(buf + len, "IRQ %d. ", dev->irq);
582 }
583
584 if (dev->master) {
585 if (len + 80 > size) {
586 return -1;
587 }
588 len += sprintf(buf + len, "Master Capable. ");
589 if (latency)
590 len += sprintf(buf + len, "Latency=%d. ", latency);
591 else
592 len += sprintf(buf + len, "No bursts. ");
593 if (min_gnt)
594 len += sprintf(buf + len, "Min Gnt=%d.", min_gnt);
595 if (max_lat)
596 len += sprintf(buf + len, "Max Lat=%d.", max_lat);
597 }
598
599 for (reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4) {
600 if (len + 40 > size) {
601 return -1;
602 }
603 pcibios_read_config_dword(bus, devfn, reg, &l);
604 base = l;
605 if (!base) {
606 continue;
607 }
608
609 if (base & PCI_BASE_ADDRESS_SPACE_IO) {
610 len += sprintf(buf + len,
611 "\n I/O at 0x%lx.",
612 base & PCI_BASE_ADDRESS_IO_MASK);
613 } else {
614 const char *pref, *type = "unknown";
615
616 if (base & PCI_BASE_ADDRESS_MEM_PREFETCH) {
617 pref = "P";
618 } else {
619 pref = "Non-p";
620 }
621 switch (base & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
622 case PCI_BASE_ADDRESS_MEM_TYPE_32:
623 type = "32 bit"; break;
624 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
625 type = "20 bit"; break;
626 case PCI_BASE_ADDRESS_MEM_TYPE_64:
627 type = "64 bit";
628
629 reg += 4;
630 pcibios_read_config_dword(bus, devfn, reg, &l);
631 base |= ((u64) l) << 32;
632 break;
633 }
634 len += sprintf(buf + len,
635 "\n %srefetchable %s memory at "
636 "0x%lx.", pref, type,
637 base & PCI_BASE_ADDRESS_MEM_MASK);
638 }
639 }
640
641 len += sprintf(buf + len, "\n");
642 return len;
643 }
644
645
646
647
648
649
650 int get_pci_list(char *buf)
651 {
652 int nprinted, len, size;
653 struct pci_dev *dev;
654 # define MSG "\nwarning: page-size limit reached!\n"
655
656
657 size = PAGE_SIZE - (strlen(MSG) + 1);
658 len = sprintf(buf, "PCI devices found:\n");
659
660 for (dev = pci_devices; dev; dev = dev->next) {
661 nprinted = sprint_dev_config(dev, buf + len, size - len);
662 if (nprinted < 0) {
663 return len + sprintf(buf + len, MSG);
664 }
665 len += nprinted;
666 }
667 return len;
668 }
669
670
671
672
673
674
675 static void *pci_malloc(long size, unsigned long *mem_startp)
676 {
677 void *mem;
678
679 #ifdef DEBUG
680 printk("...pci_malloc(size=%ld,mem=%p)", size, *mem_startp);
681 #endif
682 mem = (void*) *mem_startp;
683 *mem_startp += (size + sizeof(void*) - 1) & ~(sizeof(void*) - 1);
684 memset(mem, 0, size);
685 return mem;
686 }
687
688
689 static unsigned int scan_bus(struct pci_bus *bus, unsigned long *mem_startp)
690 {
691 unsigned int devfn, l, max;
692 unsigned char cmd, tmp, hdr_type = 0;
693 struct pci_dev_info *info;
694 struct pci_dev *dev;
695 struct pci_bus *child;
696
697 #ifdef DEBUG
698 printk("...scan_bus(busno=%d,mem=%p)\n", bus->number, *mem_startp);
699 #endif
700
701 max = bus->secondary;
702 for (devfn = 0; devfn < 0xff; ++devfn) {
703 if (PCI_FUNC(devfn) == 0) {
704 pcibios_read_config_byte(bus->number, devfn,
705 PCI_HEADER_TYPE, &hdr_type);
706 } else if (!(hdr_type & 0x80)) {
707
708 continue;
709 }
710
711 pcibios_read_config_dword(bus->number, devfn, PCI_VENDOR_ID,
712 &l);
713
714 if (l == 0xffffffff || l == 0x00000000) {
715 hdr_type = 0;
716 continue;
717 }
718
719 dev = pci_malloc(sizeof(*dev), mem_startp);
720 dev->bus = bus;
721
722
723
724
725
726 dev->next = pci_devices;
727 pci_devices = dev;
728
729 dev->devfn = devfn;
730 dev->vendor = l & 0xffff;
731 dev->device = (l >> 16) & 0xffff;
732
733
734
735
736
737
738 info = pci_lookup_dev(dev->vendor, dev->device);
739 if (!info) {
740 printk("Warning : Unknown PCI device (%x:%x). Please read include/linux/pci.h \n",
741 dev->vendor, dev->device);
742 } else {
743
744 if (info->bridge_type != 0xff) {
745 burst_bridge(bus->number, devfn,
746 info->bridge_type, 1);
747 }
748 }
749
750
751 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
752 &cmd);
753 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
754 cmd | PCI_COMMAND_MASTER);
755 pcibios_read_config_byte(bus->number, devfn, PCI_COMMAND,
756 &tmp);
757 dev->master = ((tmp & PCI_COMMAND_MASTER) != 0);
758 pcibios_write_config_byte(bus->number, devfn, PCI_COMMAND,
759 cmd);
760
761
762 pcibios_read_config_byte(bus->number, devfn,
763 PCI_INTERRUPT_LINE, &dev->irq);
764
765
766 pcibios_read_config_dword(bus->number, devfn,
767 PCI_CLASS_REVISION, &l);
768 l = l >> 8;
769 dev->class = l;
770
771
772
773
774 dev->sibling = bus->devices;
775 bus->devices = dev;
776
777 if (dev->class >> 8 == PCI_CLASS_BRIDGE_PCI) {
778 unsigned int buses;
779 unsigned short cr;
780
781
782
783
784 child = pci_malloc(sizeof(*child), mem_startp);
785 child->next = bus->children;
786 bus->children = child;
787 child->self = dev;
788 child->parent = bus;
789
790
791
792
793
794 child->number = child->secondary = ++max;
795 child->primary = bus->secondary;
796 child->subordinate = 0xff;
797
798
799
800
801 pcibios_read_config_word(bus->number, devfn,
802 PCI_COMMAND, &cr);
803 pcibios_write_config_word(bus->number, devfn,
804 PCI_COMMAND, 0x0000);
805 pcibios_write_config_word(bus->number, devfn,
806 PCI_STATUS, 0xffff);
807
808
809
810 pcibios_read_config_dword(bus->number, devfn, 0x18,
811 &buses);
812 buses &= 0xff000000;
813 buses |= (((unsigned int)(child->primary) << 0) |
814 ((unsigned int)(child->secondary) << 8) |
815 ((unsigned int)(child->subordinate) << 16));
816 pcibios_write_config_dword(bus->number, devfn, 0x18,
817 buses);
818
819
820
821 max = scan_bus(child, mem_startp);
822
823
824
825
826 child->subordinate = max;
827 buses = (buses & 0xff00ffff)
828 | ((unsigned int)(child->subordinate) << 16);
829 pcibios_write_config_dword(bus->number, devfn, 0x18,
830 buses);
831 pcibios_write_config_word(bus->number, devfn,
832 PCI_COMMAND, cr);
833 }
834 }
835
836
837
838
839
840
841
842 return max;
843 }
844
845
846 unsigned long pci_init (unsigned long mem_start, unsigned long mem_end)
847 {
848 mem_start = pcibios_init(mem_start, mem_end);
849
850 if (!pcibios_present()) {
851 printk("pci_init: no BIOS32 detected\n");
852 return mem_start;
853 }
854
855 printk("Probing PCI hardware.\n");
856
857 memset(&pci_root, 0, sizeof(pci_root));
858 pci_root.subordinate = scan_bus(&pci_root, &mem_start);
859
860
861 mem_start = pcibios_fixup(mem_start, mem_end);
862
863 #ifdef DEBUG
864 {
865 int len = get_pci_list((char*)mem_start);
866 if (len) {
867 ((char *) mem_start)[len] = '\0';
868 printk("%s\n", (char *) mem_start);
869 }
870 }
871 #endif
872 return mem_start;
873 }