root/arch/i386/kernel/smp.c

/* [previous][next][first][last][top][bottom][index][help] */

DEFINITIONS

This source file includes following definitions.
  1. mpf_checksum
  2. mpc_family
  3. smp_read_mpc
  4. smp_scan_config
  5. install_trampoline
  6. smp_alloc_memory
  7. get_kernel_stack
  8. smp_store_cpu_info
  9. smp_commence
  10. smp_callin
  11. smp_boot_cpus
  12. smp_message_pass
  13. smp_invalidate
  14. smp_reschedule_irq
  15. smp_message_irq

   1 /*
   2  *      Intel MP v1.1 specification support routines for multi-pentium 
   3  *      hosts.
   4  *
   5  *      (c) 1995 Alan Cox, CymruNET Ltd  <alan@cymru.net>
   6  *      Supported by Caldera http://www.caldera.com.
   7  *      Much of the core SMP work is based on previous work by Thomas Radke, to
   8  *      whom a great many thanks are extended.
   9  *
  10  *      This code is released under the GNU public license version 2 or
  11  *      later.
  12  *
  13  *      Fixes
  14  *              Felix Koop      :       NR_CPUS used properly
  15  *              Jose Renau      :       Handle single CPU case.
  16  *              Alan Cox        :       By repeated request 8) - Total BogoMIP report.
  17  *
  18  */
  19 
  20 #include <linux/kernel.h>
  21 #include <linux/string.h>
  22 #include <linux/config.h>
  23 #include <linux/timer.h>
  24 #include <linux/sched.h>
  25 #include <linux/mm.h>
  26 #include <linux/kernel_stat.h>
  27 #include <linux/delay.h>
  28 #include <asm/i82489.h>
  29 #include <linux/smp.h>
  30 #include <asm/bitops.h>
  31 #include <asm/smp.h>
  32 
  33 extern void *vremap(unsigned long offset, unsigned long size);  /* Linus hasnt put this in the headers yet */
  34 
  35 static int smp_found_config=0;                          /* Have we found an SMP box                             */
  36 
  37 unsigned long cpu_present_map = 0;                      /* Bitmask of existing CPU's                            */
  38 int smp_num_cpus;                                       /* Total count of live CPU's                            */
  39 int smp_threads_ready=0;                                /* Set when the idlers are all forked                   */
  40 volatile unsigned long cpu_callin_map[NR_CPUS] = {0,};  /* We always use 0 the rest is ready for parallel delivery */
  41 volatile unsigned long smp_invalidate_needed;           /* Used for the invalidate map thats also checked in the spinlock */
  42 struct cpuinfo_x86 cpu_data[NR_CPUS];                   /* Per cpu bogomips and other parameters                */
  43 static unsigned int num_processors = 0;                 /* Internal processor count                             */
  44 static unsigned long io_apic_addr = 0;                  /* Address of the I/O apic (not yet used)               */
  45 unsigned char boot_cpu_id = 0;                          /* Processor that is doing the boot up                  */
  46 static unsigned char *kstack_base,*kstack_end;          /* Kernel stack list pointers                           */
  47 static int smp_activated = 0;                           /* Tripped once we need to start cross invalidating     */
  48 static volatile int smp_commenced=0;                    /* Tripped when we start scheduling                     */
  49 static unsigned char nlong=0;                           /* Apparent value for boot CPU                          */
  50 unsigned char *apic_reg=((unsigned char *)&nlong)-0x20; /* Later set to the vremap() of the APIC                */
  51 unsigned long apic_retval;                              /* Just debugging the assembler..                       */
  52 unsigned char *kernel_stacks[NR_CPUS];                  /* Kernel stack pointers for CPU's (debugging)          */
  53 
  54 static volatile unsigned char smp_cpu_in_msg[NR_CPUS];  /* True if this processor is sending an IPI             */
  55 static volatile unsigned long smp_msg_data;             /* IPI data pointer                                     */
  56 static volatile int smp_src_cpu;                        /* IPI sender processor                                 */
  57 static volatile int smp_msg_id;                         /* Message being sent                                   */
  58 
  59 volatile unsigned long kernel_flag=0;                   /* Kernel spinlock                                      */
  60 volatile unsigned char active_kernel_processor = NO_PROC_ID;    /* Processor holding kernel spinlock            */
  61 volatile unsigned long kernel_counter=0;                /* Number of times the processor holds the lock         */
  62 volatile unsigned long syscall_count=0;                 /* Number of times the processor holds the syscall lock */
  63 volatile unsigned long smp_spins=0;                     /* Count of cycles wasted to spinning                   */
  64 
  65 volatile unsigned long ipi_count;                       /* Number of IPI's delivered                            */
  66 
  67 /* 
  68  *      Checksum an MP configuration block.
  69  */
  70  
  71 static int mpf_checksum(unsigned char *mp, int len)
     /* [previous][next][first][last][top][bottom][index][help] */
  72 {
  73         int sum=0;
  74         while(len--)
  75                 sum+=*mp++;
  76         return sum&0xFF;
  77 }
  78 
  79 /*
  80  *      Processor encoding in an MP configuration block
  81  */
  82  
  83 static char *mpc_family(int family,int model)
     /* [previous][next][first][last][top][bottom][index][help] */
  84 {
  85         static char n[32];
  86         static char *model_defs[]=
  87         {
  88                 "80486DX","80486DX",
  89                 "80486SX","80486DX/2 or 80487",
  90                 "80486SL","Intel5X2(tm)",
  91                 "Unknown","Unknown",
  92                 "80486DX/4"
  93         };
  94         if(family==0x5)
  95                 return("Pentium(tm)");
  96         if(family==0x0F && model==0x0F)
  97                 return("Special controller");
  98         if(family==0x04 && model<9)
  99                 return model_defs[model];
 100         sprintf(n,"Unknown CPU [%d:%d]",family, model);
 101         return n;
 102 }
 103 
 104 /*
 105  *      Read the MPC
 106  */
 107 
 108 static int smp_read_mpc(struct mp_config_table *mpc)
     /* [previous][next][first][last][top][bottom][index][help] */
 109 {
 110         char str[16];
 111         int count=sizeof(*mpc);
 112         int apics=0;
 113         unsigned char *mpt=((unsigned char *)mpc)+count;
 114 
 115         if(memcmp(mpc->mpc_signature,MPC_SIGNATURE,4))
 116         {
 117                 printk("Bad signature [%c%c%c%c].\n",
 118                         mpc->mpc_signature[0],
 119                         mpc->mpc_signature[1],
 120                         mpc->mpc_signature[2],
 121                         mpc->mpc_signature[3]);
 122                 return 1;
 123         }
 124         if(mpf_checksum((unsigned char *)mpc,mpc->mpc_length))
 125         {
 126                 printk("Checksum error.\n");
 127                 return 1;
 128         }
 129         if(mpc->mpc_spec!=0x01)
 130         {
 131                 printk("Unsupported version (%d)\n",mpc->mpc_spec);
 132                 return 1;
 133         }
 134         memcpy(str,mpc->mpc_oem,8);
 135         str[8]=0;
 136         printk("OEM ID: %s ",str);
 137         memcpy(str,mpc->mpc_productid,12);
 138         str[12]=0;
 139         printk("Product ID: %s ",str);
 140         printk("APIC at: 0x%lX\n",mpc->mpc_lapic);
 141         
 142         /*
 143          *      Now process the configuration blocks.
 144          */
 145          
 146         while(count<mpc->mpc_length)
 147         {
 148                 switch(*mpt)
 149                 {
 150                         case MP_PROCESSOR:
 151                         {
 152                                 struct mpc_config_processor *m=
 153                                         (struct mpc_config_processor *)mpt;
 154                                 if(m->mpc_cpuflag&CPU_ENABLED)
 155                                 {
 156                                         printk("Processor #%d %s APIC version %d\n",
 157                                                 m->mpc_apicid, 
 158                                                 mpc_family((m->mpc_cpufeature&
 159                                                         CPU_FAMILY_MASK)>>8,
 160                                                         (m->mpc_cpufeature&
 161                                                                 CPU_MODEL_MASK)>>4),
 162                                                 m->mpc_apicver);
 163                                         if(m->mpc_featureflag&(1<<0))
 164                                                 printk("    Floating point unit present.\n");
 165                                         if(m->mpc_featureflag&(1<<7))
 166                                                 printk("    Machine Exception supported.\n");
 167                                         if(m->mpc_featureflag&(1<<8))
 168                                                 printk("    64 bit compare & exchange supported.\n");
 169                                         if(m->mpc_featureflag&(1<<9))
 170                                                 printk("    Internal APIC present.\n");
 171                                         if(m->mpc_cpuflag&CPU_BOOTPROCESSOR)
 172                                         {
 173                                                 printk("    Bootup CPU\n");
 174                                                 boot_cpu_id=m->mpc_apicid;
 175                                                 nlong = boot_cpu_id<<24;        /* Dummy 'self' for bootup */
 176                                         }
 177                                         else    /* Boot CPU already counted */
 178                                                 num_processors++;
 179                                                 
 180                                         if(m->mpc_apicid>NR_CPUS)
 181                                                 printk("Processor #%d unused. (Max %d processors).\n",m->mpc_apicid, NR_CPUS);
 182                                         else                                            
 183                                                 cpu_present_map|=(1<<m->mpc_apicid);
 184                                 }
 185                                 mpt+=sizeof(*m);
 186                                 count+=sizeof(*m);
 187                                 break;
 188                         }
 189                         case MP_BUS:
 190                         {
 191                                 struct mpc_config_bus *m=
 192                                         (struct mpc_config_bus *)mpt;
 193                                 memcpy(str,m->mpc_bustype,6);
 194                                 str[6]=0;
 195                                 printk("Bus #%d is %s\n",
 196                                         m->mpc_busid,
 197                                         str);
 198                                 mpt+=sizeof(*m);
 199                                 count+=sizeof(*m);
 200                                 break; 
 201                         }
 202                         case MP_IOAPIC:
 203                         {
 204                                 struct mpc_config_ioapic *m=
 205                                         (struct mpc_config_ioapic *)mpt;
 206                                 if(m->mpc_flags&MPC_APIC_USABLE)
 207                                 {
 208                                         apics++;
 209                                         printk("I/O APIC #%d Version %d at 0x%lX.\n",
 210                                                 m->mpc_apicid,m->mpc_apicver,
 211                                                 m->mpc_apicaddr);
 212                                         io_apic_addr = m->mpc_apicaddr;
 213                                 }
 214                                 mpt+=sizeof(*m);
 215                                 count+=sizeof(*m); 
 216                                 break;
 217                         }
 218                         case MP_INTSRC:
 219                         {
 220                                 struct mpc_config_intsrc *m=
 221                                         (struct mpc_config_intsrc *)mpt;
 222                                 
 223                                 mpt+=sizeof(*m);
 224                                 count+=sizeof(*m);
 225                                 break;
 226                         }
 227                         case MP_LINTSRC:
 228                         {
 229                                 struct mpc_config_intlocal *m=
 230                                         (struct mpc_config_intlocal *)mpt;
 231                                 mpt+=sizeof(*m);
 232                                 count+=sizeof(*m);
 233                                 break;
 234                         }
 235                 }
 236         }
 237         if(apics>1)
 238                 printk("Warning: Multiple APIC's not supported.\n");
 239         return num_processors;                          
 240 }
 241 
 242 /*
 243  *      Scan the memory blocks for an SMP configuration block.
 244  */
 245  
 246 void smp_scan_config(unsigned long base, unsigned long length)
     /* [previous][next][first][last][top][bottom][index][help] */
 247 {
 248         unsigned long *bp=(unsigned long *)base;
 249         struct intel_mp_floating *mpf;
 250         num_processors = 1;             /* The boot processor */
 251         
 252 /*      printk("Scan SMP from %p for %ld bytes.\n",
 253                 bp,length);*/
 254         if(sizeof(*mpf)!=16)
 255                 printk("Error: MPF size\n");
 256         
 257         while(length>0)
 258         {
 259                 if(*bp==SMP_MAGIC_IDENT)
 260                 {
 261                         mpf=(struct intel_mp_floating *)bp;
 262                         if(mpf->mpf_length==1 && 
 263                                 !mpf_checksum((unsigned char *)bp,16) &&
 264                                 mpf->mpf_specification==1)
 265                         {
 266                                 printk("Intel multiprocessing (MPv1.1) available.\n");
 267                                 if(mpf->mpf_feature2&(1<<7))
 268                                         printk("    IMCR and PIC mode supported.\n");
 269                                 smp_found_config=1;
 270                                 /*
 271                                  *      Now see if we need to read further.
 272                                  */
 273                                 if(mpf->mpf_feature1!=0)
 274                                 {
 275                                         num_processors=2;
 276                                         printk("I/O APIC at 0xFEC00000.\n");
 277                                         printk("Bus#0 is ");
 278                                 }
 279                                 switch(mpf->mpf_feature1)
 280                                 {
 281                                         case 1:
 282                                                 printk("ISA");
 283                                                 break;
 284                                         case 2:
 285                                                 printk("EISA with no IRQ8 chaining");
 286                                                 break;
 287                                         case 3:
 288                                                 printk("EISA");
 289                                                 break;
 290                                         case 4:
 291                                                 printk("MCA");
 292                                                 break;
 293                                         case 5:
 294                                                 printk("ISA\nBus#1 is PCI");
 295                                                 break;
 296                                         case 6:
 297                                                 printk("EISA\nBus #1 is PCI");
 298                                                 break;
 299                                         case 7:
 300                                                 printk("MCA\nBus #1 is PCI");
 301                                                 break;
 302                                         case 0:
 303                                                 break;
 304                                         default:
 305                                                 printk("???\nUnknown standard configuration %d\n",
 306                                                         mpf->mpf_feature1);
 307                                                 return;
 308                                 }
 309                                 /*
 310                                  *      Read the physical hardware table. If there isn't one
 311                                  *      the processors present are 0 and 1.
 312                                  */
 313                                 if(mpf->mpf_physptr)
 314                                         smp_read_mpc((void *)mpf->mpf_physptr);
 315                                 else
 316                                         cpu_present_map=3;
 317                                 printk("Processors: %d\n", num_processors);
 318                         }
 319                 }
 320                 bp+=4;
 321                 length-=16;
 322         }
 323 }
 324 
 325 /*
 326  *      Trampoline 80x86 program as an array.
 327  */
 328 
 329 static unsigned char trampoline_data[]={ 
 330 #include  "trampoline.hex"
 331 };
 332 
 333 /*
 334  *      Currently trivial. Write the real->protected mode
 335  *      bootstrap into the page concerned. The caller
 336  *      has made sure its suitably aligned.
 337  */
 338  
 339 static void install_trampoline(unsigned char *mp)
     /* [previous][next][first][last][top][bottom][index][help] */
 340 {
 341         memcpy(mp,trampoline_data,sizeof(trampoline_data));
 342 }
 343 
 344 /*
 345  *      We are called very early to get the low memory for the trampoline/kernel stacks
 346  *      This has to be done by mm/init.c to parcel us out nice low memory. We allocate
 347  *      the kernel stacks at 4K, 8K, 12K... currently (0-03FF is preserved for SMM and
 348  *      other things).
 349  */
 350  
 351 unsigned long smp_alloc_memory(unsigned long mem_base)
     /* [previous][next][first][last][top][bottom][index][help] */
 352 {
 353         int size=(num_processors-1)*PAGE_SIZE;          /* Number of stacks needed */
 354         /*
 355          *      Our stacks have to be below the 1Mb line, and mem_base on entry
 356          *      is 4K aligned.
 357          */
 358          
 359         if(mem_base+size>=0x9F000)
 360                 panic("smp_alloc_memory: Insufficient low memory for kernel stacks.\n");
 361         kstack_base=(void *)mem_base;
 362         mem_base+=size;
 363         kstack_end=(void *)mem_base;
 364         return mem_base;
 365 }
 366         
 367 /*
 368  *      Hand out stacks one at a time.
 369  */
 370  
 371 static void *get_kernel_stack(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 372 {
 373         void *stack=kstack_base;
 374         if(kstack_base>=kstack_end)
 375                 return NULL;
 376         kstack_base+=PAGE_SIZE;
 377         return stack;
 378 }
 379 
 380 
 381 /*
 382  *      The bootstrap kernel entry code has set these up. Save them for
 383  *      a given CPU
 384  */
 385  
 386 void smp_store_cpu_info(int id)
     /* [previous][next][first][last][top][bottom][index][help] */
 387 {
 388         struct cpuinfo_x86 *c=&cpu_data[id];
 389         c->hard_math=hard_math;                 /* Always assumed same currently */
 390         c->x86=x86;
 391         c->x86_model=x86_model;
 392         c->x86_mask=x86_mask;
 393         c->x86_capability=x86_capability;
 394         c->fdiv_bug=fdiv_bug;
 395         c->wp_works_ok=wp_works_ok;             /* Always assumed the same currently */
 396         c->hlt_works_ok=hlt_works_ok;
 397         c->udelay_val=loops_per_sec;
 398         strcpy(c->x86_vendor_id, x86_vendor_id);
 399 }
 400 
 401 /*
 402  *      Architecture specific routine called by the kernel just before init is
 403  *      fired off. This allows the BP to have everything in order [we hope].
 404  *      At the end of this all the AP's will hit the system scheduling and off
 405  *      we go. Each AP will load the system gdt's and jump through the kernel
 406  *      init into idle(). At this point the scheduler will one day take over 
 407  *      and give them jobs to do. smp_callin is a standard routine
 408  *      we use to track CPU's as they power up.
 409  */
 410 
 411 void smp_commence(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 412 {
 413         /*
 414          *      Lets the callin's below out of their loop.
 415          */
 416         smp_commenced=1;
 417 }
 418  
 419 void smp_callin(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 420 {
 421         int cpuid=GET_APIC_ID(apic_read(APIC_ID));
 422         unsigned long l;
 423         /*
 424          *      Activate our APIC
 425          */
 426          
 427 /*      printk("CALLIN %d\n",smp_processor_id());*/
 428         l=apic_read(APIC_SPIV);
 429         l|=(1<<8);              /* Enable */
 430         apic_write(APIC_SPIV,l);
 431         sti();
 432         /*
 433          *      Get our bogomips.
 434          */     
 435         calibrate_delay();
 436         /*
 437          *      Save our processor parameters
 438          */
 439         smp_store_cpu_info(cpuid);
 440         /*
 441          *      Allow the master to continue.
 442          */     
 443         set_bit(cpuid, &cpu_callin_map[0]);
 444         /*
 445          *      Until we are ready for SMP scheduling
 446          */
 447         load_ldt(0);
 448 /*      printk("Testing faulting...\n");
 449         *(long *)0=1;            OOPS... */
 450         local_invalidate();
 451         while(!smp_commenced);
 452         local_invalidate();
 453 /*      printk("Commenced..\n");*/
 454         
 455         /* This assumes the processor id's are consecutive 0..n-1 -  FIXME */
 456         load_TR(cpuid);
 457 /*      while(1);*/
 458 }
 459 
 460 /*
 461  *      Cycle through the processors sending pentium IPI's to boot each.
 462  */
 463  
 464 void smp_boot_cpus(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 465 {
 466         int i=0;
 467         int cpucount=0;
 468         void *stack;
 469         extern unsigned long init_user_stack[];
 470         
 471         /*
 472          *      Map the local APIC into kernel space
 473          */
 474         
 475         apic_reg = vremap(0xFEE00000,4096);
 476         
 477         
 478         if(apic_reg == NULL)
 479                 panic("Unable to map local apic.\n");
 480                 
 481         /*
 482          *      Now scan the cpu present map and fire up anything we find.
 483          */
 484          
 485          
 486         kernel_stacks[boot_cpu_id]=(void *)init_user_stack;     /* Set up for boot processor first */
 487 
 488         smp_store_cpu_info(boot_cpu_id);                        /* Final full version of the data */
 489         
 490         active_kernel_processor=boot_cpu_id;
 491                 
 492         for(i=0;i<NR_CPUS;i++)
 493         {
 494                 if((cpu_present_map&(1<<i)) && i!=boot_cpu_id)          /* Rebooting yourself is a bad move */
 495                 {
 496                         unsigned long cfg;
 497                         int timeout;
 498                         
 499                         /*
 500                          *      We need a kernel stack for each processor.
 501                          */
 502                         
 503                         stack=get_kernel_stack();       /* We allocated these earlier */
 504                         if(stack==NULL)
 505                                 panic("No memory for processor stacks.\n");
 506                         kernel_stacks[i]=stack;
 507                         install_trampoline(stack);
 508                         
 509                         printk("Booting processor %d stack %p: ",i,stack);                      /* So we set whats up   */
 510                                 
 511                         /*
 512                          *      Enable the local APIC
 513                          */
 514                          
 515                         cfg=apic_read(APIC_SPIV);
 516                         cfg|=(1<<8);            /* Enable APIC */
 517                         apic_write(APIC_SPIV,cfg);
 518                         
 519                         /*
 520                          *      This gunge sends an IPI (Inter Processor Interrupt) to the
 521                          *      processor we wish to wake. When the startup IPI is received
 522                          *      the target CPU does a real mode jump to the stack base.
 523                          */
 524                         
 525                         cfg=apic_read(APIC_ICR2);
 526                         cfg&=0x00FFFFFF;
 527                         apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(i));                      /* Target chip          */
 528                         cfg=apic_read(APIC_ICR);
 529                         cfg&=~0xFDFFF   ;                                                       /* Clear bits           */
 530                         cfg|=APIC_DEST_FIELD|APIC_DEST_DM_STARTUP|(((unsigned long)stack)>>12); /* Boot on the stack    */              
 531                         apic_write(APIC_ICR, cfg);                                              /* Kick the second      */
 532                         udelay(10);                                                             /* Masses of time       */
 533                         cfg=apic_read(APIC_ESR);
 534                         if(cfg&4)               /* Send accept error */
 535                                 printk("Processor refused startup request.\n");
 536                         else
 537                         {
 538                                 for(timeout=0;timeout<50000;timeout++)
 539                                 {
 540                                         if(cpu_callin_map[0]&(1<<i))
 541                                                 break;                          /* It has booted */
 542                                         udelay(100);                            /* Wait 5s total for a response */
 543                                 }
 544                                 if(cpu_callin_map[0]&(1<<i))
 545                                         cpucount++;
 546                                 else
 547                                 {
 548                                         /*
 549                                          *      At this point we should set up a BIOS warm start and try
 550                                          *      a RESTART IPI. The 486+82489 MP pair don't support STARTUP IPI's
 551                                          */
 552                                         if(*((unsigned char *)8192)==0xA5)
 553                                                 printk("Stuck ??\n");
 554                                         else
 555                                                 printk("Not responding.\n");
 556                                         cpu_present_map&=~(1<<i);
 557                                 }
 558                         }
 559                 }
 560         }
 561         /*
 562          *      Allow the user to impress friends.
 563          */
 564         if(cpucount==0)
 565         {
 566                 printk("Error: only one processor found.\n");
 567                 cpu_present_map=(1<<smp_processor_id());
 568         }
 569         else
 570         {
 571                 unsigned long bogosum=0;
 572                 for(i=0;i<32;i++)
 573                 {
 574                         if(cpu_present_map&(1<<i))
 575                                 bogosum+=cpu_data[i].udelay_val;
 576                 }
 577                 printk("Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 
 578                         cpucount+1, 
 579                         (bogosum+2500)/500000,
 580                         ((bogosum+2500)/5000)%100);
 581                 smp_activated=1;
 582                 smp_num_cpus=cpucount+1;
 583         }
 584 }
 585 
 586 
 587 /*
 588  *      A non wait message cannot pass data or cpu source info. This current setup
 589  *      is only safe because the kernel lock owner is the only person who can send a message.
 590  *
 591  *      Wrapping this whole block in a spinlock is not the safe answer either. A processor may
 592  *      get stuck with irq's off waiting to send a message and thus not replying to the person
 593  *      spinning for a reply....
 594  *
 595  *      In the end invalidate ought to be the NMI and a very very short function (to avoid the old
 596  *      IDE disk problems), and other messages sent with IRQ's enabled in a civilised fashion. That
 597  *      will also boost performance.
 598  */
 599  
 600 void smp_message_pass(int target, int msg, unsigned long data, int wait)
     /* [previous][next][first][last][top][bottom][index][help] */
 601 {
 602         unsigned long cfg;
 603         unsigned long target_map;
 604         int p=smp_processor_id();
 605         int irq=0x2d;                                                           /* IRQ 13 */
 606         int ct=0;
 607         static volatile int message_cpu = NO_PROC_ID;
 608 
 609         /*
 610          *      During boot up send no messages
 611          */
 612          
 613         if(!smp_activated)
 614                 return;
 615                 
 616         
 617         /*
 618          *      Skip the reschedule if we are waiting to clear a
 619          *      message at this time. The reschedule cannot wait
 620          *      but is not critical.
 621          */
 622         
 623         if(msg==MSG_RESCHEDULE)                                                 /* Reschedules we do via trap 0x30 */
 624         {
 625                 irq=0x30;
 626                 if(smp_cpu_in_msg[p])
 627                         return;
 628         }
 629 
 630         /*
 631          *      Sanity check we don't re-enter this across CPU's. Only the kernel
 632          *      lock holder may send messages. For a STOP_CPU we are bringing the
 633          *      entire box to the fastest halt we can.. 
 634          */
 635          
 636         if(message_cpu!=NO_PROC_ID && msg!=MSG_STOP_CPU)
 637         {
 638                 panic("CPU #%d: Message pass %d but pass in progress by %d of %d\n",
 639                         smp_processor_id(),msg,message_cpu, smp_msg_id);
 640         }
 641         message_cpu=smp_processor_id();
 642         
 643 
 644         /*
 645          *      We are busy
 646          */
 647                 
 648         smp_cpu_in_msg[p]++;
 649         
 650         /*
 651          *      Reschedule is currently special
 652          */
 653          
 654         if(msg!=MSG_RESCHEDULE)
 655         {
 656                 smp_src_cpu=p;
 657                 smp_msg_id=msg;
 658                 smp_msg_data=data;
 659         }
 660         
 661 /*      printk("SMP message pass #%d to %d of %d\n",
 662                 p, msg, target);*/
 663         
 664         /*
 665          *      Wait for the APIC to become ready - this should never occur. Its
 666          *      a debugging check really.
 667          */
 668          
 669         while(ct<1000)
 670         {
 671                 cfg=apic_read(APIC_ICR);
 672                 if(!(cfg&(1<<12)))
 673                         break;
 674                 ct++;
 675                 udelay(10);
 676         }
 677         
 678         /*
 679          *      Just pray... there is nothing more we can do
 680          */
 681          
 682         if(ct==1000)
 683                 printk("CPU #%d: previous IPI still not cleared after 10mS", smp_processor_id());
 684                 
 685         /*
 686          *      Program the APIC to deliver the IPI
 687          */
 688          
 689         cfg=apic_read(APIC_ICR2);
 690         cfg&=0x00FFFFFF;
 691         apic_write(APIC_ICR2, cfg|SET_APIC_DEST_FIELD(target));                 /* Target chip                  */
 692         cfg=apic_read(APIC_ICR);
 693         cfg&=~0xFDFFF;                                                          /* Clear bits                   */
 694         cfg|=APIC_DEST_FIELD|APIC_DEST_DM_FIXED|irq;                            /* Send an IRQ 13               */              
 695 
 696         /*
 697          *      Set the target requirement
 698          */
 699          
 700         if(target==MSG_ALL_BUT_SELF)
 701         {
 702                 cfg|=APIC_DEST_ALLBUT;
 703                 target_map=cpu_present_map;
 704                 cpu_callin_map[0]=(1<<smp_src_cpu);
 705         }
 706         else if(target==MSG_ALL)
 707         {
 708                 cfg|=APIC_DEST_ALLINC;
 709                 target_map=cpu_present_map;
 710                 cpu_callin_map[0]=0;
 711         }
 712         else
 713         {
 714                 target_map=(1<<target);
 715                 cpu_callin_map[0]=0;
 716         }
 717                 
 718         /*
 719          *      Send the IPI. The write to APIC_ICR fires this off.
 720          */
 721          
 722         apic_write(APIC_ICR, cfg);      
 723         
 724         /*
 725          *      Spin waiting for completion
 726          */
 727          
 728         switch(wait)
 729         {
 730                 case 1:
 731                         while(cpu_callin_map[0]!=target_map);           /* Spin on the pass             */
 732                         break;
 733                 case 2:
 734                         while(smp_invalidate_needed);                   /* Wait for invalidate map to clear */
 735                         break;
 736         }
 737         
 738         /*
 739          *      Record our completion
 740          */
 741          
 742         smp_cpu_in_msg[p]--;
 743         message_cpu=NO_PROC_ID;
 744 }
 745 
 746 /*
 747  *      This is fraught with deadlocks. Linus does an invalidate at a whim
 748  *      even with IRQ's off. We have to avoid a pair of crossing invalidates
 749  *      or we are doomed.  See the notes about smp_message_pass.
 750  */
 751  
 752 void smp_invalidate(void)
     /* [previous][next][first][last][top][bottom][index][help] */
 753 {
 754         unsigned long flags;
 755         if(smp_activated && smp_processor_id()!=active_kernel_processor)
 756                 panic("CPU #%d:Attempted invalidate IPI when not AKP(=%d)\n",smp_processor_id(),active_kernel_processor);
 757 /*      printk("SMI-");*/
 758         
 759         /*
 760          *      The assignment is safe because its volatile so the compiler cannot reorder it,
 761          *      because the i586 has strict memory ordering and because only the kernel lock holder
 762          *      may issue an invalidate. If you break any one of those three change this to an atomic
 763          *      bus locked or.
 764          */
 765         
 766         smp_invalidate_needed=cpu_present_map&~(1<<smp_processor_id());
 767         
 768         /*
 769          *      Processors spinning on the lock will see this IRQ late. The smp_invalidate_needed map will
 770          *      ensure they dont do a spurious invalidate or miss one.
 771          */
 772          
 773         save_flags(flags);
 774         cli();
 775         smp_message_pass(MSG_ALL_BUT_SELF, MSG_INVALIDATE_TLB, 0L, 2);
 776         
 777         /*
 778          *      Flush the local TLB
 779          */
 780          
 781         local_invalidate();
 782         
 783         restore_flags(flags);
 784         
 785         /*
 786          *      Completed.
 787          */
 788          
 789 /*      printk("SMID\n");*/
 790 }
 791 
 792 /*      
 793  *      Reschedule call back
 794  */
 795 
 796 void smp_reschedule_irq(int cpl, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
 797 {
 798         static int ct=0;
 799         if(ct==0)
 800         {
 801                 printk("Beginning scheduling on CPU#%d\n",smp_processor_id());
 802                 ct=1;
 803         }
 804         
 805         if(smp_processor_id()!=active_kernel_processor)
 806                 panic("SMP Reschedule on CPU #%d, but #%d is active.\n",
 807                         smp_processor_id(), active_kernel_processor);
 808         /*
 809          *      Update resource usage on the slave timer tick.
 810          */
 811                         
 812         if (user_mode(regs)) 
 813         {
 814                 current->utime++;
 815                 if (current->pid) 
 816                 {
 817                         if (current->priority < 15)
 818                                 kstat.cpu_nice++;
 819                         else
 820                                 kstat.cpu_user++;
 821                 }
 822                 /* Update ITIMER_VIRT for current task if not in a system call */
 823                 if (current->it_virt_value && !(--current->it_virt_value)) {
 824                         current->it_virt_value = current->it_virt_incr;
 825                         send_sig(SIGVTALRM,current,1);
 826                 }
 827         } else {
 828                 current->stime++;
 829                 if(current->pid)
 830                         kstat.cpu_system++;
 831 #ifdef CONFIG_PROFILE
 832                 if (prof_buffer && current->pid) {
 833                         extern int _stext;
 834                         unsigned long eip = regs->eip - (unsigned long) &_stext;
 835                         eip >>= CONFIG_PROFILE_SHIFT;
 836                         if (eip < prof_len)
 837                                 prof_buffer[eip]++;
 838                 }
 839 #endif
 840         }
 841         /*
 842          * check the cpu time limit on the process.
 843          */
 844         if ((current->rlim[RLIMIT_CPU].rlim_max != RLIM_INFINITY) &&
 845             (((current->stime + current->utime) / HZ) >= current->rlim[RLIMIT_CPU].rlim_max))
 846                 send_sig(SIGKILL, current, 1);
 847         if ((current->rlim[RLIMIT_CPU].rlim_cur != RLIM_INFINITY) &&
 848             (((current->stime + current->utime) % HZ) == 0)) {
 849                 unsigned long psecs = (current->stime + current->utime) / HZ;
 850                 /* send when equal */
 851                 if (psecs == current->rlim[RLIMIT_CPU].rlim_cur)
 852                         send_sig(SIGXCPU, current, 1);
 853                 /* and every five seconds thereafter. */
 854                 else if ((psecs > current->rlim[RLIMIT_CPU].rlim_cur) &&
 855                         ((psecs - current->rlim[RLIMIT_CPU].rlim_cur) % 5) == 0)
 856                         send_sig(SIGXCPU, current, 1);
 857         }
 858 
 859         /* Update ITIMER_PROF for the current task */
 860         if (current->it_prof_value && !(--current->it_prof_value)) {
 861                 current->it_prof_value = current->it_prof_incr;
 862                 send_sig(SIGPROF,current,1);
 863         }
 864 
 865 
 866         /*
 867          *      Don't reschedule if we are in an interrupt...
 868          *      [This is test code and not needed in the end]
 869          */
 870          
 871 /*      if(intr_count==1)
 872         {*/
 873 
 874                 /*
 875                  *      See if the slave processors need a schedule.
 876                  */
 877 
 878                 if ( 0 > --current->counter || current->pid == 0) 
 879                 {
 880                         current->counter = 0;
 881                         need_resched=1;
 882                 }
 883 /*      }*/
 884 
 885         /*
 886          *      Clear the IPI
 887          */
 888         apic_read(APIC_SPIV);           /* Dummy read */
 889         apic_write(APIC_EOI, 0);        /* Docs say use 0 for future compatibility */
 890 }       
 891 
 892 /*
 893  *      Message call back.
 894  */
 895  
 896 void smp_message_irq(int cpl, struct pt_regs *regs)
     /* [previous][next][first][last][top][bottom][index][help] */
 897 {
 898         int i=smp_processor_id();
 899 /*      static int n=0;
 900         if(n++<NR_CPUS)
 901                 printk("IPI %d->%d(%d,%ld)\n",smp_src_cpu,i,smp_msg_id,smp_msg_data);*/
 902         switch(smp_msg_id)
 903         {
 904                 case 0: /* IRQ 13 testing - boring */
 905                         return;
 906                         
 907                 /*
 908                  *      A TLB flush is needed.
 909                  */
 910                  
 911                 case MSG_INVALIDATE_TLB:
 912                         if(clear_bit(i,&smp_invalidate_needed))
 913                                 local_invalidate();
 914                         set_bit(i, &cpu_callin_map[0]);
 915                         cpu_callin_map[0]|=1<<smp_processor_id();
 916                         break;
 917                         
 918                 /*
 919                  *      Halt other CPU's for a panic or reboot
 920                  */
 921                 case MSG_STOP_CPU:
 922                         while(1)
 923                         {
 924                                 if(cpu_data[smp_processor_id()].hlt_works_ok)
 925                                         __asm__("hlt");
 926                         }
 927                 default:
 928                         printk("CPU #%d sent invalid cross CPU message to CPU #%d: %X(%lX).\n",
 929                                 smp_src_cpu,smp_processor_id(),smp_msg_id,smp_msg_data);
 930                         break;
 931         }
 932         /*
 933          *      Clear the IPI, so we can receive future IPI's
 934          */
 935          
 936         apic_read(APIC_SPIV);           /* Dummy read */
 937         apic_write(APIC_EOI, 0);        /* Docs say use 0 for future compatibility */
 938 }

/* [previous][next][first][last][top][bottom][index][help] */